IMT Preliminary Specification IM29LV001T and IM29LV001B 1 M Bit (128K x 8) 3.3V-Only Flash Memory Features: • • • • • • • • 0.40 µm, triple-poly double-metal CMOS process Single power supply operation 3.3V ± 10% for both read and write High endurance > 10,000 program/erase cycles Fast read access time 70 and 90 ns Single page erasability for optimal data alterability Page size: 512 bytes Hardwired data protection Inhibits program and erase operations of the top (IM29LV001T) or bottom (IM29LV001B) 32 pages of the array for false write and virus prevention. Flexible boot block configurability Fast program and erase operations: Byte program : < 35 µsec typical • • • • • Page erase : < 7 msec typical Chip erase : < 2 sec typical Self-timed program/erase operations with end-of-cycle detection Data# Polling and Toggle Bit Inadvertent write protection Glitch filtering for WE# and CE# Low Vcc (< 2.2 V ) write inhibit Hardwired data protection Low Icc for power conservation Read: 6 ma typical Write: 10 ma typical Stand-by: 10 µA typical Compatible with JEDEC byte wide pinout and single-supply flash command standards Package types: 32-pin PLCC, TSOP and PDIP Others available upon request General Descriptions The IM29LV001T/B is a 1 Mega-bit, 5V-only page erasable flash memory organized as 128K X 8 bits.It is manufactured with IMT’s proprietary double metal, 0.40 µm CMOS flash technology. High performance cell design and advanced process technology attain better reliability, manufacturability, circuit performance and future scaleability than other alternative approaches. Fast, self-timed program/erase operations are made possible with an innovative cell and array architecture which is free from the over-erase problem of the traditional stacked-gate structures. to other large-erase-block based products for direct replacement. flash Single page (512 bytes) data alterability ensures optimum flexibility and efficiency in program codes, parameters and data storage. It also allows backward compatibility Designed, manufactured and tested for extended endurance applications, the IM29LV001 is specified for more than 10 4 cycling endurance and greater than 10 years of data retention. The IM29LV001T/B is designed with interface features for direct in-system programming and erase operations. Vendor re-programmable, hardwired data protection is provided for absolute prevention in inadvertent data alteration and virus infection. The IM29LV001 conforms to the JEDEC byte wide memory pin-out and single supply flash command standards. This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 IMT Preliminary Specification Pin-out Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N/C A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc WE N/C A14 A13 A8 A9 A11 OE A12 A15 A16 N/C Vcc WE N/C A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ1 DQ2 Vss DQ3 DQ4 DQ5 DQ6 32-pin PDIP A11 A9 A8 A13 A14 N/C WE Vcc N/C A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin PLCC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard 32-pin TSOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Reverse 32-pin TSOP Block Diagram OE WE CE Control Signal Inputs and Logic A0 Address Input and Pre-decorder A16 DQ0 I/O Buffer and Data Latch Command Logic and State Machine High Voltage Generators and Logic X-Dec Flash Cell Array Y-Dec Y-Gating DQ7 This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 A11 A9 A8 A13 A14 NC WE Vcc N/C A16 A15 A12 A7 A6 A5 A4 IMT Preliminary Specification Flexible Boot Block Architecture The page erase function of IM29LV001T/B erases only the bytes located inside the 512byte boundary (as defined by A9 - A16) of the selected page. It does not affect any other memory location outside of the page boundary. Any page of the array can be used as an independent data storage unit which is not affected by the erase and programming operations of the rest of the array. A boot block of any size can be constructed by selecting a contiguous, or non-contiguous if so desired, group of pages from the top or bottom address. This provides the most convenient boot block configuration than those utilizing the fixedsize boot block approach. Hard Wired Data Protection A hard wired data protection option is provided for the first 32 pages either from the top address (IM29LV001T) or from the bottom address (IM29LV001B). This option can be utilized to protect the BIOS boot codes which usually reside in the top or bottom 16K-byte address range. Device Operation Read The read operation of the IM29LV001T/B is activated by setting CE# and OE# to low (VIL) and WE# to high (VIH). Data is obtained from the output pins. CE# controls the device selection function. When CE# is high, the device is deselected and only standby power is consumed. When CE# is low, the device is selected. OE# controls the output buffer. It is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. See Fig. 1 for the read cycle timing diagram. Write The write operation is used to issue commands and data for the program and erase functions of the device. It is initiated by forcing CE# low, OE# high and WE# low. The addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. See Fig. 2 for the timing diagram of writing a command with WE# as the controlling signal, and Fig. 3 for that with CE# as the controlling signal. Erase: Page and Chip Erase The IM29LV001T/B provides two erase functions: page erase and chip erase. The page erase function erases a single page (512 bytes in size) at a time. It is activated by writing the page erase command to the part. The page erase command is consisted of 6 write cycles as shown in Table 2. The first 5 cycles contain the command codes, while the 6th cycle asserts the page address (A9 to A16) by forcing the correct address signals to the address pins. See Fig. 9 for the flow chart and Fig. 5 for the page erase timing diagram. The chip erase function erases the complete 1 mega-bit array simultaneously. It is activated by a 6-byte command cycle shown in Table 2. See Fig. 6 for the timing diagram and Fig. 10 for the flow chart. The page and chip erase operations, once initiated, will trigger an internal timer to start the erase operation until completion, which takes typically 6 ms for the page and 2 sec for the chip erase. During this period, the data and address buses of the part are in high impedance states. The system buses OPERATION CE# OE# WE# A0 Note 1 Read VIL VIL VIH Ain Standby VIH X X X Output Disable VIL VIH VIH X Note 1 Write VIL VIH VIL Ain Note 1 VIL X Enable Hardwired Data Protect VIL VH Note 1 Disable Hardwired Data Protect VH VH VIL X Verify Hardwired Data Protect VIL VIL VIH VIL Product Identification Manufacturer ID Byte 1 VIL VIL VIH VIL Byte 2 VIL VIL VIH VIH Device ID VIL VIL VIH VIH Note 1: VH=12 V, Ain = address input, X = don’t care. Note 2: A5H for IM29LV001T and A6H for IM29LV 001B Table 1 Operation Modes A1 Note 1 Ain X X Note 1 Ain X X VIH A9 Note 1 Ain X X Note 1 Ain Note 1 VH Note 1 VH Note 1 VH VIL VIH VIL VH Note 1 VH Note 1 VH Note 1 I/O DOUT HIGHZ HIGHZ DIN X X CODE 7FH 1FH Note 2 A5H/A6H This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 IMT Preliminary Specification Data# Polling (DQ7) are free for other operations. Program Byte program operation is initiated by issuing a program command which is consisted of 4 write cycles as shown in Table 2. The first 3 cycles contain the command codes and the 4th cycle asserts the byte address and data. See Fig. 11 for the flow chart and Fig. 4 for the timing diagram. The program operation, once initiated, will continue internally until completion, typically within 20 µs. During the byte programming period, the data and address buses of the part are in high impedance state. The system buses are free for other operations. For example, during the byte programming period, the host is free to perform other tasks, such as to fetch data from other locations in the system for the next byteprogram operation. Program/Erase Status Detection: Data# Polling and Toggle Bit The IM29LV001T/B provides two status bits for detecting the completion of a program or erase period. They are the Data# Polling (DQ7) and Toggle (DQ6) bits. During the program or erase operation, the only valid read operations of the part are to read Data# Polling and Toggle Bits. Both bits are enabled and can be detected after the program or erase cycle is initiated by the first rising edge of WE# or CE# signal. See Fig. 7 and 8 for the timing diagrams and Fig. 9, 10 and 11 for the flow charts representation of the usage of Data# Polling and Toggle Bit in page erase, chip erase and byte program operations. Command First Cycle Add Data xxxxH F0H 5555H AAH 5555H AAH 5555H AAH 5555H AAH Second Cycle Add Data Read Reset/ Read 2AAAH Program 2AAAH Page Erase 2AAAH Chip Erase 2AAAH Product Identification Manufacturer ID Byte 1 5555H AAH 2AAAH Byte 2 5555H AAH 2AAAH Device ID 5555H AAH 2AAAH Note: A5H for IM29LV001T and A6H for IM29LV001B When the IM29LV001T/B is in the program or erase period, any attempt to read DQ7 will receive the complement of the intended data of the program or erase operation. Once the program or erase cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Fig. 7 for Data# Polling timing diagram. Toggle Bit (DQ6) During the program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0’s and 1’s. It will start with “0” and then toggle between “0” and “1”. When the program or erase cycle is completed, the toggling action will stop. The device is then ready for the next operation. See Fig. 8 for Toggle Bit timing diagram. Data Protection The IM29LV001T/B provides both hardware and software features to protect nonvolatile data from inadvertent writes. Optional Hardwired data protection for selected sectors: The program and erase operations of the first (IM29LV001T) or last (IM29LV001B) 32 pages can be disabled permanently to prevent false write and/or virus infection. As shown in Table 1, the hardwired protection mode can be enabled by applying VH, or 12 Volt, to A9 and OE#, and VIL to CE# and WE#. The mode can be disabled by applying the same voltages to the above pins except CE#, where V H is applied. To verify the status of the hardwired data protection mode, A9 is set to VH ( or 12 Volt), CE#, OE# and A0 to VIL, and WE# and A1 to VIH. If D0 = “1” then the hardwired data protection mode is enabled. Or vice versa, if D0 = “0”. The status of the hardwired data Third Cycle Add Data Fourth Cycle Add Data 55H 55H 55H 55H 5555H 5555H 5555H 5555H F0H A0H 80H 80H Byte Add Byte Data Byte Add Byte Data 5555H 5555H AAH AAH 55H 55H 55H 5555H 5555H 5555H 90H 90H 90H xx00H xx11H xx01H 7FH 1FH Note A5H/A6H Fifth Cycle Add Data 2AAAH 2AAAH 55H 55H Table 2 Command Definitions This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 Sixth Cycle Add Data Page Add 5555H 30H 10H IMT Preliminary Specification Command Read Hardwired Protection Status Bit First Cycle Add 5555H Data AAH Second Cycle Add 2AAAH Data 55H Third Cycle Add 5555H Data 90H Fourth Cycle Add A16 - A2 A1 Don’t Care 1 A0 0 Data/Status Protected: D0 = 1, D7-1=Don’t Care Unprotected: D0 = 0, D7-1=Don’t Care Table 3 Hardwired Protection Status Bit Read Command protection mode can also be verified by software means. See Table 3 for the command code to access the status bit of the top and bottom sector. The hardwired data protection mode can not be disabled by software means, however. Noise/Glitch Protection: A WE# or CE# noise glitch of less than 5 ns will not initiate a program or erase cycle. VCC Power Up/Down Detection: The program or erase operation is inhibited when VCC is less than 3.5V. Write Inhibit Mode: The program or erase operation is inhibited if any one of the following conditions is enforced: OE# low, CE# high, or WE# high. This prevents inadvertent data alterations during power-up or power-down period. Product Identification The product identification mode identifies the device as the IM29LV001T/B and the manufacturer as IMT. This mode may be accessed by hardware or software operations. They are typically used by a Flash Memory programmer to identify the IMT IM29LV001T/B device and apply the correct algorithm to program the data. See Table 1 for hardware operation or Table 2 for software operation codes. The manufacturer ID for IMT is consisted of two bytes. The first byte is 7F which is located at A0=0 and A1=0. The second byte is 1F, located at A0=1 and A1=1. The device ID is A1, located at A1=0 and A0=1. See Table 4 Byte 1 Byte 2 Address Data Address Data ID Type A16-2 A1 A0 A16-2 A1 A0 Manufacturer ID X 0 0 7FH X 1 1 1FH Note Device ID X 0 1 A5H/A6H Not Applicable Note: A5H for IM29LV001T and A6H for IM29LV001B Table 4 Product Identification Table for manufacturer and device ID designations. Termination of Product Identification Mode To return to the standard read mode, the Software Product Identification mode must be terminated. It is accomplished by issuing the Reset/Read operation, which returns the device to the read operation. See Table 2 for the Reset/Read command codes. This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 IMT Preliminary Specification Absolute Maximum Ratings Operating Ranges Storage temperature…… -65°C to +150 °C Ambient temperature with power applied…………………….-65°C to +125°C Voltage with respect to ground Vcc……………………….. -0.5 V to 3.6 V A9 …………………….. -0.5 V to +12.5 V All the other pins… -0.5 V to Vcc + 0.5 V Ambient Temperature : Commercial ( C ) Devices…0 °C to 70 °C Industrial ( I ) Devices……-40 °C to +85 °C Extended ( E ) Devices… -55 °C to 125 °C Vcc Supply Voltages : 3.0 V to 3.6 V DC Parameters: Symbol ICC Parameter Min Power Supply Current Read Write Standby Power Supply Current TTL input CMOS input ISB1 ISB2 Limits Max Units 10 mA 15 mA 1 15 mA µA Test Conditions CE#=OE#=VIL,WE#=VIH , all I/Os open, Address input = VIL/VIH, at f=1/TRC, Min., VCC=VCC, Max CE#=WE#=VIL, OE#=VIH, VCC = VCC, Max. CE# = VIH, VCC = VCC, Max. CE# = VCC -0.3V, VCC = VCC, Max. ILI Input Leakage Current 1 µA VIN =GND to VCC, VCC = VCC, ILO Output Leakage Current 10 µA VOUT =GND to VCC , VCC = VCC, VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 0.8 V V V V VH High voltage input for Product ID and Hardwired Data Protection modes High voltage input for Product ID and Hardwired Data Protection modes IH . Max 12.5 V VCC = VCC, Max. VCC = VCC, Max. IOL = 2.1 mA, VCC = VCC, Min. IOH = -400µA, VCC = VCC, Min. CE# = OE# =VIL, WE# = VIH 50 µA CE# = OE# = VIL, WE# = VIH, A9 = VH, 2.0 0.4 2.4 11.5 . Max . Max AC Parameters: a) Read Characteristics: Parameter tRC tAA tCE tOE tCLZ tOLZ tCHZ tOHZ tOH Description Read cycle time Address to output delay CE# to output delay OE# to output delay CE# low to output active OE# low to output active CE# high to output at high-Z OE# high to output at high-Z Output hold from address change IM29LV00155 Min Max 55 55 55 25 0 0 20 20 0 IM29LV00170 Min Max 70 70 70 35 0 0 30 30 0 IM29LV00190 Min Max 90 90 90 45 0 0 40 40 0 IM29LV001120 Min Max 120 120 120 60 0 0 50 50 0 This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 Unit ns ns ns ns ns ns ns ns ns IMT Preliminary Specification b) Write Characteristics: Parameter Description tWC tAS tAH tDS tDH tOES tOEH tCS tCH tCP tCPH tWS tWH tWP tWPH Write command cycle time Address setup time Address hold time Data setup time Data hold time OE# setup time OE# hold time CE# setup time CE# hold time CE# write pulse width CE# write pulse width high WE# setup time WE# hold time WE# write pulse width WE# write pulse width high Byte programming time Page erase time Chip erase time CE# access time for Data# Polling and Toggle bit read OE# access time for Data# Polling and Toggle bit read tWHWH1 tWHWH2 tWHWH3 tCEP tOEP IM29LV001-55 Min Max 55 0 35 20 0 0 0 0 0 25 20 0 0 25 20 30 9 3 55 25 IM29LV001-70 Min Max 70 0 45 30 0 0 0 0 0 35 30 0 0 35 30 30 9 3 70 IM29LV001-90 IM29LV001-120 Min Max Min Max 90 120 0 0 55 60 40 45 0 0 0 0 0 0 0 0 0 0 45 50 30 35 0 0 0 0 45 50 30 35 30 30 9 9 3 3 90 120 35 45 60 Test Conditions Input rise and fall time ……………………………… 5 ns Input pulse levels……………………………………. 0.0 V to 3.0 V Timing measurement reference level Input…………………………………………. 1.5 V Output……………………………………….. 1.5 V Output loading 55ns and 70 ns parts…………………….. 1 TTL load + 30 pF 90 ns and 120 ns parts…………………… 1 TTL load + 100 pF This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ms s ns ns IMT Preliminary Specification tRC ADDRESS t CE CE tOE OE VIH t CLZ tOLZ WE DQ t OHZ t HIGH Z t CHZ OH DATA VALID DATA VALID t AA Fig. 1 Read Cycle Timing Diagram t AS t AH ADDRESS t CS CE t CH t OES t OEH OE t WP t WPH WE t DS DQ HIGH Z DATA VALID t DH Fig. 2 WE Controlled Command Write Timing Diagram This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 IMT Preliminary Specification t AH t AS ADDRESS t CP CE t CPH t OES t OEH OE t WS tWH WE t DS DQ HIGH Z DATA VALID t DH Fig. 3 CE Controlled Command Write Timing Diagram THREE-BYTE COMMAND CODE FOR BYTE PROGRAMMING MODE ADDRESS DQ 5555 2AAA 5555 AA 55 A0 DATA BYTE Add Data CE OE t WP WE t WC tW H W H 1 t WPH Internal Programming Start Fig. 4 Byte Programming Mode Timing Diagram This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 IMT Preliminary Specification SIX-BYTE COMMAND CODE FOR PAGE ERASE OPERATION ADDRESS DQ 5555 2AAA AA 5555 55 80 5555 AA 2AAA Page Address 55 30 CE OE t WP WE t WHWH2 t WC t WPH Internal Erase Start Fig. 5 Page Erase Timing Diagram SIX-BYTE COMMAND CODE FOR CHIP ERASE OPERATION ADDRESS DQ 5555 2AAA 5555 55 AA 80 5555 AA 2AAA 55 5555 10 CE OE t WP WE t WC t WHWH3 t WPH Internal Erase Start Fig. 6 Chip Erase Timing Diagram This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 IMT Preliminary Specification ADDRESS WE t CEP CE t OEH OE DQ7 t OES t OEP X X X X t WHWH1,2,or 3 Fig. 7 Data Polling Timing Diagram ADDRESS WE t CEP CE tOES tOEH OE t OEP DQ6 X t WHWH1,2,or 3 Fig. 8 Toggle Bit Timing Diagram This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 IMT Preliminary Specification Start 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H Page Address/30H No Time Out For t WHWH2? No Data# Polling: DQ7=Data? No Toggle Bit: DQ6 stops toggling? Yes Yes Yes Page Erase Completion Page Erase Completion Page Erase Completion Fig. 9 Page Erase Flow Chart This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 IMT Preliminary Specification Start 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H 5555H/10H No Time Out For t WHWH3? No Data# Polling: DQ7=Data? No Toggle Bit: DQ6 stops toggling? Yes Yes Yes Chip Erase Completion Chip Erase Completion Chip erase Completion Fig. 10 Chip Erase Flow Chart This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696 IMT Preliminary Specification Start 5555H/AAH 2AAAH/55H 5555H/A0H Program Byte Address/Data No Time Out For t WHWH1? No Data# Polling: DQ7=Data? No Toggle Bit: DQ6 stops toggling? Yes Yes Yes Byte Program Completion Byte Program Completion Byte Program Completion Fig. 11 Byte Program Flow Chart This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696