ISSI IS62C1024L

ISSI
®
IS62C1024L
128K x 8 LOW POWER CMOS STATIC RAM
DECEMBER 2003
FEATURES
• High-speed access time: 35, 70 ns
• Low active power: 450 mW (typical)
• Low standby power: 150 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
DESCRIPTION
The ISSI IS62C1024L is a low power,131,072-word by 8-bit
CMOS static RAM. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields higher
performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the
device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs, CE1 and CE2. The active LOW Write
Enable (WE) controls both writing and reading of the
memory.
The IS62C1024L is available in 32-pin plastic SOP and
TSOP (type 1) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
CE1
CE2
OE
WE
CONTROL
CIRCUIT
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
1
ISSI
IS62C1024L
PIN CONFIGURATION
PIN CONFIGURATION
32-Pin SOP
32-Pin TSOP (Type 1)
NC
1
32
VDD
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE
A7
5
28
A13
A6
A5
6 62C1024L 27
26
7
A4
8
25
A11
A3
9
24
OE
A2
10
23
A10
A1
11
22
CE1
A0
12
21
I/O7
I/O0
13
20
I/O6
I/O1
14
19
I/O5
I/O2
15
18
I/O4
GND
16
17
I/O3
ISSI
A11
A9
A8
A13
WE
CE2
A15
VDD
NC
A16
A14
A12
A7
A6
A5
A4
A8
A9
PIN DESCRIPTIONS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
®
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
OPERATING RANGE
A0-A16
Address Inputs
Range
CE1
Chip Enable 1 Input
Commercial
CE2
Chip Enable 2 Input
Industrial
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
VDD
Power
GND
Ground
Ambient Temperature
VDD
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
2
WE
CE1
CE2
OE
X
X
H
H
L
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
I/O Operation
High-Z
High-Z
High-Z
DOUT
DIN
VDD Current
ISB1, ISB2
ISB1, ISB2
ICC
ICC
ICC
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
ISSI
IS62C1024L
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
1.5
20
Unit
V
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
VDD = Min., IOH = –1.0 mA
VDD = Min., IOL = 2.1 mA
Output Leakage
GND ≤ VOUT ≤ VDD
—
0.4
VDD + 0.5
0.8
2
10
2
10
V
V
V
V
µA
ILO
2.4
—
2.2
–0.3
–2
–10
–2
–10
GND ≤ VIN ≤ VDD
Com.
Ind.
Com.
Ind.
µA
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
3
ISSI
IS62C1024L
®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-35 ns
Min. Max.
-70 ns
Min. Max.
Symbol
Parameter
Test Conditions
Unit
ICC
VDD Dynamic Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
100
110
—
—
70
80
mA
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL, CE1 ≥ VIH,
or CE2 ≤ VIL, f = 0
Com.
Ind.
—
—
10
15
—
—
10
15
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
Com.
CE1 ≤ VDD – 0.2V,
Ind.
CE2 ≤ 0.2V, VIN ≥ VDD – 0.2V,
or VIN ≤ 0.2V, f = 0
—
—
500
750
—
—
500
750
µA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
-35
Min. Max.
-70
Min.
Max.
Unit
tRC
Read Cycle Time
35
—
70
—
ns
tAA
Address Access Time
—
35
—
70
ns
tOHA
Output Hold Time
3
—
3
—
ns
tACE1
CE1 Access Time
—
35
—
70
ns
tACE2
CE2 Access Time
—
35
—
70
ns
tDOE
OE Access Time
—
10
—
35
ns
OE to Low-Z Output
0
—
0
—
ns
OE to High-Z Output
0
10
0
25
ns
tLZCE1(2)
CE1 to Low-Z Output
3
—
10
—
ns
tLZCE2
CE2 to Low-Z Output
3
—
10
—
ns
tHZCE
CE1 or CE2 to High-Z Output
0
10
0
25
ns
tLZOE
(2)
tHZOE
(2)
(2)
(2)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
ISSI
IS62C1024L
®
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
5 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
100 pF
Including
jig and
scope
255 Ω
5 pF
Including
jig and
scope
Figure 1a.
255 Ω
Figure 1b.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
tRC
ADDRESS
tAA
tOHA
DOUT
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
tOHA
DATA VALID
5
ISSI
IS62C1024L
®
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tHZOE
tDOE
CE1
tLZOE
tACE1/tACE2
CE2
tLZCE1/
tLZCE2
DOUT
tHZCE
HIGH-Z
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power)
Symbol
Parameter
-35
Min. Max.
-70
Min.
Max.
Unit
tWC
Write Cycle Time
35
—
70
—
ns
tSCE1
CE1 to Write End
25
—
60
—
ns
tSCE2
CE2 to Write End
25
—
60
—
ns
tAW
Address Setup Time to Write End
25
—
60
—
ns
tHA
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
tPWE
WE Pulse Width
25
—
50
—
ns
tSD
Data Setup to Write End
20
—
30
—
ns
tHD
Data Hold from Write End
0
—
0
—
ns
tHZWE(2)
WE LOW to High-Z Output
—
10
—
25
ns
tLZWE
WE HIGH to Low-Z Output
3
—
5
—
ns
tSA
(4)
(2)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
ISSI
IS62C1024L
®
AC WAVEFORMS
WE Controlled)(1,2)
WRITE CYCLE NO. 1 (WE
tWC
ADDRESS
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE(4)
WE
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
CE1
WRITE CYCLE NO. 2 (CE1
CE1, CE2 Controlled)(1,2)
tWC
ADDRESS
tSA
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE(4)
WE
tHZWE
DOUT
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
7
ISSI
IS62C1024L
®
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
VDR
VDD for Data Retention
See Data Retention Waveform
2.0
IDR
Data Retention Current
VDD = 3.0V, CE1 ≥ VDD – 0.2V
tSDR
Data Retention Setup Time
See Data Retention Waveform
tRDR
Recovery Time
See Data Retention Waveform
Com.
Ind.
Max.
Unit
5.5
V
250
400
µA
0
—
ns
tRC
—
ns
—
—
Typ.
45
60
CE1 Controlled)
DATA RETENTION WAVEFORM (CE1
Data Retention Mode
tSDR
tRDR
VDD
4.5V
2.2V
VDR
CE1 ≥ VDD - 0.2V
CE1
GND
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode
VDD
4.5V
CE2
2.2V
tSDR
tRDR
VDR
0.4V
CE2 ≤ 0.2V
GND
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
ISSI
IS62C1024L
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part No.
Package
35
35
IS62C1024L-35Q
IS62C1024L-35T
Plastic SOP
TSOP, Type 1
70
70
IS62C1024L-70Q
IS62C1024L-70T
Plastic SOP
TSOP, Type 1
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
35
35
IS62C1024L-35QI
IS62C1024L-35TI
Plastic SOP
TSOP, Type 1
70
70
IS62C1024L-70QI
IS62C1024L-70TI
Plastic SOP
TSOP, Type 1
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
9
ISSI
®
PACKAGING INFORMATION
450-mil Plastic SOP
Package Code: Q (32-pin)
N
E1
E
1
D
SEATING PLANE
A
S
MILLIMETERS
Symbol
No. Leads
A
A1
B
C
D
E
E1
e
L
α
S
Min.
L
B
e
A1
INCHES
Max.
Min.
Max.
32
—
3.00
0.10
—
0.36
0.51
0.15
0.30
20.14
20.75
13.87
14.38
11.18
11.43
1.27 BSC
0.58
0.99
0°
10°
—
0.86
—
0.118
0.004
—
0.014
0.020
0.006
0.012
0.793
0.817
0.546
0.566
0.440
0.450
0.050 BSC
0.023
0.039
0°
10°
—
0.034
α
C
Notes:
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect to
one another within 0.004 inches at the
seating plane.
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/13/03
ISSI
PACKAGING INFORMATION
®
Plastic TSOP-Type I
Package Code: T (32-pin)
1
E
H
N
D
SEATING PLANE
A
S
MILLIMETERS
Symbol
No. Leads
A
A1
B
C
D
E
H
e
L
α
S
Min.
L
B
e
A1
INCHES
Max.
Min.
Max.
32
—
1.20
0.05
0.25
0.17
0.23
0.12
0.17
7.90
8.10
18.30
18.50
19.80
20.20
0.50 BSC
0.40
0.60
0°
8°
0.25 REF
—
0.047
0.002
0.010
0.007
0.009
0.005
0.007
0.311
0.319
0.720
0.728
0.780
0.795
0.020 BSC
0.016
0.024
0°
8°
0.010 REF
α
C
Notes:
1. Controlling dimension: millimeters, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect
to one another within 0.004 inches at the
seating plane.
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/13/03