SAMSUNG K4C561638C-TCD3

K4C5608/1638C
256Mb Network-DRAM
256Mb Network-DRAM Specification
Version 0.7
- 1 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Revision History
Version 0.0 (Oct. / 5 / 2001)
- First Release
Version 0.1 (Dec. / 15 / 2001)
- The product name is changed to Network-DRAM
Version 0.2 (Jan. / 21 / 2002)
- M-version is renamed to C-version
- Specify DC operating condition values
- Added Power Up Sequence and Power Down(CL=4) Timing Diagrams
Version 0.3 (Mar. / 23 / 2002)
- The product name is changed to Network RAM
- Added Speed bin (366Mbps/pin,183MHz)
Version 0.4 (May. / 01 / 2002)
- The product name is changed to Network-DRAM
- Redefined IDD1S, IDD5 in DC Characteristic
Version 0.5 (Nov. /23 / 2002)
-Updated the current spec. value
Version 0.6 (Apr. /9 / 2003)
-Changed IDD2P value from 2mA to 3mA in page 10.
-Changed capacitance of DQ/DQS
Unit: pF
From
Capacitance(DQ/DQS)
To
Min
Max
Min
Max
4.0
6.0
3.0
6.0
Version 0.7 (Aug.31 / 2003)
-Changed tCK max like below
From
To
D4
DA
D3
D4
DA
D3
8.5
12
12
7.5
7.5
7.5
- 2 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
General Information
Organization
D4 (400Mbps)
DA (366Mbps )
D3 (333Mbps )
256Mx8
K4C560838C-TCD4
K4C560838C-TCDA
K4C560838C-TCD3
256Mx16
K4C561638C-TCD4
K4C561638C-TCDA
K4C561638C-TCD3
1
2
3
4
5
6
7
8
9
10
11
K 4 C XX XX X X X - X X XX
Memory
Speed
DRAM
Temperature & Power
Small Classification
Package
Density and Refresh
Version
Organization
Bank
Interface (VDD & VDDQ)
1. SAMSUNG Memory : K
8. Version
C : 4th Generation
2. DRAM : 4
3. Small Classification
C : Network-DRAM
9. Package
T : TSOP II (400mil x 875mil)
4. Density & Refresh
56 : 256M 8K/64ms
10. Temperature & Power
C : (Commercial, Normal)
5. Organization
08 : x8
16 : x16
11. Speed
D4 : 400bps/pin (200MHz, CL=4)
DA : 366bps /pin (183MHz, CL=4)
D3 : 333bps/pin (167MHz, CL=4)
6. Bank
3 : 4 Bank
7. Interface (VDD & VDDQ)
8: SSTL-2(2.5V, 2.5V)
- 3 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Key Feature
K4C560838/1638C-TC
Item
tCK Clock Cycle Time (Min.)
D4 (400Mbps)
DA (366Mbps)
D3 (333Mbps)
CL=3
5.5ns
6ns
6.5ns
CL=4
5ns
5.5ns
6ns
25ns
27.5ns
30ns
tRC Random Read/Write Cycle Time (Min.)
tRAC Random Access Time (Max.)
22ns
24ns
26ns
310mA
300mA
290mA
IDD2P Power Down Current (Max.)
2mA
2mA
2mA
IDD6 Self-Refresh Current(Max.)
3mA
3mA
3mA
IDD1S Operating Current (Single bank) (Max.)
• Fully Synchronous Operation
Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
Differential Clock (CK and CK)inputs
CS, FN and all address input signals are sampled on the positive edge of CK.
Output data (DQs and DQS) is referenced to the crossings of CK and CK.
• Fast clock cycle time of 5ns minimum Clock : 200MHz maximum
Data : 400Mbps/pin maximum
• Quad independent banks operation
• Fast cycle and short Iatency
• Bidirectional data strobe signal
• Distributed Auto-Refresh cycle in 7.8us
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency - 1
• Programmable CAS Latency and Burst Length
CAS Latency = 3, 4
Burst Length = 2, 4
• Organization K4C561638C-TC : 4,194,304 words x4 banks x 16
K4C560838C-TC : 8,388,608 words x4 banks x 8
• Power supply voltage Vdd : 2.5 ± 0.15V
VddQ : 2.5 ± 0.15V
• 2.5V CMOS I/O comply with SSTL-2 (Strong / Normal / Weaker / Weakest)
• Package 400X875mil, 66pin TSOP II, 0.65mm pin pitch (TSOP II 66-P-400-0.65)
- 4 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Pin Assignment (Top View)
Pin Names
K4C561638C-TC
Pin
Name
A0 to A14
Address Input
BA0, BA1
Bank Address
DQ0 to DQ7 (x8)
DQ0 to DQ15 (x16)
Data Input/Output
CS
Chip Select
FN
Function Control
PD
Power Down Control
CK, (CK)
Clock Input
DQS (X8)
Write/Read Data Strobe
UDQS/LDQS (X16)
Vdd
Power(+2.5V)
Vss
Ground
VddQ
Power (+2.5V)
(for I/O buffer)
VssQ
Ground
(for I/O buffer)
VREF
Reference Voltage
NC1,NC2
No Connection
K4C560838C-TC
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
NC1
VddQ
LDQS
NC1
Vdd
NC1
NC2
A14
A13
FN
CS
NC1
BA0
BA1
A10
A0
A1
A2
A3
Vdd
- 5 -
Vdd
DQ0
VddQ
NC2
DQ1
VssQ
NC2
DQ2
VddQ
NC2
DQ3
VssQ
NC2
NC1
VddQ
NC2
NC1
Vdd
NC1
NC2
A14
A13
FN
CS
NC1
BA0
BA1
A10
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
400mil Width
875mil Length
66Pin TSOP II
0.65mm
Lead Pitch
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
Vss
DQ7
VssQ
NC2
DQ6
VddQ
NC2
DQ5
VssQ
NC2
DQ4
VddQ
NC2
NC1
VssQ
DQS
NC1
VREF
Vss
NC2
CK
CK
PD
NC1
A12
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
NC1
VssQ
UDQS
NC1
VREF
Vss
NC2
CK
CK
PD
NC1
A12
A11
A9
A8
A7
A6
A5
A4
Vss
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Package Outline Drawing (TSOP II 66-P-400-0.65)
0.1 ± 0.05
± 0.1
0.1
- 6 -
0.5 ± 0.1
0 ~ 10×
1 ± 0.1
22.62 MAX
22.22
33
0.13 M
0.145 ± 0.055
+ 0.08
0.24 - 0.07
0.65
1.2 MAX
1
0.71TYP
11.76 ± 0.2
34
10.16 ± 0.1
66
Unit in mm
0.8 ± 0.2
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Block Diagram
CK
DLL
CK
CLOCK
PD
BUFFER
To Each Block
BANK #3
COMMAND
FN
DECODER
SIGNAL
ADDRESS
BA0, BA1
BUFFER
BANK #0
ROW DECODER
A0 to A14
BANK #1
GENERATOR
MODE
REGISTER
UPPER ADDRESS
LATCH
REFRESH
COUNTER
DATA
CONTROL AND LATCH
CIRCUIT
CS
BANK #2
CONTROL
MEMORY
CELL
ARRAY
COLUMN DECODER
LOWER ADDRESS
LATCH
BURST
COUNTER
READ
DATA
BUFFER
WRITE ADDRESS
LATCH
ADDRESS
COMPARATOR
DQS
WRITE
DATA
BUFFER
DQ BUFFER
DQ0 to DQn
Note : The K4C560838C-TC configuration is 4 Bank of 32768X256X 8 of cell array with the DQ pins numbered DQ0-7
The K4C561638C-TC configuration is 4 BanK of 32768X128X16 of cell array with the DQ pins numbered DQ0-15.
- 7 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
Vdd
Power Supply Voltage
-0.3 to 3.3
V
VddQ
Power Supply Voltage (for I/O buffer)
-0.3 to Vdd + 0.3
V
VIN
Input Voltage
-0.3 to Vdd + 0.3
V
VOUT
DQ pin Voltage
-0.3 to VddQ + 0.3
V
VREF
Input Reference Voltage
-0.3 to Vdd + 0.3
V
TOPR
Operating Temperature
0 to 70
O
C
TSTG
Storage Temperature
-55 to 150
O
C
TSOLDER
Soldering Temperature(10s)
260
O
C
PD
Power Dissipation
1
W
IOUT
Short Circuit Output Current
± 50
mA
Notes
Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.
Recommanded DC,AC Operating Conditions (Notes : 1)
Symbol
Min
Typ
Max
Units
Power Supply Voltage
2.35
2.5
2.65
V
VddQ
Power Supply Voltage (for I/O Buffer)
2.35
2.5
2.65
V
VREF
Input Reference Voltage
VddQ/2*96%
VddQ/2
VddQ/2*104%
V
2
Vdd
Parameter
(Ta = 0 to 70 ×°C)
Notes
VIH (DC)
Input DC high Voltage
VREF+0.2
-
VddQ+0.2
V
5
VIL(DC)
Input DC Low Voltage
-0.1
-
VREF-0.2
V
5
VICK (DC)
Differential Clock DC Input Voltage
-0.1
-
VddQ+0.1
V
10
VID (DC)
Input Differential Voltage. CK and CK Inputs (DC)
0.4
-
VddQ+0.2
V
7,10
VIH (AC)
Input AC High Voltage
VREF+0.35
-
VddQ+0.2
V
3,6
VIL (AC)
Input AC Low Voltage
-0.1
-
VREF-0.35
V
4,6
VID (AC)
Input Differential Voltage. CK and CK Inputs (AC)
0.7
-
VddQ+0.2
V
7,10
VX (AC)
Differential AC Input Cross Point Voltage
VddQ/2-0.2
-
VddQ/2+0.2
V
8,10
Differential Clock AC Middle Level
VddQ/2-0.2
-
VddQ/2+0.2
V
9,10
VISO (AC)
- 8 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Notes: 1. All voltages are referenced to Vss, VssQ.
2. VREF is expected to track variations in VddQ DC level of the transmitting device.
Peak to peak AC noise on VREF may not exceed ± 2% of VREF (DC).
3. Overshoot Iimit : VIH(max.) = VddQ + 0.9V with a pulse width <= 5ns
4. Undershoot Iimit : VIL(min.) = -0.9V with a pulse width <= 5ns
5. VIH(DC) and VIL(DC) are levels to maintain the current logic state.
6. VIH(AC) and VIL(AC) are levels to change to the new logic state.
7. VID is magnitude of the difference between CK input level and CK input level.
8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device.
9. VISO means [VICK(CK) + VICK(CK)]/2
10. Refer to the figure below.
CLK
VX
VX
VX
VX
VX
VID(AC)
CLK
VICK
VICK
VICK
VICK
VSS
VID(AC)
0 V Differential
VISO
VISO(min)
VISO(max)
VSS
11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of VREF(DC) ± 0.04V.
Pin Capacitance (Vdd, VddQ = 2.5V, f = 1MHz, Ta = 25×°C)
Symbol
Parameter
Min
Max
Units
CIN
Input Pin Capacitance
2.5
4.0
pF
CINC
Clock Pin (CK, CK) Capacitance
2.5
4.0
pF
CI/O
I/O Pin (DQ, DQS) Capacitance
3.0
6.0
pF
CNC1
NC1 Pin Capacitance
-
1.5
pF
CNC2
NC2 Pin Capacitance
4.0
6.0
pF
Note : These parameters are periodically sampled and not 100% tested.
2 The NC2 pins have additional capacitance for adjustment of the adjacent pin capacitance.
1 The NC2 pins have Power and Ground clamp.
- 9 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
DC Characteristics and Operating Conditions (Vdd, VddQ = 2.5V ± 0.15V, Ta = 0~70×°C)
Item
Symbol
Max
D4(400Mbps) DA(366Mbps) D3(333Mbps)
Units
Notes
Operating Current
tCK = min, IRC=min
Read/Write command cycling
OV<=VIN<=VIL(AC) (max.) VIH(AC)(min.) <=VIN<=VddQ
1 bank operation, Burst Length = 4
Address change up to 2 times during minimum IRC.
IDD1S
310
300
290
1, 2
Standby Current
tCK=min, CS = VIH, PD = VIH,
0V<=VIN<=VIL(AC)(max.) VIH(AC)(min.)<=VIH<=VddQ
All Banks : inactive state
Other input signals are changed one time during 4*tCK
IDD2N
85
85
80
1
Standby (Power Down) Current
tCK=min, CS = VIH, PD = VIL (Power Down)
0V<=VIN<=VddQ
All Banks : inactive state
IDD2P
2
2
2
1
Auto-Refresh Current
tCK = min, IREFC= min, tREFI = min
Auto-Refresh command cycling
0V<=VIN<=VIL(AC) (max.), VIH(AC) (min.) <=VIN<=VddQ
Address change up to 2 times during minimum IREFC.
IDD5
105
100
95
1
Self-Refresh Current
self-Refresh mode
PD = 0.2V, OV<=VIN<=VddQ
IDD6
3
3
3
mA
Symbol
Min
Max
Unit
Input Leakage Current
(0V<=VIN<=VddQ, All other pins not under test = 0V)
Item
ILI
-5
5
uA
Output Leakage Current
(Output disabled, 0V<=VOUT<=VddQ)
ILO
-5
5
uA
VREF Current
IREF
-5
5
uA
Output Source DC Current
VOH = VddQ - 0.4V
IOH(DC)
-10
-
3
Output Sink DC Current
VOL=0.4V
IOL(DC)
10
-
3
Output Source DC Current
VOH = VddQ - 0.4V
IOH(DC)
-11
-
3
Output Sink DC Current
VOL=0.4V
IOL(DC)
11
-
Output Source DC Current
VOH = VddQ - 0.4V
IOH(DC)
-8
-
3
Output Sink DC Current
VOL=0.4V
IOL(DC)
8
-
3
Output Source DC Current
VOH = VddQ - 0.4V
IOH(DC)
-7
-
3
Output Sink DC Current
VOL=0.4V
IOL(DC)
7
-
3
Normal Output Driver
Strong Output Driver
Weaker Output Driver
Weakest Output Driver
Notes
3
mA
Notes : 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK, tRC and IRC.
2. These parameters depend on the output loading. The specified values are obtained with the output open.
3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
- 10 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
AC Characteristics and Operating Conditions (Notes : 1, 2)
Symbol
tRC
Item
Random Cycle Time
D4(400Mbps)
DA(366Mbps)
D3(333Mbps)
Min
Max
Min
Min
Max
Max
Units Notes
25
-
27.5
-
30
-
3
CL = 3
5.5
7.5
6
7.5
6.5
7.5
3
CL = 4
5
7.5
5.5
7.5
6
7.5
3
-
22
-
24
-
26
3
tCK
Clock Cycle Time
tRAC
Random Access Time
tCH
Clock High Time
0.45*tCK
-
0.45*tCK
-
0.45*tCK
-
3
tCL
Clock Low Time
0.45*tCK
-
0.45*tCK
-
0.45*tCK
-
3
tCKQS
DQS Access Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
tQSQ
Data Output Skew from DQS
-
0.4
-
0.45
-
0.5
4
tAC
Data Access Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
tOH
Data Output Hold Time from CLK
tQSPRE
DQS(Read) Preamble Pulse Width
tHP
CLK half period ( minium of Actual tCH, tCL)
tQSP
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
0.9*tCK-0.2
1.1*tCK+0.2
0.9*tCK-0.2
1.1*tCK+0.2
0.9*tCK-0.2
1.1*tCK+0.2
3
min(tCH, tCL)
-
min(tCH, tCL)
-
min(tCH, tCL)
-
DQS(Read) Pulse Width
tHP-0.55
-
tHP-0.6
-
tHP-0.65
-
4
tQSQV
Data Output Valid Time from DQS
tHP-0.55
-
tHP-0.6
tHP-0.65
-
4
tDQSS
DQS(Write) Low to High Setup Time
0.75*tCK
1.25*tCK
0.75*tCK
1.25*tCK
0.75*tCK
1.25*tCK
3
tDSPRE
DQS(Write) Preamble Pulse Width
0.4*tCK
-
0.4*tCK
-
0.4*tCK
-
4
tDSPRES DQS First Input Setup Time
0
-
0
-
0
-
3
tDSPREH DQS First Low Input Hold Time
0.25*tCK
-
0.25*tCK
-
0.25*tCK
-
3
tDSP
0.45*tCK
0.55*tCK
0.45*tCK
0.55*tCK
0.45*tCK
0.55*tCK
1.3
-
1.4
-
1.5
-
-
DQS High or Low Input Pulse Width
CL = 3
tDSS
DQS Input Falling Edge to Clock Setup Time
tDSPST
DQS(Write) Postamble Pulse Width
CL = 4
tDSPSTH DQS(Write) Postamble Hold Time
CL = 3
CL = 4
1.3
-
1.4
0.45*tCK
-
0.45*tCK
1.3
-
1.4
-
4
ns
3, 4
1.5
-
0.45*tCK
-
3, 4
4
1.5
-
3, 4
3, 4
1.3
-
1.4
-
1.5
-
-0.5*tCK
0.5*tCK
-0.5*tCK
0.5*tCK
-0.5*tCK
0.5*tCK
0.5
-
0.5
-
0.6
-
4
0.6
-
4
1.9
-
tDSSK
UDQS - LDQS Skew (x16)
tDS
Data Input Setup Time from DQS
tDH
Data Input Hold Time from DQS
0.5
-
0.5
-
tDIPW
Data Input pulse Width (for each device)
1.5
-
1.5
-
tIS
Command / Address Input Setup Time
0.9
-
0.9
-
1
-
3
tIH
Command / Address Input Hold Time
0.9
-
0.9
-
1
-
3
tIPW
Command / Address Input Pulse Width (for each device)
2.0
-
2.0
-
2.2
-
tLZ
Data-out Low Impedance Time from CLK
-0.65
-
-0.75
-
-0.85
-
3, 6, 8
tHZ
Data-out High Impedance Time from CLK
-
0.65
-
0.75
-
0.85
3, 7, 8
tQSLZ
DQS-out Low Impedance Time from CLK
-0.65
-
-0.75
-
-0.85
-
3, 6, 8
tQSHZ
DQS-out High Impedance Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 7, 8
tQPDH
Last Output to PD High Hold Time
0
-
0
-
0
-
tPDEX
Power Down Exit Time
tT
Input Transition Time
tFPDL
PD Low Input Window for Self-Refresh Entry
2
-
2
-
2
-
0.1
1
0.1
1
0.1
1
-0.5*tCK
5
-0.5*tCK
5
-0.5*tCK
5
- 11 -
3
3
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued)
Symbol
Item
tREFI
Auto-Refresh Average Interval
tPAUSE
Pause Time after Power-up
IRC
DA(366Mbps)
D3(333Mbps)
Max
Min
Max
Min
Max
0.4
7.8
0.4
7.8
0.4
7.8
Units Notes
5
us
200
-
200
-
200
-
Random Read/Write Cycle Time
CL = 3
5
-
5
-
5
-
(Applicable to Same Bank)
CL = 4
5
-
5
-
5
-
1
1
1
1
1
1
CL = 3
4
-
4
-
4
-
CL = 4
4
-
4
-
4
-
2
-
2
-
2
-
BL = 2
2
-
2
-
2
-
BL = 4
3
-
3
-
3
-
1
-
1
-
1
-
CL = 3
5
-
5
-
5
-
CL = 4
5
-
5
-
5
-
-
1
-
1
-
1
IRCD
RDA/WRA to LAL Command Input Delay
(Applicable to Same Bank)
IRAS
LAL to RDA/WRA Command Input Delay
(Applicable to Same Bank)
IRBD
Random Bank Access Delay
(Applicable to Other Bank)
IRWD
LAL following RDA to WRA Delay
(Applicable to Other Bank)
IWRD
LAL following WRA to RDA Delay
(Applicable to Other Bank)
IRSC
Mode Register Set Cycle Time
IPD
PD Low to Inactive State of Input Buffer
IPDA
PD High to Active State of Input Buffer
IPDV
D4(400Mbps)
Min
Cycle
-
1
-
1
-
1
CL = 3
15
-
15
-
15
-
CL = 4
18
-
18
-
18
-
CL = 3
15
-
15
-
15
-
CL = 4
18
-
18
-
18
-
Power down mode valid from REF command
IREFC
Auto-Refresh Cycle Time
ICKD
REF Command to Clock Input Disable
at Self-Refresh Entry
16
-
16
-
16
-
ILOCK
DLL Lock-on Time (Applicable to RDA command)
200
-
200
-
200
-
- 12 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
AC Test Conditions
Symbol
VIH(min)
VIL (max)
VREF
VTT
VSWING
VR
VID(AC)
Value
Units
Input high voltage (minimum)
Parameter
VREF + 0.35
V
Input low voltage (maximum)
VREF - 0.35
V
VddQ/2
V
VREF
V
1.0
V
VX(AC)
V
Input reference voltage
Termination voltage
Input signal peak to peak swing
Differential clock input reference level
Input differential voltage
1.5
V
SLEW
Input signal minimum slew rate
1.0
V/ns
VOTR
Output timing measurement reference voltage
VddQ/2
V
Notes
VTT
VddQ
Measurement Point
VIH min(AC)
VSWING
VREF
RT=50Ω
Output
Z=50Ω
VIL max(AC)
CL=30pF
VREF
=0.5*VddQ
Vss
∆T
Output Load Circuit(SSTL_2)
∆T
Slew=(VIHmin(AC) - VILmax(AC))/∆T
Notes : 1. Transition times are measured between VIH min(DC) and VIL max(DC).
Transition (rise and fall) of input signals have a fixed slope.
2. If the result of nominal calculation with regard to tCK contains more than
one decimal place, the result is rounded up to the nearest decimal place.
(i.e., tDQSS = 0.75*tCK, tCK = 5ns, 0.75*5ns = 3.75ns is rounded up to 3.8ns.)
3. These parameters are measured from the differential clock (CK and CK) AC cross point.
4. These parameters are measured from signal transition point of DQS crossing VREF level.
5. The tREFI (MAX.) applies to equally distributed refresh method.
The tREFI (MIN.) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In
other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the
maximum.
6. Low Impedance State is speified at VddQ/2± 0.2V from steady state.
7. High Impedance State is specified where output buffer is no longer driven.
8. These parameters depend on the clock jitter. These parameters are measured at stable clock.
- 13 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Power Up Sequence
1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection.
2. Apply Vdd before or at the same time as VddQ.
3. Apply VddQ before or at the same time as VREF.
4. Start clock (CK, CK) and maintain stable condition for 200us (min.).
5. After stable power and clock, apply DESL and take PD = H.
6. Issue EMRS to enable DLL and to define driver strength. (Note : 1)
7. Issue MRS for set CAS Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1)
8. Issue two or more Auto-Refresh commands. (Note:1)
9. Ready for normal operation after 200 clocks from Extended Mode Register programming. (Note : 2)
Note : 1. Sequence 6, 7 and 8 can be issued in random order.
2. L=Logic Low, H = Logic High
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
1.25V(TYP)
∼
2.5V(TYP)
∼
VDDQ
2.5V(TYP)
∼
VDD
VREF
∼
∼
CLK
∼
CLK
tPDEX
tPDA
200 µs(min)
∼
DESL
WRA REF
DESL
∼
WRA REF
op-code
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
MRS
∼
∼
Hi-Z
DESL
∼
RDA MRS
∼
∼
DQS
∼
DESL
∼
RDA MRS
∼
DESL
EMRS
DQ
lREFC
200 clock cycle(min)
op-code
Address
lREFC
∼
∼
∼
Command
lRSC
∼
PD
lRSC
EMRS
MRS
- 14 -
Auto Refresh cycle
Nomal Operation
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Basic Timing Diagrams
Input Timing
tCK
tCH
tCK
tCL
CK
~
CK
CS
tIH
tIS
tIH
1st
2nd
tIPW
tIS
tIS
tIH
tIH
tIPW
A0-A14
BA0.BA1
tIS
tIH
tIH
~~
tIS
~~
2nd
1st
FN
~~
tIS
LA
UA, BA
tIPW
~
DQS
tDS
tDH
tDS
tDH
~~
DQ(Input)
tDIPW
tDIPW
Refer to the Command Truth Table.
Timing of the CK, /CK
tCH
tCL
CK
CK
tT
tT
VIH
VIH(AC)
VIL(AC)
VIL
tCK
VIH
CK
VID(AC)
CK
VX
VX
- 15 -
VX
VIL
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Read Timing (Burst Length = 4)
tCH
tCL
tCK
CK
CK
tIS
Input
(Control &
Addresses)
tIH
LAL
(after RDA)
tCKQS
tIPW
tQSLZ
CAS latency = 3
DQS
(Output)
tCKQS
tCKQS
tQSP
tQSHZ
High-Z
High-Z
Preamble
tQSQV
tQSQ
Postamble
tQSQ
tQSQV
tLZ
DQ
(Output)
tQSP
tQSPRE
High-Z
Q0
Q1
tAC
tAC
tQSQ
Q2
Q3
tAC
tOH
tCKQS
CAS latency = 4
tQSLZ
tCKQS
tHZ
High-Z
tCKQS
tQSP
tQSP
tQSHZ
tQSPRE
DQS
(Output)
High-Z
Preamble
tQSQ
tQSQV
tQSQ
tQSQV
tLZ
DQ
(Output)
Postamble
High-Z
Q0
tAC
Q1
tAC
Q2
tAC
tQSQ
tHZ
Q3
tOH
Note : The correspondence of LDQS, UDQS to DQ. (K4C561638C-TC)
LDQS
DQ0 to 7
UDQS
DQ8 to 15
- 16 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Write Timing (Burst Length = 4)
tCH
tCL
tCK
CK
CK
tIS
Input
(Control &
Addresses)
tIH
LAL
(after WRA)
tDSPSTH
tIPW
CAS latency = 3
tDQSS
tDSS
tDSP
tDSPRES
tDSP
tDSP
tDSPST
tDSPREH
DQS
(Input)
Preamble
tDSPRE
tDSS
tDS
DQ
(Input)
tDIPW
tDH
D0
Postamble
tDS
tDS
tDH
D1
D2
tDH
D3
tDSS
tDQSS
CAS latency = 4
tDSPRES
tDSS
tDSP
tDSPSTH
tDSP
tDSP
tDSPST
tDSPREH
DQS
(Input)
Preamble
tDSPRE
tDSS
tDS
tDIPW
tDS
tDH
tDH
DQ
(Input)
D0
tDQSS
Postamble
tDS
D1
D2
tDH
D3
tDQSS
Note. The correspondence of LDQS, UDQS to DQ. (K4C561638C-TC)
LDQS
DQ0 to 7
UDQS
DQ8 to 15
~
tREFI, tPAUSE, Ixxxx Timing
CK
tIS
Input
(Control &
Addresses)
tIH
Command
tREFI,tPAUSE,IXXXX
~
CK
tIS
tIH
Command
Note. "IXXXX"means "IRC", "IRCD", "IRAS", etc.
- 17 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Write Timing (x16 device) (Burst Length = 4)
CK
CK
Input
(Control &
Addresses)
WRA
LAL
CAS latency = 3
tDSSK
tDSSK
tDSSK
tDSSK
LDQS
Preamble
Postamble
tDH
DQ0 ~ 7
tDH
tDH
tDH
tDS
tDS
tDS
tDS
D0
D1
D2
D3
UDQS
Preamble
Postamble
tDH
DQ8 ~ 15
tDH
tDH
tDH
tDS
tDS
tDS
tDS
D0
D1
D2
D3
CAS latency = 4
tDSSK
tDSSK
tDSSK
tDSSK
LDQS
Preamble
Postamble
tDH
DQ0 ~ 7
tDH
tDH
tDH
tDS
tDS
tDS
tDS
D0
D1
D2
D3
UDQS
Preamble
Postamble
tDH
DQ8 ~ 15
- 18 -
tDH
tDH
tDH
tDS
tDS
tDS
tDS
D0
D1
D2
D3
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Function Truth Table (Notes : 1,2,3)
Command Truth Table (Notes : 4)
•The First Command
Symbol
Function
CS
FN
BA1-BA0
A14-A9
A8
A7
A6-A0
DESL
Device Deselect
H
X
X
X
X
X
X
RDA
Read with Auto-close
L
H
BA
UA
UA
UA
UA
WRA
Write with Auto-close
L
L
BA
UA
UA
UA
UA
•The Second Command (The next clock of RDA or WRA command)
Symbol
Function
CS
FN
BA1-BA0
A14-A13 A12-A11
A10-A9
A8
A7
A6-A0
LAL
Lower Address Latch (x16)
H
X
X
V
V
X
X
X
LA
LAL
Lower Address Latch (x8)
H
X
X
V
X
X
X
LA
LA
REF
Auto-Refresh
L
X
X
X
X
X
X
X
X
MRS
Mode Register Set
L
X
V
L
L
L
L
V
V
Notes : 1. L = Logic Low, H = Logic High, X = either L or H, V = Valid (Specified Value), BA = Bank Address, UA = Upper Address,
LA = Lower Address.
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and the
command table below.
Read Command Table
Command (Symbol)
CS
FN
BA1-BA0
A14-A9
A8
A7
A6-A0
RDA (1st)
L
H
BA
UA
UA
UA
UA
LAL (2nd)
H
X
X
X
X
LA
LA
Notes
5
Notes : 5. For x16 device, A7 is "X" (either L or H).
- 19 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Write Command Table
K4C561638C-TC
Command (Symbol)
CS
FN
BA1-BA0
A14
A13
A12
A11
A10-A9
A8
A7
A6-A0
WRA (1st)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
UA
LAL (2nd)
H
X
X
LVWO
LVW1
UVW0
UVW1
X
X
X
LA
Command (Symbol)
CS
FN
BA1-BA0
A14
A13
A12
A11
A10-A9
A8
A7
A6-A0
WRA (1st)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
UA
LAL (2nd)
H
X
X
VWO
VW1
X
X
X
X
LA
LA
K4C560838C-TC
Note : 6. A14 to A11 are used for variable Write Length (VW) control at Write Operation.
VW Truth Table
Function
VW0
VW1
Write All Words
L
X
Write First One Word
H
X
Reserved
L
L
Write All Words
H
L
Write First Two Words
L
H
Write First One Word
H
H
BL = 2
BL = 4
Note : 7. For x16 device, LVW0 and LVW1 control DQ0-DQ7, UVW0 and UVW1 control DQ8-DQ15.
Mode Register Set Command Truth Table
Command (Symbol)
CS
FN
BA1-BA0
A14-A9
A8
A7
A6-A0
RDA (1st)
L
H
X
X
X
X
X
MRS (2nd)
L
X
V
L
L
V
V
Notes
8
Note : 8. Refer to "Mode Register Table".
- 20 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Function Truth Table (Continued)
Auto-Refresh Command Table
PD
Command
(Symbol)
Current
State
n-1
n
Active
WRA(1st)
Standby
H
Auto-Refresh
REF(2nd)
Active
H
Function
CS
FN
BA1-BA0 A14-A9
H
L
L
X
H
L
X
X
A8
A7
A6-A0
X
X
X
X
X
X
X
X
Notes
Self-Refresh Command Table
PD
Command
(Symbol)
Current
State
n-1
n
Active
WRA(1st)
Standby
H
Self-Refresh Entry
REF(2nd)
Active
-
Function
CS
FN
H
L
L
X
X
X
X
X
H
L
L
X
X
X
X
X
X
Self-Refresh
L
L
X
X
X
X
X
X
X
SELFX
Self-Refresh
L
H
H
X
X
X
X
X
X
Command
(Symbol)
Current
State
CS
FN
A8
A7
n-1
n
PDEN
Standby
H
L
H
X
X
X
X
X
X
-
Power Down
L
L
X
X
X
X
X
X
X
PDEX
Power Down
L
H
H
X
X
X
X
X
X
Self-Refresh Continue
Self-Refresh Exit
BA1-BA0 A14-A9 A8
A7
A6-A0 Notes
9, 10
11
Power Down Table
Function
Power Down Entry
Power Down Continue
Power Down Exit
PD
BA1-BA0 A14-A9
A6-A0 Notes
10
11
Notes : 9. PD has to be brought to Low within tFPDL from REF command.
10. PD should be brought to Low after DQ’s state turned high impedance.
11. When PD is brought to High from Low, this function is executed asynchronously.
- 21 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Function Truth Table (Continued)
Current State
Idle
Row Active for Read
Row Active for Write
Read
Write
Auto-Refreshing
Mode Register Accessing
Power Down
Se;f-Refreshing
PD
CS
FN
Address
Command
H
L
L
H
L
X
H
L
X
X
X
BA, UA
BA, UA
X
X
DESL
RDA
WRA
PDEN
-
X
H
H
L
L
X
H
H
L
L
X
H
X
H
L
H
L
X
H
L
H
L
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
LA
Op-Code
X
X
X
LA
X
X
X
X
X
LAL
MRS/EMRS
PDEN
REF (Self)
LAL
REF
PDEN
REF (Self)
DESL
H
H
H
H
H
L
L
L
H
H
L
X
BA, UA
BA, UA
X
RDA
WRA
PDEN
Illegal
Illegal
Illegal
H
L
H
H
H
H
H
L
L
X
H
H
H
L
L
X
L
X
H
L
L
H
L
X
X
X
X
H
L
X
X
X
X
X
X
BA, UA
BA, UA
X
X
X
DESL
RDA
WRA
PDEN
-
Illegal
Invalid
Data write & continue burst write to end
Illegal
Illegal
Illegal
Illegal
Invalid
H
H
H
X
X
DESL
NOP-> Idle after IREFC
H
H
H
H
H
H
L
L
L
L
H
L
H
L
X
X
BA, UA
BA, UA
X
X
RDA
WRA
PDEN
-
Illegal
Illegal
Self-Refresh entry
Illegal
L
H
X
H
X
H
X
X
X
X
DESL
Refer to Self-Refreshing state
Nop-> Idle after IRSC
H
H
H
H
L
H
L
L
H
H
L
L
X
X
L
H
L
L
H
L
X
X
X
H
H
L
X
X
X
X
X
X
BA, UA
BA, UA
X
X
X
X
X
X
RDA
WRA
PDEN
RDEX
Illegal
Illegal
Illegal
Illegal
Invalid
Invalid
Maintain Power Down Mode
Exit Power Down Mode->Idle after tPDEX
L
H
L
L
H
X
L
H
L
X
X
H
X
X
X
X
X
X
X
X
SELFX
Illegal
Invalid
Maintain Self-Refresh
Exit Self-Refresh->Idle after IREFC
L
H
L
X
X
-
n-1
H
H
H
H
H
n
H
H
H
L
L
L
H
H
H
H
L
H
H
H
H
L
H
Action
NOP
Row activate for Read
Row activate for Write
Power Down Entry
Illegal
Notes
12
Refer to Power Down state
Begin read
Access to Mode Register
Illegal
Illegal
Invalid
Begin Write
Auto-Refresh
Illegal
Self-Refresh entry
Invalid
Continue burst read to end
13
13
13
13
14
Illegal
Notes : 12. Illegal if any bank is not idle.
13. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA).
14. Illegal if tFPDL is not satisfied.
- 22 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Mode Register Table
Regular Mode Register (Notes : 1)
Address
BA1*1
BA0*1
A14-A8
A7*3
A6-A4
A3
A2-A0
Register
0
0
0
TM
CL
BT
BL
A7
Test Mode (TM)
A3
Burst Type (BT)
0
Regular (Default)
0
Sequential
1
Test Mode Entry
1
Interleave
A6
A5
A4
CAS Latency (CL)
A2
A1
A0
Burst Length (BL)
0
0
X
Reserved *2
0
0
0
Reserved *2
0
1
0
Reserved *2
0
0
1
2
0
1
1
3
0
1
0
4
1
0
0
4
0
1
1
Reserved *2
1
0
1
Reserved *2
1
X
X
1
1
X
Reserved *2
Extended Mode Register (Notes : 4)
Address
BA1*4
BA0*4
A14-A7
A6
A5-A2
A1
A0
Register
0
1
0
DIC
0
DIC
DS
A6
A1
Output Driver Impedance Control (DIC)
0
0
Normal Output Driver
0
1
Strong Output Driver
1
0
Weaker Output Driver
1
1
Weakest Output Driver
Note : 1. Regular Mode Register is Chosen Using the combination of BA0 = 0 and BA1 = 0.
2. "Reserved" places in Regular Mode Register should not be set.
3. A7 in Regular Mode Register must be set to "0"(Low state).
Because test Mode is specific mode for supplier.
4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0.
- 23 -
A0
DLL Switch (DS)
0
DLL Enable
1
DLL Disable
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
State Diagram
Self
Refresh
Power
Down
PDEX
(PD = H)
SELFX
(PD = H)
PDEN
(PD = L)
PD = L
Standby
(Idle)
PD = H
AutoRefresh
Mode
Register
WRA
RDA
REF
MRS
Active
(Restore)
Active
LAL
LAL
Write
(Buffer)
Read
Command Input
Automatic Return
The second command at Active
state must be issued 1clock after
RDA or WRA command input
- 24 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Timing Diagrams
Single Bank Read Timing (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
RDA
LAL
CK
CK
IRC = 5 cycles
Command
RDA
LAL
IRCD = 1 cycle
BL = 2
DQS
(Output)
IRC = 5 cycles
DESL
RDA
IRAS = 4 cycles
LAL
IRCD = 1 cycle
IRAS = 4 cycles
Hi-Z
Hi-Z
Hi-Z
CL = 3
DQ
(Output)
DESL
CL = 3
Hi-Z
Hi-Z
Q0 Q1
Hi-Z
Q0 Q1
BL = 4
DQS
(Output)
Hi-Z
DQ
(Output)
Hi-Z
Hi-Z
Hi-Z
CL = 3
CL = 3
Hi-Z
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Hi-Z
Single Bank Read Timing (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
RDA
LAL
CK
CK
IRC = 5 cycles
Command
BL = 2
DQS
(Output)
RDA
LAL
IRCD = 1 cycle
DESL
IRC = 5 cycles
RDA
IRAS = 4 cycles
LAL
DESL
IRCD = 1 cycle
IRAS = 4 cycles
Hi-Z
Hi-Z
CL = 4
DQ
(Output)
CL = 4
Hi-Z
Q0 Q1
Hi-Z
Q0 Q1
BL = 4
DQS
(Output)
Hi-Z
Hi-Z
CL = 4
DQ
(Output)
CL = 4
Hi-Z
Q0 Q1 Q2 Q3
- 25 -
Hi-Z
Q0 Q1 Q2
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Single Bank Write Timing (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
WRA
LAL
CK
CK
IRC = 5 cycles
Command
WRA
LAL
IRCD = 1 cycle
IRC = 5 cycles
DESL
WRA
IRAS = 4 cycles
LAL
IRCD = 1 cycle
DESL
IRAS = 4 cycles
IRCD = 1 cycle
BL = 2
DQS
(Input)
tDQSS
WL = 2
WL = 2
DQ
(input)
D0 D1
D0 D1
tDQSS
tDQSS
BL = 4
DQS
(Input)
WL = 2
WL = 2
DQ
(input)
D0 D1 D2 D3
D0 D1 D2 D3
Single Bank Write Timing (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
WRA
LAL
CK
CK
IRC = 5 cycles
Command
WRA
LAL
IRCD = 1 cycle
IRC = 5 cycles
DESL
WRA
IRAS = 4 cycles
LAL
IRCD = 1 cycle
DESL
IRAS = 4 cycles
IRCD = 1 cycle
BL = 2
DQS
(Input)
WL = 3
WL = 3
DQ
(input)
D0 D1
D0 D1
tDQSS
tDQSS
BL = 4
DQS
(Input)
WL = 3
DQ
(input)
WL = 3
D0 D1 D2 D3
Note :
D0 D1 D2 D3
means "H" or "L"
- 26 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Single Bank Read-Write Timing (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
RDA
LAL
CK
CK
IRC = 5 cycles
Command
RDA
LAL
IRCD = 1 cycle
BL = 2
DQS
IRC = 5 cycles
DESL
WRA
IRAS = 4 cycles
LAL
IRCD = 1 cycle
IRAS = 4 cycles
Hi-Z
Hi-Z
Hi-Z
CL = 3
WL = 2
Hi-Z
DQ
DESL
Hi-Z
Q0 Q1
Hi-Z
D0 D1
tDQSS
BL = 4
DQS
Hi-Z
CL = 3
WL = 2
Hi-Z
DQ
Hi-Z
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
D0 D1 D2 D3
Single Bank Read-Write Timing (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
RDA
LAL
CK
CK
IRC = 5 cycles
Command
BL = 2
DQS
RDA
LAL
IRCD = 1 cycle
DESL
IRC = 5 cycles
WRA
IRAS = 4 cycles
LAL
IRCD = 1 cycle
IRAS = 4 cycles
Hi-Z
Hi-Z
Hi-Z
CL = 4
DQ
DESL
WL = 3
Hi-Z
Q0 Q1
Hi-Z
D0 D1
Hi-Z
BL = 4
DQS
Hi-Z
CL = 4
DQ
Hi-Z
Hi-Z
WL = 3
Hi-Z
Q0 Q1 Q2 Q3
- 27 -
Hi-Z
D0 D1 D2 D3
Hi-Z
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Multiple Bank Read Timing (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
CK
CK
IRC = 5 cycles
Command
RDAa
LALa
RDAb
IRCD = 1 cycle
Bank Add.
(BA0, BA1)
Bank"a"
DQ
(Output)
BL = 4
DQS
(Output)
DQ
(Output)
LALb
DESL
RDAa
IRAS = 4 cycles
LALa
IRCD = 1 cycle
RDAc
LALc
IRCD = 1 cycle
Bank"b"
X
Bank"a"
X
IRCD = 1 cycle
RDAd
RDAb
LALd
IRBD = 2 cycles
IRBD = 2 cycles
X
X
Bank"c"
Bank"d"
Bank"b"
IRBD = 2 cycles
BL = 2
DQS
(Output)
X
IRBD = 2 cycles
Hi-Z
Hi-Z
CL = 3
CL = 3
Hi-Z
Hi-Z
Qa0 Qa1
Hi-Z
Qb0 Qb1
Hi-Z
Qa0 Qa1
CL = 3
Qc0
CL = 3
Hi-Z
CL = 3
CL = 3
Hi-Z
Hi-Z
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qc0
Multiple Bank Read Timing (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
CK
CK
IRC = 5 cycles
Command
RDAa
LALa
RDAb
IRCD = 1 cycle
Bank Add.
(BA0, BA1)
Bank"a"
DQ
(Output)
BL = 4
DQS
(Output)
DQ
(Output)
LALb
DESL
RDAa
IRAS = 4 cycles
Bank"b"
LALa
IRCD = 1 cycle
RDAc
IRCD =1 cycle
X
Bank"a"
X
Bank"c"
IRCD = 1 cycle
LALc
RDAd
RDAb
LALd
IRBD = 2 cycles
IRBD = 2 cycles
X
X
Bank"d"
Bank"b"
IRBD = 2 cycles
BL = 2
DQS
(Output)
X
IRBD = 2 cycles
Hi-Z
Hi-Z
CL = 4
CL = 4
Hi-Z
Qa0 Qa1
Hi-Z
Hi-Z
Qb0 Qb1
Qa0 Qa1
CL = 4
Hi-Z
CL = 4
Hi-Z
CL = 4
CL = 4
Hi-Z
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Hi-Z
Qa0 Qa1 Qa2
Note : "X" is don’t care. IRC to the same bank must be satisfied.
- 28 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Multiple Bank Write Timing (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
CK
CK
Command
IRC = 5 cycles
WRAa
LALa
WRAb
IRCD = 1 cycle
Bank Add.
(BA0, BA1)
Bank"a"
X
IRBD = 2 cycles
LALb
DESL
Bank"b"
LALa
WRAc
IRCD = 1 cycle
X
Bank"a"
X
IRCD = 1 cycle
LALc
WRAd
WRAb
LALd
IRBD = 2 cycles
IRBD = 2 cycles
X
X
Bank"c"
Bank"d"
Bank"b"
tDQSS
IRBD = 2 cycles
BL = 2
WRAa
IRAS = 4 cycles
IRCD = 1 cycle
DQS
(input)
tDQSS
WL = 2
WL = 2
DQ
(input)
Da0 Da1
Db0 Db1
Da0 Da1
BL = 4
tDQSS
tDQSS
tDQSS
Dc0 Dc1
DQS
(input)
WL = 2
DQ
(input)
WL = 2
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Dc0 Dc1 Dc2
Multiple Bank Write Timing (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
CK
CK
Command
IRC = 5 cycles
WRAa
LALa
WRAb
IRCD = 1 cycle
Bank Add.
(BA0, BA1)
Bank"a"
X
IRBD = 2 cycles
LALb
DESL
WRAa
IRAS = 4 cycles
Bank"b"
WRAc
IRCD = 1 cycle
X
Bank"a"
X
IRCD = 1 cycle
LALc
WRAd
WRAb
LALd
IRBD = 2 cycles
IRBD = 2 cycles
X
X
Bank"c"
Bank"d"
Bank"b"
tDQSS
IRBD = 2 cycles
BL = 2
LALa
IRCD = 1 cycle
DQS
(input)
tDQSS
WL = 3
WL = 3
DQ
(input)
Da0 Da1
Db0 Db1
Da0 Da1
BL = 4
tDQSS
tDQSS
tDQSS
Dc0 Dc1
DQS
(input)
WL = 3
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Note :
WL = 3
Da0 Da1 Da2 Da3 Dc0 Dc1
means "H" or "L" "X" is don’t care IRC to the same bank must be satisfied.
- 29 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Multiple Bank Read-Write Timing (BL = 2)
0
1
2
3
4
5
6
7
8
9
10
11
WRAc
LALc
CK
CK
IRBD = 2 cycles
Command
WRAa
LALa
IRCD = 1 cycle
Bank Add.
(BA0, BA1)
Bank"a"
IRCD = 1 cycle
RDAb
LALb
DESL
IRBD = 2 cycles
WRAc
IWRD = 1 cycle
X
LALc
IRCD = 1 cycle
Bank"b"
X
Bank"c"
IRC = 5 cycles
RDAd
IRWD = 2 cycles
LALd
DESL
IWRD = 1 cycle
X
IRCD = 1 cycle
Bank"d"
tDQSS
CL = 3
DQS
IRWD = 2 cycles
X
X
Bank"c"
tDQSS
Hi-Z
Hi-Z
Hi-Z
CL = 3
WL = 2
WL = 2
CL = 3
Hi-Z
DQ
Da0 Da1
Qb0 Qb1
Dc0 Dc1
tDQSS
CL = 4
Qd0
tDQSS
Hi-Z
Hi-Z
Hi-Z
DQS
CL = 4
WL =3
DQ
Hi-Z
WL = 3
CL = 4
Hi-Z
Hi-Z
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Multiple Bank Read-Write Timing (BL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
CK
CK
IRBD = 2 cycles
Command
WRAa
LALa
IRCD = 1 cycle
Bank Add.
(BA0, BA1)
CL = 3
DQS
Bank"a"
IRCD = 1 cycle
RDAb
IRWD = 3 cycles
LALb
X
LALc
RDAd
DESL
LALd
IRCD = 1 cycle IWRD = 1 cycle
IWRD = 1 cycle
Bank"b"
X
Bank"c"
X
X
Bank"d"
tDQSS
tDQSS
Hi-Z
WL = 2
CL = 3
Hi-Z
WL = 2
CL = 3
Hi-Z
DQ
Da0 Da1 Da2 Da3
Hi-Z
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
tDQSS
CL = 4
DQS
WRAc
DESL
IRCD = 1 cycle
IRBD = 2 cycles
tDQSS
Hi-Z
CL = 4
WL = 3
WL = 3
Hi-Z
DQ
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Note : "X" is dont care
IRC to the same bank must be satisfied.
- 30 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Single Bank Write with VW (CL=3, BL=4, Sequential mode)
0
1
2
3
4
5
6
7
8
9
10
11
WRA
LAL
UA
LA
CK
CK
IRC = 5 cycles
IRC = 5 cycles
x8 device
Command
Address
WRA
LAL
UA
LA=#3
VW=2
DESL
WRA
LAL
UA
LA=#1
VW=1
DESL
DQS
(Input)
Last two data are masked.
DQ
(Input)
D0 D1
Address
#3
Last three data are masked.
D0
#0 (#1) (#2)
#1 (#2) (#3) (#0)
x16 device
Command
Address
WRA
LAL
UA
LA=#3
UVW=2
LVW=1
DESL
WRA
LAL
UA
LA=#3
UVW=1
LVW=1
DESL
WRA
LAL
UA
LA
UDQS
(Input)
Last two data are masked.
DQ8 to
DQ15
(Input)
D0 D1
Address
#3
Last three data are masked.
D0
#0 (#1) (#2)
#1 (#2) (#3) (#0)
LDQS
(Input)
Last three data are masked.
Last three data are masked.
DQ0 to
DQ7
(Input)
D0
Address
#3
D0
(#0) (#1) (#2)
#1 (#2) (#3) (#0)
Notes : DQS input must be continued till end of burst count even if some of laster data is masked.
- 31 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Mode Register Set Timing (CL=3, BL=2)
0
1
2
3
4
5
6
7
8
9
10
11
CK
CK
IRC = 5 cycles
Command
RDA
LAL
IRCD = 1 cycle
A14 to A0
BA0, BA1
DQS
(Output)
BA,UA
IRCS = 5 cycles
DESL
RDA
IRAS = 4 cycles
LA
MRS
DESL
RDA
or
WRA
X
BA,UA
IRCD = 1 cycle
Valid
X
(Op-Code)
Hi-Z
Hi-Z
CL = 3
DQ
(Output)
Hi-Z
Hi-Z
Q0 Q1
Power Down Timing (CL=3, BL=2)
0
1
2
3
4
5
6
7
n-1
n
n+1
n+2
∼
CK
CK
IPDA = 1 cycles
RDA
LAL
∼
Command
DESL
IRCD = 1 cycle
tIH
tIS
Hi-Z
∼∼
tQPDH
Hi-Z
RDA
or
WRA
IPD = 1 cycle
A14 to A0
BA0, BA1
DQS
(Output)
DESL
X
tPDEX
CL = 3
Hi-Z
Q0 Q1
Hi-Z
Power Down Entry
∼
DQ
(Output)
Power Down Exit
Note : "x" is don’t care.
IPD is defined from the first clock rising edage after PD is brought to "Low".
IPDA is defined from the first clock rising edage after PD is brought to "High".
PD must be kept "High" level until end of Burst data output.
PD should be brought to high within tREFI(max) to maintain the data written into cell.
- 32 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Power Down Timing (CL=4)
Write cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
n-1
n
n+1
n+2
∼
CLK
CLK
IRDA = 1 cycle
WRA
LAL
DESL
∼
Command
x
tIH
tIS
IPD = 1 cycle
DESL
RDA
or
WRA
PD
∼
WL=3
2 clock cycles
tPDEX
IRC(min), tREFI(max)
DQS
(Input)
Hi-Z
DQ
(Input)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
∼
Hi-Z
∼
DQ
(Input)
Hi-Z
∼
Hi-Z
∼
DQS
(Input)
BL=4
D0
D1
D2
D3
BL=2
D0
D1
Power Down Entry
Power Down Exit
Note : "x" is don’t care.
PD must be kept "High" level until WL+2 clock cycles from LAL command.
PD should be brought to high within tREFI(max) to maintain the data written into cell.
- 33 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Auto-Refresh Timing (CL=3, BL=4)
0
1
2
3
4
5
6
7
8
CK
IRC = 5 cycles
Command
RDA
LAL
IRCD = 1 cycle
10
11
RDA
or
WRA
LAL or
MRS or
REF
IREFC = 15 cycles
DESL
WRA
IRAS = 4 cycles
REF
DESL
IRCD = 1 cycle
Hi-Z
Hi-Z
~
DQS
(Output)
9
~
CK
CL = 3
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
~
DQ
(Output)
Note : In case of CL=3, IREFC must be meet 15 clock cycles. When the Auto-Refresh operation is performed,
the synthetic average interval of Auto-Refresh command specified by tREFI must be satisfied. tREFI is
average Interval time in 8 Refresh cycles that is sampled randomly.
WRA REF
t8
~
t7
~
WRA REF
~
t3
~
WRA REF
t2
~
t1
CK
WRA REF
WRA REF
8 Refresh Cycle
Total time of 8 Refresh cycle
tREFI =
=
t1 + t2 + t3 + t4 + t5+ t6+ t 7+ t8
8
8
tREFI is specified to avoid partly concentrated current of Refresh operation that is activated larger area than
Read/Write operation.
- 34 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Self-Refresh Entry Timing
0
1
2
3
4
5
m-1
IRCD = 1 cycle
WRA
IREFC
REF
X *1
DESL
tFPDL(min) tFPDL(max)
Auto Refresh
Self Refresh Entry
IPDV*2
tQPDH
ICKD = 16 cycleS *3
Hi-Z
DQS
(Output)
~
~
Hi-Z
Qx
~ ~
PD
DQ
(Output)
m+1
~ ~ ~ ~
CK
Command
m
~
CK
Note : 1. "X" is don’t care.
2. PD msut be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self Refresh mode
When PD is brought to "Low" after IPDV, Network-DRAM perform Auto Refresh and enter Power down mode.
3. It is desirable that clock input is continued at least 16 clock cycles from REF command even though
PD is brought to "Low" for Self-Refresh Entry.
Self-Refresh Exit Timing
0
1
2
m-1
m
m+1
IREFC
X*1
DESL*3
REF*5
Command Command
(1st)*6
(2nd)*6
DESL
IRCD = 1 cycle
tPDEX
p
RDA*7
LAL*7
IRCD = 1 cycle
~
~
~
Hi-Z
~
DQ
(Output)
ILOCK
~
Hi-Z
~
DQS
(Output)
p-1
~
~
~
PD
n+1
IREFC
WRA*5
IPDA = 1 cycle *4
n
~
Command
n-1
~
CK
m+2
~
~
CK
Self-Refresh Exit
Note : 1. "X" is don’t care.,
2. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during IREFC after PD is brought to "High".
4. IPDA is defined from the first clock rising edge after PD is brought to "High".
5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation.
6. Any command (except Read command) can be issued after IREFC.
7. Read command (RDA+LAL) can be issued after ILOCK.
- 35 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Function Description
Network-DRAM
The Network-DRAM is Double Data Rate (DDR) operating. The Network-DRAM is competent to perform fast random core access,
low latency, low consumption and high-speed data bandwidth.
Pin Functions
Clock Inputs : CK & CK
The CK and CK inputs are used as the reference for synchronus operation. CK is master clock input. The CS, FN and all address
input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK. The DQS and DQ and DQ output
data are referenced to the crossing point of CK and CK. The timing reference point for the differential clock is when the CK and CK signals cross during a transition.
Power Down : PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like
a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being performed.
Chip Select & Function Control : CS & FN
The CS and FN inputs are a control aignal for forming the operation commands on Network-DRAM. Each operation mode is decided
by the combination of the two consecutive operation commands using the CS and FN inputs.
Bank Addresses : BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for
the operation.
BA0
BA1
Bank #0
0
0
Bank #1
1
0
Bank #2
0
1
Bank #3
1
1
- 36 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Functional Description (Continued)
Address Inputs : A0 to A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank
address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs
are also used for setting the data in the Regular or Extended Mode Register set cycle.
Upper Address
Lower Address
K4C560838C-TC
A0 to A14
A0 to A7
K4C561638C-TC
A0 to A14
A0 to A6
Data Input/Output : DQ0 to DQ7 or DQ15
The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal.
The output data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS output signal.
Data Strobe : DQS or LDQS, UDQS
The DQS is bi-directional signal. Both edges of DQS are used as the reference of data input or output. The LDQS is allotted for Lower
Byte (DQ0 to DQ7) Data. The UDQS is allotted for Upper Byte(DQ8 to DQ15) Data. In write operation, the DQS used as an input signal
is utilized for a latch of write data. In read operation, the DQS that is an output signal provides the read data strobe.
Power Supply : Vdd, VddQ, Vss, VssQ
Vdd and Vss are supply pins for memory core and peripheral circuits.
VddQ and VssQ are power supply pins for the output buffer.
Reference Voltage : VREF
VREF is reference voltage for all input signals.
- 37 -
REV. 0.7 Aug. 2003
K4C5608/1638C
256Mb Network-DRAM
Functional Description (Continued)
Command Functions and Operations
K4C5608/1638C-TC are introduced the two consccutive command input method. Therefore, except for Power Down mode, each
operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be
accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in
a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out
sequentially synchroniaing with the both edges of DQS output signal (Burst Read Operation). The initial valid read data appears after
CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank
goes back automatically to the idle state after IRC.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address
in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is
latched sequentially synchronizing with the both edges of DQS input signal (Burst Write Operation). The data and DQS inputs have to
be asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The write data length is set by the
VW in the LAL command. The DQS have to be provided for a burst length. The CAS latency and the burst type must be set in the
Mode Register beforehand. The write operated bank goes back automatically to the idle state after IRC.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
K4C560838/1638C-TC are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command
following to the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all outputs are
in Hi-z states. In a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into
the next clock of the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the
next command is specified by IREFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In
case of equally distributed refresh, Auto-Refresh command has to be issued within once for every 7.8us by the maximum In case of
burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than
400ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2us (8x400ns) is to 8 times in the
maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD="L")
It is the function of Self-Refresh operation that refresh operation can be performed automatically by using an internal timer. When all
banks are in the idle state and all outputs are in Hi-z states, the K4C560838/1638C-TC become Self-Refresh mode by issuing the SelfRefresh command. PD has to be brought to "Low" within tFPDL from the REF command following to the WRA command for a SelfRefresh mode entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 7.8us after the
latest Auto-Refresh command. Once the device enters Self-Refresh mode, the DESL command must be continued for IREFC period. In
addition, it is desirable that clock input is kept in ICKD period. The device is in Self-Refresh mode as long as PD held "Low". During
Self-Refresh mode, all input and output buffers except for PD are disabled, therefore the power dissipation lowers. Regarding a SelfRefresh mode exit, PD has to be changed over from "Low" to "High" along with the DESL command, and the DESL command has to
be continuously issued in the number of clocks specified by IREFC. The Self-Refresh exit function is asynchronous operation. It is
required that one Auto-Refresh command is issued to avoid the violence of the refresh period just after IREFC from Self-Refresh exit.
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256Mb Network-DRAM
Power Down Mode( PD="L" )
When all banks are in the idle state and all outputs are in Hi-Z states, the K4C560838/1638C-TC become Power Down Mode by
asserting PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD are disabled after
specified time. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL
command has to be issued at next CK rising edge after PD goes high. The Power Down exit function is asynchronous operation.
Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a
point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the
RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1
address inputs. The K4C560838/1638C-TC have two mode registers. These are Regule and Extended Mode Register. The Regular or
Extended Mode Register is chosen by BA0 in the MRS command.The Regular Mode Register designates the operation mode for a
read or write cycle. The Regular Mode Register has four function fields.
The four fields are as follows :
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has two function fields.
The two fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
Once these fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by
another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper operation.
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256Mb Network-DRAM
Functional Description (Continued)
• Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
BA1
BA0
A14 - A0
0
0
Regular MRS cycle
0
1
Extended MRS cycle
1
X
Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2 or 4
words.
A2
A1
A0
Burst Length
0
0
0
Reserved
0
0
1
2 words
0
1
0
4 words
0
1
1
Reserved
1
X
X
Reserved
(R-2) Burst Type field (A3)
This Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is " 0", Sequential mode is
selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words.
A3
Burst Type
0
Sequential
1
Interleave
• Addressing sequence of Sequential mode (A3)
A column access is started from the inputted lower address and is performed by incrementing the lower address input to
the device. The address is varied by the Burst Length as the following.
CAS Latency = 2
CK
CK
Command
RDA
LAL
DQS
DQ
Data 0 Data 1 Data 2 Data 3
Addressing sequence for Sequential mode
Data
Access Address
Data 0
n
Data 1
n+1
Data 2
n+2
Data 3
n+3
Burst Length
2 words (Address bits is LA0)
not carried from LA0 to LA1
4 words(Address bits is LA1, LA0)
not carried from LA0 to LA1
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256Mb Network-DRAM
Functional Description (Continued)
• Addressing sequence of Inteleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits in the
sequence shown as the following.
Addressing sequence for Interleave mode
Data
Access Address
Data 0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
Burst Length
Data 1
...A8 A7 A6 A5 A4 A3 A2 A1 A0
2 words
Data 2
...A8 A7 A6 A5 A4 A3 A2 A1 A0
4 words
Data 3
...A8 A7 A6 A5 A4 A3 A2 A1 A0
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to
the first data read. The minimum values of CAS Latency depends on the frequency of CK. In a write mode, the place of
clock which should input write data is CAS Latency cycles - 1.
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation.
(R-5) Reserved field in the Regular Mode Register
• Reserved bits (A8 to A14)
These bits are reserved for future operations. They must be set to "0" for normal operation.
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256Mb Network-DRAM
Functional Description (Continued)
Extended Mode Register Fields
(E-1) DLL Switch field (A0)
This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled.
(E-2) Output Driver Impedance Control field (A1/A0)
This field is used to choose Output Driver Strength. Four types of Driver Strength are supported.
A6
A1
Output Driver Impedance Control
0
0
Normal Output Driver
0
1
Strong Output Driver
1
0
Weaker Output Driver
1
1
Weakest Output Driver
(E-3) Reserved field (A2 to A5, A7 to A14)
These bits are reserved for future operations and must be set to "0" for normal operation.
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