KODENSHI KK74LV04D

TECHNICAL DATA
KK74LV04
Hex Inverter
The KK74LV04 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT04A.
The KK74LV04 provides six inverting buffers.
•
•
•
•
Wide Operating Voltage: 1.0÷5.5 V
Optimized for Low Voltage applications: 1.0÷3.6 V
Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V
Low Input Current
ORDERING INFORMATION
KK74LV04N
Plastic
KK74LV04D
SOIC
TA = -40° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Input
Output
A
Y
L
H
H
L
PIN 14 =VCC
PIN 7 = GND
1
KK74LV04
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC supply voltage (Referenced to GND)
Value
Unit
-0.5 ÷ +7.0
V
1
DC input diode current
±20
mA
2
DC output diode current
±50
mA
DC output source or sink current
-bus driver outputs
±25
mA
IGND
DC GND current for types with
- bus driver outputs
±50
mA
ICC
DC VCC current for types with
- bus driver outputs
±50
mA
PD
Power dissipation per package, plastic DIP+
SOIC package+
750
500
mW
-65 ÷ +150
°C
260
°C
IIK*
IOK*
Io*
3
Tstg
TL
Storage temperature
Lead temperature, 1.5 mm from Case for 10 seconds
(Plastic DIP ), 0.3 mm (SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SOIC Package: : - 8 mW/°C from 70° to 125°C
*1: VI < -0.5V or VI > VCC+0.5V
*2: Vo < -0.5V or Vo > VCC+0.5V
*3: -0.5V < Vo < VCC+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
VCC =1.2 V
VCC =2.0 V
VCC =3.0 V
VCC =3.6 V
Min
Max
Unit
1.0
5.5
V
0
VCC
V
-40
+125
°C
0
0
0
0
1000
700
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74LV04
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC,
25°C
V
min
max
-40°C ÷
85°C
min max
-40°C ÷
125°C
min max
Unit
VIH
High-Level Input
Voltage
1.2
2.0
3.0
3.6
0.9
1.4
2.1
2.5
-
0.9
1.4
2.1
2.5
-
0.9
1.4
2.1
2.5
-
V
VIL
Low-Level Input
Voltage
1.2
2.0
3.0
3.6
-
0.3
0.6
0.9
1.1
-
0.3
0.6
0.9
1.1
-
0.3
0.6
0.9
1.1
V
VOH
High-Level
Output Voltage
VI = VIL
IO = -50 µA
1.2
2.0
*
1.1
1.92
2.92
-
1.0
1.9
2.9
-
1.0
1.9
2.9
-
V
VI = VIL
IO = -6.0 µA
*
2.48
-
2.34
-
2.20
-
V
1.2
2.0
-
0.09
0.09
0.09
-
0.1
0.1
0.1
-
0.1
0.1
0.1
V
3.0
-
0.33
-
0.4
-
0.5
V
-
-0.1
-
-1.0
-
-1.0
µA
VOL
Low-Level Output VI = VIH
Voltage
IO = 50 µA
VI = VIH or VIL
IO = 6.0 mА
IIL
Low-Level Input
Leakage Current
IIН
High-Level Input VI = VCC
Leakage Current
*
-
0.1
-
1.0
-
1.0
µA
IСС
Quiescent Supply VI = 0 В or VCC
Current
IO = 0 µA
(per Package)
*
-
2.0
-
20
-
40
µA
* : VCC= (3.3±0.3) V
3
KK74LV04
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns, VIL=0V, VIH=VCC, RL=1 kΩ)
Guaranteed Limit
VCC
Symbol
Parameter
25°C
min
max
V
-40°C ÷ 85°C
max
min
-40°C ÷ 125°C
min
max
tTHL, (tTLH)
Output Transition
Time, Any Output
(Figure 1)
1.2
2.0
*
-
70
16
10
-
85
20
13
-
100
24
15
tPHL, (tPLH)
Propagation Delay,
Input A to Output Y
(Figure 1)
1.2
2.0
*
-
90
23
14
-
120
28
18
-
150
34
21
Input Capacitance
3.0
-
-
-
3.5
-
3.5
CI
CPD
Power Dissipation Capacitance (Per
Inverter)
ТА=25°С, VI=0V÷VCC
Unit
ns
pF
pF
42
Used to determine the no-load dynamic power consumption:
PD = CPDVCC2fI+ ∑(CLVCC2fo), fI - input frequency, fo - output frequency (MHz)
∑(CLVCC2fo) – sum of the outputs
tHL
tLH
0.9
0.9
Input А
V1
0.1
VCC
V1
0.1
tPHL
0.9
0.9
Output Y
VCC
V1
V1
0.1
V1 = 0.5 VCC
GND
tPLH
0.1
tTHL
GND
tTLH
Figure 1. Switching Waveforms
VCC
VI
PULSE
GENERATOR
Termination resistance RT – should
be equal to ZOUT of pulse generators
VO
RT
DEVICE
UNDER
TEST
CL
RL
Figure 2. Test Circuit
4
KK74LV04
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
Dimension, mm
8
14
B
7
1
Symbol
MIN
MAX
A
18.67
19.69
B
6.1
7.11
5.33
C
F
L
C
-T- SEATING
PLANE
N
G
M
K
J
H
D
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 012AB)
Dimension, mm
A
14
8
H
B
1
G
P
7
R x 45
C
-TK
D
SEATING
PLANE
M
Symbol
MIN
MAX
A
8.55
8.75
B
3.8
4
C
1.35
1.75
D
0.33
0.51
F
0.4
1.27
G
1.27
H
5.27
J
0°
8°
K
0.1
0.25
1. Dimensions A and B do not include mold flash or protrusion.
M
0.19
0.25
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
P
5.8
6.2
R
0.25
0.5
J
0.25 (0.010) M T C M
NOTES:
F
5