KM62256D Family CMOS SRAM Document Title 32Kx8 bit Low Power CMOS Static RAM Revision History Revision No History Draft Data Remark 0.0 Initial draft May 18, 1997 Design target 0.1 First revision - KM62256DL/DLI ISB1 = 100 → 50µA KM62256DL-L ISB1 = 20 → 10µA KM62256DLI-L ISB1 = 50 → 15µA - CIN = 6 → 8pF, CIO = 8 → 10pF - KM62256D-4/5/7 Family tOH = 5 → 10ns - KM62256DL/DLI IDR = 50→30µA KM62256DL-L/DLI-L I DR = 30 → 15µA April 1, 1997 Preliminily 1.0 Finalize - Remove ICC write value - Improved operating current ICC2 = 70 → 60mA - Improved standby current KM62256DL/DLI ISB1 = 50 → 30µA KM62256DL-L I SB1 = 10 → 5µA KM62256DLI-L ISB1 = 15 → 5µA - Improved data retention current KM62256DL/DLI IDR = 30 → 5µA KM62256DL-L/DLI-L IDR = 15 → 3µA - Remove 45ns part from commercial product and 100ns part from industrial product. Replace test load 100pF to 50pF for 55ns part November 11, 1997 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. Revision 1.0 November 1997 KM62256D Family CMOS SRAM 32Kx8 bit Low Power CMOS Static RAM FEATURES GENERAL DESCRIPTION • • • • • • The KM62256D families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery backup operation with low data retention current. Process Technology : TFT Organization : 32Kx8 Power Supply Voltage : 4.5~5.5V Low Data Retention Voltage : 2V(Min) Three state output and TTL Compatible Package Type : 28-DIP-600B, 28-SOP-450 28-TSOP1-0813.4 F/R PRODUCT FAMILY Power Dissipation Product Family Operating Temperature KM62256DL VCC Range Speed Standby (ISB1, Max) 30µA 551)/70ns Commercial (0~70°C) KM62256DL-L Industrial (-40~85°C) 28-DIP,28-SOP 28-TSOP1-F/R 5µA 4.5 to 5.5V KM62256DLI 60mA 30µA 70ns KM62256DLI-L PKG Type Operating (Icc2, Max) 28-SOP 28-TSOP1-F/R 5µA 1. The parameter is tested with 50pF test load. FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION A14 A12 A7 1 28 2 27 3 26 A6 4 25 A5 5 24 A4 6 23 A3 7 A2 8 A1 28-DIP 28-SOP OE A11 A9 A8 VCC A13 WE WE VCC A13 A14 A12 A8 A7 A6 A9 A5 A4 A11 A3 22 OE 21 A10 9 20 CS A0 10 19 I/O8 I/O1 11 I/O2 12 18 17 I/O7 I/O6 I/O3 13 16 I/O5 VSS 14 15 I/O4 27 3 26 4 25 5 24 6 23 7 8 28-TSOP Type1 - Forward 22 21 20 10 19 11 18 12 17 13 16 14 15 A3 14 15 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 13 16 12 17 11 18 10 19 A10 CS Clk gen. I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 Precharge circuit. A13 A8 A12 A14 A4 Memory array 256 rows 128×8 columns Row select A5 A6 A7 Function 9 8 7 20 28-TSOP Type1 - Reverse 21 22 6 23 5 24 4 25 3 26 2 27 1 28 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10 I/O8 A10 A3 Function CS Data Inputs/Outputs WE Vcc Power OE Write Enable Input Vss Ground Address Inputs NC No connect OE Output Enable Input WE Column select Data cont I/O1 ~I/O8 Chip Select Input I/O Circuit Data cont I/O1 Pin Name CS A0 ~A14 28 2 9 OE Pin Name 1 A0 A1 A2 A9 A11 Control Logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Revision 1.0 November 1997 KM62256D Family CMOS SRAM PRODUCT LIST Commercial Temperature Products(0~70°C) Part Name Industrial Temperature Products(-40~85°C) Function Part Name 28-DIP, 55ns, L-pwr 28-DIP, 55ns, LL-pwr 28-DIP, 70ns, L-pwr 28-DIP, 70ns, LL-pwr 28-SOP, 50ns, L-pwr 28-SOP, 50ns, LL-pwr 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP1 F, 55ns, L-pwr 28-TSOP1 F, 55ns, LL-pwr 28-TSOP1 F, 70ns, L-pwr 28-TSOP1 F, 70ns, LL-pwr 28-TSOP1 R, 55ns, L-pwr 28-TSOP1 R, 55ns, LL-pwr 28-TSOP1 R, 70ns, L-pwr 28-TSOP1 R, 70ns, LL-pwr KM62256DLP-5 KM62256DLP-5L KM62256DLP-7 KM62256DLP-7L KM62256DLG-5 KM62256DLG-5L KM62256DLG-7 KM62256DLG-7L KM62256DLTG-5 KM62256DLTG-5L KM62256DLTG-7 KM62256DLTG-7L KM62256DLRG-5 KM62256DLRG-5L KM62256DLRG-7 KM62256DLRG-7L Function 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP1 F, 70ns, L-pwr 28-TSOP1 F, 70ns, LL-pwr 28-TSOP1 R, 70ns, L-pwr 28-TSOP1 R, 70ns, LL-pwr KM62256DLGI-7 KM62256DLGI-7L KM62256DLTGI-7 KM62256DLTGI-7L KM62256DLRGI-7 KM62256DLRGI-7L FUNCTIONAL DESCRIPTION CS OE I/O Mode Power X High-Z Deselected Standby H High-Z Output Disabled Active L H Dout Read Active X1) L Din Write Active H X L H L L 1) WE 1) 1. X means don′t care (Must be in high or low states) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol Ratings Unit Remark VIN,VOUT -0.5 to 7.0 V - VCC -0.5 to 7.0 V - PD 1.0 W - TSTG -65 to 150 °C - TA TSOLDER 0 to 70 °C KM62256DL -40 to 85 °C KM62256DLI 260°C, 10sec (Lead Only) - - 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Revision 1.0 November 1997 KM62256D Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Symbol Min Typ Max Unit Supply voltage Item Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input high voltage VIH 2.2 - Vcc+0.5V2) V Input low voltage VIL -0.53) - 0.8 V Note: 1. Commercial Product : TA=0 to 70°C, otherwise specified Industrial Product : TA=-40 to 85°C, otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width≤30ns 3. Undershoot : -3.0V in case of pulse width≤30ns 4. Overshoot and undershoot are sampled, not 100% tested CAPACITANCE1) (f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled not, 100% tested DC AND OPERATING CHARACTERISTICS Item Min Typ Max Unit ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIH or VIL, Read - 5 10 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA CS≤0.2V, VIN≤0.2V, V IN≥Vcc -0.2V - 2 5 - 20 Input leakage current Average operating current Symbol Test Conditions Read Write mA ICC2 Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - 45 60 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS=VIH, Other inputs=VIH or VIL Standby Current (CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc - - 1 mA Low Power - 1 30 µA Low Low Power - 0.2 5 µA Revision 1.0 November 1997 KM62256D Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL=50pF+1TTL CL1) 1. Including scope and jig capacitance AC CHARACTERISTICS (Vcc=4.5~5.5V, KM62256D Family:TA=0 to 70°C, KM62256DI Family:TA=-40 to 85°C) Speed Bins Parameter List Symbol 55 ns Min Read Write Units 70ns 1) Max Min Max Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO - 55 - 70 ns Output enable to valid output tOE - 25 - 35 ns Chip select to low-Z output tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 30 ns Output disable to high-Z output tOHZ 0 20 0 30 ns Output hold from address change tOH 10 - 10 - ns Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 40 - 50 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 25 - 30 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns Min Typ Max Unit 2.0 - 5.5 V L-Ver - 1 15 µA LL-Ver - 0.2 3 0 - - 5 - - 1. The parameter is tested with 50pF test load. DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS≥Vcc-0.2V Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V Data retention set-up time tSDR Recovery time tRDR See data retention waveform ms Revision 1.0 November 1997 KM62256D Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tOE OE Data out High-Z tOLZ tLZ tOHZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection. Revision 1.0 November 1997 KM62256D Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 4.5V 2.2V VDR CS≥VCC - 0.2V CS GND Revision 1.0 November 1997 KM62256D Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeter(inch) 28 PIN DUAL INLINE PACKAGE(600mil) 0.25 +0.10 -0.05 +0.004 0.010-0.002 #15 #1 #14 15.24 0.600 #28 13.60± 0.20 0.535± 0.008 0~15° 3.81± 0.20 0.150± 0.008 36.72 MAX 1.446 5.08 0.200 MAX 36.32± 0.20 1.430± 0.008 ( 3.30± 0.30 0.130± 0.012 0.46± 0.10 0.018± 0.004 1.52± 0.10 0.060± 0.004 1.65 ) 0.065 0.38 0.015 MIN 2.54 0.100 28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil) 0~8° #15 11.81± 0.30 0.465± 0.012 #1 8.38± 0.20 0.330± 0.008 #14 0.15 2.59± 0.20 0.102± 0.008 18.69 MAX 0.736 11.43 0.450 #28 +0.10 -0.05 1.02± 0.20 0.040± 0.008 0.006+0.004 -0.002 3.00 0.118MAX 18.29± 0.20 0.720± 0.008 0.10 MAX 0.004 MAX ( 0.89 ) 0.035 0.41± 0.10 0.016± 0.004 1.27 0.050 0.05 MIN 0.002 Revision 1.0 November 1997 KM62256D Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeter(inch) +0.10 -0.05 0.008+0.004 -0.002 0.20 0.10 MAX 0.004 MAX 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F) 13.40± 0.20 0.528± 0.008 #1 #28 0.55 0.0217 #14 0.25 0.010 TYP 0.425 ) 0.017 8.00 0.315 8.40 0.331 MAX ( #15 11.80± 0.10 0.465± 0.004 +0.10 -0.05 +0.004 0.006-0.002 0.15 0~8° 1.00± 0.10 0.039± 0.004 0.05 0.002 MIN 1.20 0.047 MAX 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 0.10 MAX 0.004 MAX 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R) +0.10 -0.05 +0.004 0.008-0.002 0.20 13.40± 0.20 0.528± 0.008 #14 #15 0.55 0.0217 #1 0.25 0.010 TYP 0.425 ) 0.017 8.00 0.315 8.40 0.331 MAX ( #28 11.80± 0.10 0.465± 0.004 +0.10 -0.05 0.006+0.004 -0.002 0.15 1.00± 0.10 0.039± 0.004 0.05 0.002 MIN 1.20 0.047 MAX 0~8° 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 Revision 1.0 November 1997