DRAM MODULE KMM372C80(8)3CK/CS KMM372C80(8)3CK/CS Fast Page Mode 8Mx72 DRAM DIMM with ECC Using 8Mx8, 4K & 8K Refresh, 5V GENERAL DESCRIPTION The Samsung KMM372C80(8)3C is a 8Mx72bits Dynamic RAM high density memory module. The Samsung KMM372C80(8)3C consists of nine CMOS 8Mx8bits DRAMs in SOJ/TSOP-II 400mil packages and two 16 bits driver IC in TSSOP package mounted on a 168-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM372C80(8)3C is a Dual In-line Memory Module and is intended for mounting into 168 pin edge connector sockets. PERFORMANCE RANGE Speed tRAC tCAC tRC tPC -5 50ns 18ns 90ns 35ns -6 60ns 20ns 110ns 40ns FEATURES • Part Identification Part number PKG KMM372C803CK SOJ KMM372C803CS TSOP KMM372C883CK SOJ KMM372C883CS TSOP • • • • • • • • 29 *CAS2 57 30 RAS0 58 31 OE0 59 60 VSS 32 61 A0 33 62 A2 34 63 A4 35 64 A6 36 A8 65 37 66 A10 38 67 A12 39 68 VCC 40 41 RFU 69 42 RFU 70 71 43 VSS OE2 72 44 45 RAS2 73 46 CAS4 74 47 *CAS6 75 76 48 W2 77 49 VCC 50 RSVD 78 51 RSVD 79 52 DQ18 80 53 DQ19 81 82 54 VSS 55 DQ20 83 56 DQ21 84 4K 8K ROR Ref. 4K/64ms 4K/64ms 8K/64ms PIN NAMES Pin Front Pin Front Pin Front VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS RSVD RSVD VCC W0 CAS0 CBR Ref. Fast Page Mode Operation CAS-before-RAS Refresh capability RAS-only and Hidden refresh capability TTL compatible inputs and outputs Single 5V±10% power supply JEDEC standard pinout & Buffered PDpin Buffered input except RAS and DQ PCB : Height(1250mil), single sided component PIN CONFIGURATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Ref. DQ22 DQ23 VCC DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID0 VCC Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS RSVD RSVD VCC RFU *CAS1 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 NOTE : A12 is used for only KMM372C883CK/CS (8K Ref.) Back *CAS3 *RAS1 RFU VSS A1 A3 A5 A7 A9 A11 *A13 VCC RFU B0 VSS RFU *RAS3 *CAS5 *CAS7 PDE VCC RSVD RSVD DQ54 DQ55 VSS DQ56 DQ57 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ58 DQ59 VCC DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 VCC Pin Names Function A0, B0, A1 - A11 Address Input(4K ref.) A0, B0, A1 - A12 Address Input(8K ref.) DQ0 - DQ71 Data In/Out W0, W2 Read/Write Enable OE0, OE2 Output Enable RAS0, RAS2 Row Address Strobe CAS0, CAS4 Column Address Strobe VCC Power(+5V) VSS Ground NC No Connection PDE Presence Detect Enable PD1 - 8 Presence Detect ID0 - 1 ID bit RSVD Reserved Use RFU Reserved for Future Use Pins marked ′* ′ are not used in this module. PD & ID Table Pin 50NS 60NS PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 1 0 1 1 0 0 0 0 1 0 1 1 0 1 1 0 ID0 0 0 0 ID1 0 PD Note :PD & ID Terminals must each be pulled up through a resistor to VCC at the next higher level assembly. PDs will be either open (NC) or driven to VSS via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C ID Note : IDs will be either open (NC) or connected directly to VSS without a buffer. ID : 0 for Vss & 1 for N.C DRAM MODULE KMM372C80(8)3CK/CS FUNCTIONAL BLOCK DIAGRAM RAS0 W0 OE0 CAS0 A0 A1-A11(A12) RAS2 W2 OE2 CAS4 B0 A1-A11(A12) U0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 U2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 U3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 U4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 NOTE : A12 is used for only KMM372C880CK/CS(8K Ref.) U5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U6 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 U7 U8 Vcc 0.1 or 0.22uF Capacitor under each DRAM To all DRAMs Vss A0 B0 A1-A11(A12) W0, OE0 W2, OE2 U0-U4 U5-U8 U0-U8 U0-U4 U5-U8 DRAM MODULE KMM372C80(8)3CK/CS ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol Rating Unit VIN, VOUT VCC Tstg PD IOS -1 to +7.0 -1 to +7.0 -55 to +125 9 50 V V °C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min Typ Max Unit VCC VSS VIH VIL 4.5 0 2.4 5.0 0 - 5.5 0 V V V V -1.0*2 VCC*1 0.8 *1 : VCC+2.0V at pulse width≤20ns, which is measured at VCC. *2 : -2.0V at pulse width≤20ns, which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol Speed ICC1 KMM372C803CK/CS KMM372C883CK/CS Unit Min Max Min Max -5 -6 -- 1080 990 - 810 720 mA mA ICC2 Don′t care - 100 - 100 mA ICC3 -5 -6 - 1080 990 - 810 720 mA mA ICC4 -5 -6 - 630 540 - 540 450 mA mA ICC5 Don′t care - 30 - 30 mA ICC6 -5 -6 - 1080 990 - 810 720 mA mA II(L) IO(L) Don′t care -10 -5 10 5 -10 -5 10 5 uA uA VOH VOL Don′t care 2.4 - 0.4 2.4 - 0.4 V V ICC1*: Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=V IH) ICC3*: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4*: Fast Page Mode Current * (RAS=V IL, CAS cycling : tPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6*: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0≤VIN≤Vcc+0.5V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0V≤VOUT≤Vcc) VOH : Output High Voltage Level (IOH = -5mA) VOL : Output Low Voltage Level (IOL = 4.2mA) * NOTE : ICC1, ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one Fast page mode cycle time, tPC. DRAM MODULE KMM372C80(8)3CK/CS CAPACITANCE (TA = 25°C, f = 1MHz) Item Symbol Min Max Unit Input capacitance[A0, B0, A1 - A12] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0, RAS2] Input capacitance[CAS0, CAS4] Input/Output capacitance[DQ0 - 71] CIN1 CIN2 CIN3 CIN4 CDQ - 20 20 45 20 17 pF pF pF pF pF AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referencde to CAS Read command hold referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data in set-up time Data in hold time Refresh period(4K & 8K) Write command set-up time CAS to W delay time Column address to W delay time CAS prechange to W delay time RAS ro W delay time Symbol tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCWD tAWD tCPWD tRWD -5 Min -6 Max Min Max Unit 90 110 ns 133 155 ns Note 50 60 ns 3,4 18 20 ns 3,4,5,11 30 35 ns 3,10,11 5 ns 3,11 5 18 5 5 20 ns 6,11 1 50 1 50 ns 2 30 50 40 10K 60 ns 10K ns 18 20 ns 11 45 55 ns 11 13 10K 15 10K ns 18 32 18 40 ns 4,11 13 20 13 25 ns 10,11 ns 11 10 10 5 5 ns 11 8 8 ns 11 0 0 ns 10 10 ns 30 35 ns 0 0 ns 0 0 ns 8 -2 -2 ns 8,11 11 10 10 ns 10 10 ns 20 20 ns 13 15 ns -2 -2 ns 9,11 15 15 ns 9,11 64 64 11 ms 0 0 ns 7 36 40 ns 7 48 55 ns 7 53 60 ns 7 73 85 ns 7,11 DRAM MODULE KMM372C80(8)3CK/CS AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.) Parameter CAS setup time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Fast page mode cycle time Fast page mode read-modify-write cycle time CAS precharge time(Fast page cycle) RAS pulse width(Fast page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Symbol tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tRHCP tWRP tWRH tOEA tOED tOEZ tOEH -5 Min -6 Max Min Max Unit Note 11 10 10 ns 8 8 ns 11 3 3 ns 11 ns 3,11 35 40 35 40 ns 76 85 ns 10 50 10 200K 60 ns 200K ns 35 40 ns 11 15 15 ns 11 8 8 ns 11 ns 11 ns 11 ns 11 18 18 5 20 20 18 13 5 20 15 ns Present Detect Read Cycle PDE to Valid PD bit PDE to PD bit Inactive tPD tPDOFF 10 2 7 2 10 ns 7 ns NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD≥tRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If tWCS≥tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tRWD≥tRWD(min), tCWD≥tCWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min). The cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. The timing skew from the DRAM to the DIMM resulted from the addition of buffers. DRAM MODULE KMM372C80(8)3CK/CS READ CYCLE tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRCD tCRP tRSH tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCH tRCS W tRRH VIH VIL - tOFF tAA OE VIH - tOEZ tOEA VIL - tCAC DQ VOH VOL - tRAC OPEN tCLZ DATA-OUT Don′t care Undefined DRAM MODULE KMM372C80(8)3CK/CS WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tCSH tCRP CAS tRCD tRSH tCAS VIH VIL - tRAD tASR A tCRP VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL tWCS W OE tWP VIL - VIH VIL - tDS DQ tWCH VIH - VIH VIL - tDH DATA-IN Don′t care Undefined DRAM MODULE KMM372C80(8)3CK/CS WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS VIL - tRSH tCAS VIH VIL - tCRP tRAD tASR A tRCD VIH - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tCWL tRWL W OE VIH - tWP VIL - VIH VIL - tOED tOEH tDS DQ VIH VIL - tDH DATA-IN Don′t care Undefined DRAM MODULE KMM372C80(8)3CK/CS READ - MODIFY - WRTIE CYCLE tRWC tRP tRAS VIH - RAS VIL - tCRP tRCD tRSH tCAS VIH - CAS VIL - tASR tRAD tRAH tASC tCAH tCSH VIH - A VIL - ROW ADDR COLUMN ADDRESS tRWL tAWD tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - tCLZ tCAC tAA DQ VI/OH VI/OL - tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined DRAM MODULE KMM372C80(8)3CK/CS FAST PAGE READ CYCLE NOTE : DOUT = OPEN tRP tRASP RAS VIH - tRHCP VIL - ¡ó tCRP CAS VIH - tRAD tASC VIL - VIH VIL - tCP tCAS tCAS tASR A tPC tCP tRCD tRSH tCAS ¡ó tCSH tRAH tCAH tASC COLUMN ADDRESS ROW ADDR tCAH COLUMN ADDRESS tASC ¡ó tCAH COLUMN ADDRESS ¡ó tRRH tRCS W tRCH tRCS VIH - tCAC tOEA VIH - ¡ó VIL - ¡ó tAA DQ ¡ó tRCH VIL - tCAC tOEA OE tRCS VOH VOL - tRAC tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ tOEZ VALID DATA-OUT tCAC tOEA tAA tOFF tCLZ tOFF tOEZ VALID DATA-OUT Don′t care Undefined DRAM MODULE KMM372C80(8)3CK/CS FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRP tRASP RAS tRHCP VIH VIL - ¡ó tPC tCRP CAS VIH - VIH VIL - tCSH tCAH tRAH tASC COLUMN ADDRESS ROW ADDR VIH - tWCH tCAH tASC ¡ó tWCS tWP ¡ó tWCH tWP tCAH COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - ¡ó VIL - VIH VIL - tCWL tRWL tCWL VIH - ¡ó tDS DQ tCAS COLUMN ADDRESS tCWL OE tRSH ¡ó tWCS W tCP tCAS tCAS tRAD tASC VIL - tASR A tPC tCP tRCD tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN VALID DATA-IN ¡ó Don′t care Undefined DRAM MODULE KMM372C80(8)3CK/CS FAST PAGE READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH VIL - tRSH tRCD CAS tCP VIH - tCRP tCAS tCAS VIL - tRAD tPRWC tRAH tASR A VIH VIL - ROW ADDR tCAH tASC COL. ADDR COL. ADDR tRWL tRCS W tRAL tCAH tASC tCWL VIH - tCWL tWP VIL - tWP tCWD tCWD tAWD OE tAWD tCPWD tRWD tOEA VIH - tOEA VIL - tOED tCAC tCAC tAA tRAC DQ tOEZ tDH tOED tDH tAA tDS tDS tOEZ VI/OH VI/OL - tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined DRAM MODULE KMM372C80(8)3CK/CS RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Don′t care DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC tCSR VIH - tWRP W tCHR VIL - tWRH VIH VIL - tOFF DQ VOH VOL - OPEN Don′t care Undefined DRAM MODULE KMM372C80(8)3CK/CS HIDDEN REFRESH CYCLE ( READ ) tRC tRC tRP tRAS RAS VIH VIL - tCRP CAS tRP tRAS tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tRCS W tRRH tWRP VIH VIL - tAA OE VIH - tOEA VIL - tOFF tCAC tRAC DQ VOH VOL - OPEN tCLZ tOEZ DATA-OUT Don′t care Undefined DRAM MODULE KMM372C80(8)3CK/CS HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS VIH - tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A tRAS VIL - tCRP CAS tRC tRP tRAS VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tWRP W OE VIH - tWCS tWCH tWP VIL - VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Don′t care Undefined DRAM MODULE KMM372C80(8)3CK/CS CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE tRP VIH - RAS tRAS VIL VIH - CAS tCPT tCSR tRSH tCAS tCHR VIL - tRAL tASC VIH - A VIL - READ CYCLE tWRP tWRH tRRH tAA tRCS tRCH tCAC VIH - W VIL VIH - OE VIL - tOEA tCLZ VOH - DQ tCAH COLUMN ADDRESS tOEZ DATA-OUT VOL - WRITE CYCLE W tOFF tWRP tRWL tWRH VIH - tCWL tWCS tWCH VIL - tWP OE VIH VIL - tDS DQ tDH VIH DATA-IN VIL - READ-MODIFY-WRITE tWRP W tWRH tAWD tRCS tCWL tCWD VIH - tRWL tWP tCAC VIL - tAA tOEA OE VIH - tOED VIL - tCLZ DQ tOEZ tDH tDS VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Don′t care NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM. Undefined DRAM MODULE KMM372C80(8)3CK/CS CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care tRP RAS tRASS tRPS VIH VIL - tRPC tRPC tCP CAS tCHS VIH - tCSR VIL - tOFF DQ VOH - OPEN VOL - tWRP W tWRH VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC VIH - tCSR tWTS W tCHR VIL - tWTH VIH VIL - tOFF DQ VOH VOL - OPEN Don′t care Undefined DRAM MODULE KMM372C80(8)3CK/CS PACKAGE DIMENSIONS Units : Inches (millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) 0.118 (3.000) R 0.079 (R 2.000) 0.700 0.350 (8.890) .450 (11.430) 0.100Min C 0.250 (6.350) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) (2.540Min) B A .118DIA±.004 (3.000DIA±.100) (17.780) 0.118 (3.000) 1.250 (31.75) 0.157±0.004 (4.000±0.100) 4.550 (115.57) ( Front view ) 0.100Max (2.54Max) TSOPII (4.19 Min) 0.165 Min 0.200Max (5.08Max) SOJ 0.050±0.0039 (1.270±0.10) 0.100 Min 0.250 (6.350) 0.250 (6.350) 0.1230±.0050 (3.125±.125) 0.079±.0040 (2.000±.100) Detail A 0.1230±.0050 (3.125±.125) 0.079±.0040 (2.000±.100) Detail B Tolerances : ±.005(.13) unless otherwise specified The used device is 8Mx8 DRAM with Fast Page mode, SOJ or TSOP II. DRAM Part No. : KMM372C803CK/CS - KM48C8100CK, KM48C8100CS KMM372C883CK/CS - KM48C8000CK, KM48C8000CS (2.540 Min) ( Back view ) 0.039±.002 (1.000±.050) 0.01Max (0.25 Max) 0.050 (1.270) Detail C