ANPEC 2176AQBI-TRG

APA2176/2176A
270mW Stereo Cap-Free Headphone Driver
Features
General Description
•
•
The APA2176/2176A is a stereo, fixed gain, and cap-free
headphone driver which is available in TQFN4x4 20-pin,
No Output Capacitor Required
Dual Supply Voltage (PVDD>VDD)
TQFN3x3 16-pin (APA2176A) or TSSOP-16 package. Dual
supply voltage provides higher efficiency and better power
– VDD=1.8 ~5.5V
•
•
– PVDD=2.2 ~ 5.5V
ripple rejection.
The APA2176/2176A is designed with ground-reference
Meeting VISTA Requirements
Output Power
output and no need the output capacitors for DC blocking.
The advantages of eliminating the output capacitor are
at 1% THD+N
-200mW, at VDD=3.3V, PVDD=5.0V, RL=16Ω
saving the cost, PCB’s space, and component height.
The built-in gain setting can minimize the external com-
-55mW, at VDD=1.8V, PVDD=3.0V, RL=16Ω
ponent counts and save the PCB space. High PSRR provides increased immunity to noise and RF rectification. In
at 10% THD+N
-270mW, at VDD=3.3V, PVDD=5.0V, RL=16Ω
•
•
•
•
•
addition to these features, a fast start-up time and small
package size make the APA2176/2176A an ideal choice
-70mW, at VDD=1.8V, PVDD=3.0V, RL=16Ω
Less External Components Required
for portable multimedia devices.
Moreover, the APA2176/2176A is also equipped other
High PSRR: 80dB at 217Hz
Fast Start-Up Time : 120µs
Short-Circuit and Thermal Protection
features. For example, at THD+N=1%, it is capable of
driving 200mW at V DD=3.3V, PV DD=5.0V into 16Ω. In
Surface-Mount Package
addition, it provides thermal and short circuit protections.
– TQFN4x4-20B (with Enhanced Thermal Pad)
Simplified Application Circuit
– TSSOP-16
– TQFN3x3-16 (with Enhanced Thermal Pad)
•
(for APA2176A)
R-CH
Input
Lead Free and Green Devices Available
RIN
(RoHS Compliant)
L-CH
Input
Applications
•
•
•
•
ROUT
LIN
Stereo
Headphone
APA2176/2176A
LOUT
Headsets
PDAs
Shutdown
Control
Portable Multimedia Devices
RSD
LSD
Notebooks
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
1
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APA2176/2176A
Ordering and Marking Information
Package Code
QB : TQFN4x4-20B O : TSSOP-16
QB : TQFN3x3-16 (APA2176A)
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APA2176
APA2176A
Assembly Material
Handling Code
Temperature Range
Package Code
APA2176
QB :
APA2176
XXXXX
XXXXX - Date Code
APA2176
O:
APA2176
XXXXX
XXXXX - Date Code
APA2176A
QB :
APA
2176A
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
NC 16
10 VDD
GND 17
GND 14
8 NC
APA2176
PVDD 19
LSD 15
7 VSS
NC 20
9 ROUT
10 LIN
NC 13
9 LOUT
LSD 18
11 RSD
12 RIN
11 ROUT
12 NC
13 LIN
14 RSD
15 RIN
Pin Configuration
8 VDD
7 LOUT
APA2176A
PVDD 16
6 VSS
5 CVSS
TQFN4x4-20B (Top View)
NC 4
CP- 3
PGND 2
CP+ 1
CVSS 5
NC 4
CP- 3
PGND 2
CP+ 1
6 NC
TQFN3x3-16 (Top View)
=Thermal Pad (connected the Thermal Pad to ground plane for better heat dissipation)
NC 1
PVDD 2
NC 3
CP+ 4
PGND 5
APA2176
CP- 6
CVSS 7
VSS 8
16 LSD
15 GND
14 RIN
13 RSD
12 LIN
11 ROUT
10 VDD
9 LOUT
TSSOP-16 (Top View)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
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APA2176/2176A
Absolute Maximum Ratings (Note 1)
(Over operating free-air temperature range unless otherwise noted.)
Symbol
VDD
PVDD
Parameter
Rating
Unit
Supply Voltage (VDD to GND)
-0.3 to 6
V
Charge Pump Supply Voltage (PVDD to PGND)
-0.3 to 6
V
-0.3 to 0.3
V
-0.3 to VDD+0.3
V
-6 to 0.3
V
VSS-0.3 to VDD+0.3
V
V
VPGND_GND
PGND to GND Voltage
VRSD, VLSD
Input Voltage (RSD and LSD to GND)
VSS, CVSS
VSS and CVSS to GND and PGND Voltage
VROUT, VLOUT
ROUT and LOUT to GND Voltage
VCP+
CP+ to PGND Voltage
-0.3 to PVDD+0.3
VCP-
CP- to PGND Voltage
CVSS-0.3 to 0.3
TJ
TSTG
TSDR
Maximum Junction Temperature
V
ο
C
150
Storage Temperature Range
ο
C
-65 to +150
Maximum Lead Soldering Temperature, 10 Seconds
ο
C
260
PD
Power Dissipation
Internally Limited
W
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics (Note 2,3)
Symbol
Parameter
Typical Value
Unit
Junction-to-Ambient Resistance in Free Air
θJA
θJC
TQFN3x3-16
TQFN4x4-20B
TSSOP16
55
43
100
TQFN3x3-16
TQFN4x4-20B
10
8
o
C/W
Junction-to-Case Resistance in Free Air
o
C/W
Note 2: Please refer to “Thermal Pad Consideration”. 2 layered 5 in2 printed circuit boards with 2oz trace and copper through several
thermal vias. The thermal pad is soldered on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TQFN3x3-16 and TQFN4x4-20B
packages.
Recommended Operating Conditions (Note 4)
Symbol
Range
Unit
VDD
Supply Voltage
Parameter
1.8 ~ 5.5
V
PVDD
Charge Pump Power Supply Voltage
2.2 ~ 5.5
V
VIH
High Level Threshold Voltage
RSD, LSD
VIL
Low Level Threshold Voltage
RSD, LSD
VICM
Common Mode Input Voltage
0.6PVDD ~ PVDD
0 ~ 0.3PVDD
~ VDD-1
V
V
V
TA
Ambient Temperature
-40 ~ 85
o
TJ
Junction Temperature
-40 ~ 125
o
RL
Headphone Resistance
14 ~
C
C
Ω
Note 4: Refer to the typical application circuit.
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
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APA2176/2176A
Electrical Characteristics
Unless otherwise specified, these specifications apply over VDD=3.3V, PVDD=5V, VPGND=VGND=0V, and CCPO=CCPF=2.2µF. Typical
values are at TA=25oC.
Symbol
Parameter
APA2176/2176A
Test Conditions
Unit
Min.
Typ.
Max.
-
2.0
4.0
mA
SUPPLY CURRENT
IDD
IPVDD
VDD Supply Current
PVDD Supply Current
ISD(VDD)
VDD Shutdown Current
VRSD = VLSD = 0
ISD(PVDD)
PVDD Shutdown Current
VRSD = VLSD = 0
-
3.2
6.5
mA
-
1.0
5.0
µA
-
1.0
5.0
µA
450
510
570
kHz
6
7
9
Ω
CHARGE PUMP
fOSC
Switching Frequency
Req
Charge Pump Equivalent
Resistance
CCPO=CCPF=2.2µF
POWER-ON-RESET
Rising VDD Threshold
PVDD=5V
1.67
1.7
1.73
V
Falling VDD Threshold
PVDD=5V
1.57
1.6
1.63
V
Av
Internal Voltage Gain
No Load
-1.55
-1.5
-1.45
V/V
∆AV
Gain Match
-
1.0
-
%
12
14
16
kΩ
AMPLIFIERS
Ri
Input Resistance
SR
Slew Rate
-
2.5
-
V/µs
CL
Maximum Capacitive Load
-
400
-
pF
Start-Up Time from Shutdown
-
120
-
µs
200
150
-
125
270
200
-
170
Tstart-up
VDD=3.3V, PVDD=5.0V, TA=25°
C
PO
THD+N
Crosstalk
PSRR
Output Power
Total Harmonic Distortion Plus
Noise
Channel Separation
THD+N = 1%, fin=1kHz, in Phase
RL = 16Ω
RL = 32Ω
THD+N = 10%, fin=1kHz, in Phase
RL = 16Ω
RL = 32Ω
fin = 1kHz
PO = 140mW, RL = 16Ω
PO = 105mW, RL = 32Ω
VO = 1.7Vrms, RL = 10kΩ
fin = 1kHz
PO = 140mW, RL = 16Ω
VO = 1.7Vrms, RL = 10kΩ
-
0.04
0.03
0.002
mW
-
%
-
78
90
-
dB
Power Supply Rejection Ratio
RL = 16Ω, fin=217Hz
-
90
-
dB
Output Offset Voltage
RL = 32Ω
-5
-
5
mV
S/N
Signal to Noise Ratio
With A-weighting Filter
PO = 105mW, RL = 32Ω
-
95
-
dB
Vn
Noise Output Voltage
RL = 32Ω
-
15
-
µV
(rms)
VOS
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
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APA2176/2176A
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VDD=3.3V, PVDD=5V, V PGND=VGND=0V, and CCPO=CCPF=2.2µF. Typical
values are at TA=25oC.
Symbol
Parameter
APA2176/2176A
Test Conditions
Unit
Min.
Typ.
Max.
55
40
-
35
70
55
-
45
VDD=1.8V, PVDD=3.0V, TA=25°
C
PO
THD+N
Crosstalk
PSRR
Output Power
Total Harmonic Distortion Plus Noise
Channel Separation
THD+N = 1%, fin=1kHz, in Phase
RL = 16Ω
RL = 32Ω
THD+N = 10%, fin=1kHz, in Phase
RL = 16Ω
RL = 32Ω
fin = 1kHz
PO = 40mW, RL = 16Ω
PO = 30mW, RL = 32Ω
VO = 0.9Vrms, RL = 10kΩ
fin = 1kHz
PO = 40mW, RL = 16Ω
VO = 0.9Vrms, RL = 10kΩ
-
0.04
0.03
0.002
mW
-
%
-
78
90
-
dB
Power Supply Rejection Ratio
RL = 16Ω, fin=217Hz
-
82
-
dB
VOS
Output Offset Voltage
RL = 32Ω
-5
-
5
mV
S/N
Signal to Noise Ratio
With A-weighting Filter
PO = 30mW, RL = 32Ω
-
95
-
dB
Vn
Noise Output Voltage
RL = 32Ω
-
15
-
µV
(rms)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
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APA2176/2176A
Typical Operating Characteristics
THD+N vs. Output Power
THD+N vs. Output Power
10
10
VDD=3.3V
PVDD=5.0V
RL=16Ω
Cin=1µF
BW<80kHz
Stereo, in Phase
1
THD+N (%)
THD+N (%)
1
VDD=3.3V
PVDD=5.0V
RL=32Ω
Cin=1µF
BW<80kHz
Stereo, in Phase
fin=20kHz
0.1
fin=20kHz
0.1
fin=1kHz
fin=1kHz
fin=20Hz
fin=20Hz
0.01
0.01
0
50
100
150
200
250
300
350
0
Output Power (mW)
VDD=3.3V
PVDD=5.0V
RL=10kΩ
Cin=1µF
BW<80kHz
Stereo, in Phase
200
250
VDD=2.8V
PVDD=3.6V
RL=16Ω
Cin=1µF
BW<80kHz
Stereo, in Phase
1
THD+N (%)
THD+N (%)
150
THD+N vs. Output Power
10
1
100
Output Power (mW)
THD+N vs. Output Voltage
10
50
0.1
fin =20kHz
fin=20kHz
0.1
fin=1kHz
0.01
fin=20Hz
fin=1kHz
fin=20Hz
0.001
0.01
0
1
2
3
4
0
200
VDD=2.8V
PVDD=3.6V
RL=10kΩ
Cin=1µF
BW<80kHz
Stereo, in Phase
1
THD+N (%)
THD+N (%)
150
10
VDD=2.8V
PVDD=3.6V
RL=32Ω
Cin=1µF
BW<80kHz
Stereo, in Phase
1
100
THD+N vs. Voltage
THD+N vs. Output Power
10
50
Output Power (mW)
Output Voltage (Vrms)
fin=20kHz
0.1
0.1
fin=20kHz
0.01
fin=1kHz
fin=1kHz
fin=20Hz
fin=20Hz
0.01
0
30
60
90
120
0.001
150m
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
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1
2
3
Output Voltage (Vrms)
Output Power (mW)
6
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APA2176/2176A
Typical Operating Characteristics (Cont.)
THD+N vs. Output Power
THD+N vs. Output Power
10
10
VDD=1.8V
PVDD=3.0V
RL=16Ω
Cin=1µF
BW<80kHz
Stereo, in Phase
1
THD+N (%)
THD+N (%)
1
VDD=1.8V
PVDD=3.0V
RL=32Ω
Cin=1µF
BW<80kHz
Stereo, in Phase
fin=20kHz
0.1
fin=20kHz
0.1
fin=1kHz
fin=1kHz
fin=20Hz
fin=20Hz
0.01
0
20
40
60
80
0.01
100
0
THD+N vs. Voltage
40
50
60
VDD=1.8V
PVDD=2.4V
RL=16Ω
Cin=1µF
BW<80kHz
Stereo, in Phase
1
THD+N (%)
THD+N (%)
30
THD+N vs. Output Power
10
VDD=1.8V
PVDD=3.0V
RL=10kΩ
Cin=1µF
BW<80kHz
Stereo, in Phase
1
20
Output Power (mW)
Output Power (mW)
10
10
0.1
fin=20kHz
fin=20kHz
0.1
fin=1kHz
0.01
fin=1kHz
fin=20Hz
fin=20Hz
0.001
0
0.5
1
1.5
0.01
2
0
10
VDD=1.8V
PVDD=2.4V
RL=32Ω
Cin=1µF
BW<80kHz
Stereo, in Phase
1
THD+N (%)
THD+N (%)
1
40
60
80
THD+N vs. Voltage
THD+N vs. Output Power
10
20
Output Power (mW)
Output Voltage (Vrms)
fin=20kHz
0.1
VDD=1.8V
PVDD=2.4V
RL=10kΩ
Cin=1µF
BW<80kHz
Stereo, in Phase
0.1
fin=20kHz
0.01
fin=1kHz
fin=1kHz
fin=20Hz
fin=20Hz
0.01
0
10
20
30
40
50
0.001
0
60
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
0.5
1
1.5
2
Output Voltage (Vrms)
Output Power (mW)
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APA2176/2176A
Typical Operating Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Frequency
10
10
VDD=3.3V
PVDD=5.0V
RL=16Ω
PO=140mW
Cin=1µF
BW<22kHz
1
THD+N (%)
THD+N (%)
1
VDD=3.3V
PVDD=5.0V
RL=32Ω
PO=105mW
Cin=1µF
BW<22kHz
0.1
Right channel
0.1
Right channel
Left channel
Left channel
0.01
0.01
0.006
0.006
20
100
1k
20
10k 20k
100
10
VDD=3.3V
PVDD=5.0V
RL=10kΩ
VO=1.7Vrms
Cin=1µF
BW<22kHz
VDD=2.8V
PVDD=3.6V
RL=16Ω
PO=70mW
Cin=1µF
BW<22kHz
1
THD+N (%)
THD+N (%)
10k 20k
THD+N vs. Frequency
THD+N vs. Frequency
10
1
1k
Frequency (Hz)
Frequency (Hz)
0.1
0.1
Right channel
0.01
Right channel
Left channel
0.001
0.01
Left channel
0.006
0.0006
20
100
1k
20
10k 20k
100
10
VDD=2.8V
PVDD=3.6V
RL=32Ω
PO=60mW
Cin=1µF
BW<22kHz
VDD=2.8V
PVDD=3.6V
RL=10kΩ
VO=1.4Vrms
Cin=1µF
BW<22kHz
1
THD+N (%)
THD+N (%)
10k 20k
THD+N vs. Frequency
THD+N vs. Frequency
10
1
1k
Frequency (Hz)
Frequency (Hz)
0.1
Right channel
0.1
0.01
Right channel
Left channel
0.01
Left channel
0.001
0.006
0.0006
20
100
1k
10k 20k
20
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
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1k
10k 20k
Frequency (Hz)
8
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APA2176/2176A
Typical Operating Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Frequency
10
10
VDD=1.8V
PVDD=3.0V
RL=16Ω
PO=40mW
Cin=1µF
BW<22kHz
0.1
1
THD+N (%)
THD+N (%)
1
VDD=1.8V
PVDD=3.0V
RL=32Ω
PO=30mW
Cin=1µF
BW<22kHz
Right channel
0.1
Right channel
Left channel
0.01
Left channel
0.01
0.001
20
100
1k
0.001
10k 20k
20
100
Frequency (Hz)
10k 20k
THD+N vs. Frequency
THD+N vs. Frequency
10
10
VDD=1.8V
PVDD=3.0V
RL=10kΩ
1 VO=0.9Vrms
Cin=1µF
BW<22kHz
THD+N (%)
THD+N (%)
1k
Frequency (Hz)
0.1
VDD=1.8V
PVDD=2.4V
RL=16Ω
1 PO=23mW
Cin=1µF
BW<22kHz
0.1
Right channel
Left channel
0.01
0.01
Right channel
0.001
Left channel
0.0006
20
100
1k
0.001
20
10k 20k
100
Frequency (Hz)
10
10
VDD=1.8V
PVDD=2.4V
RL=32Ω
PO=23mW
Cin=1µF
BW<22kHz
1
THD+N (%)
THD+N (%)
10k 20k
THD+N vs. Frequency
THD+N vs. Frequency
1
1k
Frequency (Hz)
0.1
Right channel
VDD=1.8V
PVDD=2.4V
RL=10kΩ
VO=0.9Vrms
Cin=1µF
BW<22kHz
0.1
0.01
Left channel
0.01
Right channel
Left channel
0.001
20
100
1k
0.0006
20
10k 20k
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
100
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APA2176/2176A
Typical Operating Characteristics (Cont.)
Crosstalk vs. Frequency
Crosstalk vs. Frequency
+0
+0
VDD=3.3V
PVDD=5.0V
RL=16Ω
PO=140mW
Cin=1µF
-20
Crosstalk (dB)
-30
-40
-30
-60
-70
Right to Left
-80
Left to Right
-90
-40
-50
-60
-70
-80
-100
-110
-110
100
200
500
1k
Left to Right
-90
-100
50
VDD=3.3V
PVDD=5.0V
RL=10kΩ
VO=1.7Vrms
Cin=1µF
-20
-50
-120
20
T
-10
Crosstalk (dB)
-10
2k
5k
-120
10k 20k
Right to Left
20
50
100
Frequency (Hz)
2k
5k
10k 20k
+0
VDD=1.8V
PVDD=3.0V
RL=16Ω
PO=40mW
Cin=1µF
-20
-30
-40
-20
-30
-50
-60
Right to Left
-70
-80
Left to Right
-90
-40
-50
-60
-70
-80
-100
-110
-110
50
100
200
500
1k
Left to Right
-90
-100
-120
20
VDD=1.8V
PVDD=3.0V
RL=10kΩ
VO=0.9Vrms
Cin=1µF
-10
Crosstalk (dB)
-10
Crosstalk (dB)
1k
Crosstalk vs. Frequency
Crosstalk vs. Frequency
2k
5k
Right to Left
-120
10k 20k
20
50
100
Frequency (Hz)
200
500
1k
2k
5k
10k 20k
Frequency (Hz)
Output Noise Voltage vs. Frequency
Output Noise Voltage vs. Frequency
50µ
50µ
20µ
Output Noise Voltage (Vrms)
Output Noise Voltage (Vrms)
500
Frequency (Hz)
+0
Right channel
Left channel
10µ
VDD=3.3V
PVDD=5.0V
RL=16Ω
Cin=1µF
A-Weighting
1µ
200
20
100
1k
Right channel
Left channel
10µ
VDD=3.3V
PVDD=5.0V
RL=10kΩ
Cin=1µF
A-Weighting
1µ
20
10k 20k
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
20µ
10
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APA2176/2176A
Typical Operating Characteristics (Cont.)
Output Noise Voltage vs. Frequency
Output Noise Voltage vs. Frequency
50µ
10µ
Left channel
VDD=1.8V
PVDD=3.0V
RL=16Ω
Cin=1µF
A-Weighting
1µ
20µ
100
1k
10k 20k
Left channel
10µ
VDD=1.8V
PVDD=3.0V
RL=10kΩ
Cin=1µF
A-Weighting
1µ
20
Right channel
20
100
Frequency (Hz)
1k
Frequency (Hz)
Frequency Response
Frequency Response
+4
+220
+4
+200
+3
+220
Gain
+180
Phase
VDD=3.3V
PVDD=5.0V
RL=16Ω
Cin=1µF
+0
10
100
1k
10k
Gain (dB)
Gain (dB)
+2
Phase (deg)
Gain
+3
+1
+2
+180
Phase
VDD=3.3V
PVDD=5.0V
RL=10kΩ
Cin=1µF
+1
+160
+0
10
+140
200k
100
1k
10k
Frequency (Hz)
Frequency Response
Frequency Response
+220
+4
+200
+3
VDD=1.8V
PVDD=3.0V
RL=16Ω
Cin=1µF
100
1k
10k
Gain (dB)
+180
Phase
Phase (deg)
+2
+1
+160
+140
200k
+220
Gain
Gain
+3
Gain (dB)
+200
Frequency (Hz)
+4
+0
10
10k 20k
Phase (deg)
Right channel
+2
+180
Phase
VDD=1.8V
PVDD=3.0V
RL=10kΩ
Cin=1µF
+1
+160
+0
10
+140
200k
100
1k
10k
+160
+140
200k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
+200
Phase (deg)
20µ
Output Noise Voltage (Vrms)
Output Noise Voltage (Vrms)
50µ
11
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APA2176/2176A
Typical Operating Characteristics (Cont.)
PSRR vs. Frequency
-20
TT
T
V
=3.3V
DD
PVDD=5.0V
RL=16Ω
Cin=1µF
Vrr=200mVrms
-30
-40
-50
-40
-50
-60
Left channel
-70
-80
-90
Right channel
-60
-80
-110
-110
1k
Right channel
-90
-100
100
Left channel
-70
-100
-120
20
VDD=3.3V
PVDD=5.0V
RL=10kΩ
Cin=1µF
Vrr=200mVrms
-30
PSRR (dB)
PSRR (dB)
PSRR vs. Frequency
-20
-120
20
10k 20k
100
1k
Frequency (Hz)
PSRR vs. Frequency
PSRR vs. Frequency
-20
T
-40
-50
T
-30
-40
-50
-60
PSRR (dB)
PSRR (dB)
-20
VDD=1.8V
PVDD=3.0V
RL=16Ω
Cin=1µF
Vrr=200mVrms
-30
-70
Left channel
-80
-90
T
VDD=1.8V
PVDD=3.0V
RL=10kΩ
Cin=1µF
Vrr=200mVrms
-60
-70
Left channel
-80
-90
Right channel
Right channel
-100
-100
-110
-110
-120
20
100
1k
-120
20
10k 20k
100
Charge Pump Supply Current
vs. Supply Voltage
10k 20k
Supply Current vs. Supply Voltage
4.0
3.0
3.0
Supply Current (mA)
Supply Current (mA)
1k
Frequency (Hz)
Frequency (Hz)
2.0
VDD=3.3V
IVDD=2.0mA
No Load
1.0
0.0
10k 20k
Frequency (Hz)
2.0
1.0
PVDD=5.0V
IPVDD=3.2mA
No Load
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.5
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
2.0
2.5
3.0
3.5
4.0
4.5
Supply Voltage (V)
Charge Pump Supply Voltage (V)
12
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APA2176/2176A
Typical Operating Characteristics (Cont.)
Charge Pump Shutdown Current
vs. Supply Voltage
Shutdown Current vs. Supply Voltage
0.8
RSD=LSD=0V
PVDD=5.0V
ISD(PVDD)=0.58µA
No Load
1.0
Shutdown Current (µA)
Shutdown Current (µA)
1.2
RSD=LSD=0V
VDD=3.3V
ISD(VDD)=0.65µA
No Load
0.6
0.4
0.2
0.8
0.6
0.4
0.2
0.0
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.5
2.0
2.5
Charge Pump Supply Voltage (Volt)
3.5
4.0
4.5
Power Dissipation vs. Output Power
Power Dissipation vs. Output Power
150
250
RL=16Ω
150
RL=32Ω
100
VDD=3.3V
PVDD=5.0V
THD+N<1%
50
RL=16Ω
125
Power Dissipation (mW)
200
Power Dissipation (mW)
3.0
Supply Voltage (Volt)
100
75
RL=32Ω
50
VDD=2.8V
PVDD=3.6V
THD+N<1%
25
0
0
0
50
100
150
200
0
250
20
40
60
80
100
120
Output Power (mW)
Output Power (mW)
Power Dissipation vs. Output Power
Power Dissipation vs. Output Power
100
70
Power Dissipation (mW)
Power Dissipation (mW)
60
80
RL=16Ω
60
40
RL=32Ω
VDD=1.8V
PVDD=3.0V
THD+N<1%
20
RL=16Ω
50
40
RL=32Ω
30
20
VDD=1.8V
PVDD=2.4V
THD+N<1%
10
0
0
0
10
20
30
40
50
0
60
20
30
40
Output Power (mW)
Output Power (mW)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
10
13
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APA2176/2176A
Typical Operating Characteristics (Cont.)
Output Power vs. Load Resistance
Output Power vs. Load Resistance
150
300
VDD=3.3V
PVDD=5.0V
fin=1kHz
Cin=1µF
BW<80kHz
Stereo, in Phase
200
150
THD+N=10%
100
VDD=2.8V
PVDD=3.6V
fin=1kHz
Cin=1µF
BW<80kHz
Stereo, in Phase
125
Output Power (mW)
THD+N=1%
50
100
75
THD+N=10%
50
THD+N=1%
25
0
0
10
100
10
1000
100
Load Resistance (Ω)
Output Power vs. Load Resistance
Output Power vs. Load Resistance
60
100
VDD=1.8V
PVDD=3.0V
fin=1kHz
Cin=1µF
BW<80kHz
Stereo, in Phase
60
40
THD+N=10%
THD+N=1%
20
VDD=1.8V
PVDD=2.4V
fin=1kHz
Cin=1µF
BW<80kHz
Stereo, in Phase
50
Output Power (mW)
80
Output Power (mW)
1000
Load Resistance (Ω)
40
30
THD+N=10%
20
THD+N=1%
10
0
0
10
100
10
1000
100
Load Resistance (Ω)
1000
Load Resistance (Ω)
Charge Pump Output Resistance
vs. Supply Voltage
GSM Power Supply Rejection vs.Frequency
10
+0
IPVDD=10mA
No Load
-50
8
-100
CF=CCO=1µF
7
Output Voltage (dBV)
Output Resistance (Ω)
9
CF=CCO=2.2µF
6
5
4
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Charge Pump Supply Voltage (Volt)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
-150
+0
Supply Voltage (dBV)
Output Power (mW)
250
-50
-100
-150
0
400
800
1.2k
1.6k
2k
Frequency (Hz)
14
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APA2176/2176A
Operating Waveforms
GSM Power Supply Rejection vs. Time
Output Transient at Turn on
VDD
VDD
1
1
PVDD
2
VOUT
VOUT
2
3
CH1: VDD, 500mV/Div, DC
VDD Offset = 3.3V
CH2: VOUT , 20mV/Div, DC
CH1: VDD, 2V/Div, DC
CH2: PVDD, 2V/Div, DC
CH3: VOUT, 20mV/Div, DC
TIME: 20ms/Div
TIME: 5ms/Div
Output Transient at Power off
Output Transient at Shutdown Active
VDD
1
VRSD
1
PVDD
2
VOUT
2
VOUT
3
CH1: VDD, 2V/Div, DC
CH2: PVDD, 2V/Div, DC
CH3: VOUT, 20mV/Div, DC
CH1: VRSD, 2V/Div, DC
CH2: VOUT, 20mV/Div, DC
TIME: 20ms/Div
TIME: 100ms/Div
Output Transient at Shutdown Release
Shutdown Release
VRSD
VRSD
1
1
VOUT
T
2
2
CH1: VRSD, 2V/Div, DC
CH2: VOUT, 1V/Div, DC
TIME: 200µs/Div
CH1: VRSD, 2V/Div, DC
CH2: VOUT, 20mV/Div, DC
TIME: 20ms/Div
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
VOUT
15
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APA2176/2176A
Pin Description
PIN
NO.
NAME
TQFN4x4-20B
TSSOP-16
TQFN3x3-16
(FOR APA2176A)
1
4
1
CP+
2
5
2
PGND
FUNCTION
Charge pump flying capacitor positive connection.
Charge pump ground.
3
6
3
CP-
Charge pump flying capacitor negative connection.
4, 6, 8, 12,
16, 20
1, 3
4, 13
NC
No Connection.
5
7
5
CVSS
7
8
6
VSS
Charge pump output.
Connect this pin to CVSS.
9
9
7
LOUT
Left channel output for headphone.
10
10
8
VDD
Supply voltage input pin.
11
11
9
ROUT
13
12
10
LIN
Left channel audio signal input pin.
14
13
11
RSD
Right channel shutdown mode control pin. A low-level voltage
applied on this pin shuts off the right channel headphone
driver.
15
14
12
RIN
Right channel audio signal input pin.
17
15
14
GND
Ground connection for circuitry.
18
16
15
LSD
Left channel shutdown mode control pin. A low-level voltage
applied on this pin shuts off the left channel headphone driver.
19
2
16
PVDD
Right channel output for headphone.
Charge pump power supply voltage input pin.
Block Diagram
RIN
ROUT
LIN
LOUT
PVDD
GND
CP+
RSD
LSD
Shutdown
circuit
GND
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
PGND
Charge
Pump
circuit
Power and
Depop circuit
VSS
VDD
16
CP-
CVSS
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APA2176/2176A
Typical Application Circuit
R-Ch
Input
CiR
1µF
CiL
1µF
L-CH
Input
RIN
RiR
14k
RfR
21k
RiL
14k
RfL
21k
Headphone Jack
LIN
GND
Shutdown
Control
ROUT
RSD
LSD
Shutdown
Circuit
GND PGND
VDD
Power and
Depop
Circuit
VDD
Cs
10µF
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
Charge
Pump
Circuit
LOUT
PVDD
PVDD
CP+
CCPB
10µF
CCPF
2.2µF
CP-
VSS
VSS
CVSS
CCPO
2.2µF
0.1µF
17
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APA2176/2176A
Function Description
voltage PVDD to provide maximum device performance.
VDD
By switching the both RSD and LSD pins to low level, the
amplifier enters a low-consumption current circum-
VOUT
VDD/2
stance, with charge pump disabled, and very small IDD for
the APA2176/2176A. The charge pump is enabled once
GND
either RSD or LSD pin is pulled to high. In normal
operating, the APA2176/2176A’s RSD and LSD pins
Conventional Headphone amplifier
should be pulled to high level to keep the IC out of the
shutdown mode. The RSD and LSD pins should be tied
VDD
to a definite voltage to avoid unwanted mode changing.
VOUT
GND
VSS
Cap-free Headphone amplifier
Figure 1. Cap-Free Operation
The APA2176/2176A is a stereo, fixed gain, cap-free headphone driver. The gain is set by internal resistors, input
resistors (R i), and feedback resistors (R f) with -1.5V/V
(See Typical Application Circuit).
The APA2176/2176A’s headphone drivers use a charge
pump to invert the positive power supply (PVDD) to negative power supply (CVSS), see figure1. The headphone
drivers operate at this bipolar power supply (VDD and VSS)
and the outputs reference refers to the ground. This feature eliminates the output capacitors which are used in
conventional single-ended headphone amplifiers. Compared with the single power supply amplifiers, the power
supply voltage is almost double.
Shutdown Function
In order to reduce power consumption, the APA2176/2176A
contain two shutdown signal input pins (LSD for left channel and RSD for right channel) to allow respective shutdown which turns off the bias current of the amplifier.
This shutdown feature turns the amplifier off when logic
low is placed on the RSD or LSD pin for the APA2176/
2176A. The trigger point between a logic high and logic
low level is typically 0.6PVDD and 0.3PVDD. It is highly recommended to switch between ground and the supply
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
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APA2176/2176A
Application Information
Charge Pump Flying Capacitor (CCPF)
The value of Ci is important to consider carefully because
The flying capacitor (CCPF) affects the load transient of the
charge pump. If the capacitor’s value is too small, and
it directly affects the low frequency performance of the
circuit. Consider the example where Ri is 14kΩ and the
specification that calls for a flat bass response down to
10Hz. The equation is reconfigured as below:
1
Ci =
(2)
2πRifC
then this increases charge pump’s output resistance and
degrades the performance of headphone amplifier.
Increasing the flying capacitor’s value improves the load
transient of charge pump. It is recommended to use the
low ESR ceramic capacitors (X7R type is recommended)
above 2.2µF.
When the input resistance variation is considered, the Ci
is 1µF. Therefore, a value in the range of 1µF to 2.2µF
Charge Pump Output Capacitor (CCPO)
would be chosen. A further consideration for this capacitor is the leakage path from the input source through the
The charge pump needs an output capacitor(CCPO) to filter the negative output current pulse flowing into CVSS
input network (Ri + Rf, Ci) to the load.
This leakage current creates a DC offset voltage at the
pin as well as reduces the output voltage ripple (CVSS).
The capacitor also sucks in surge current flowing from
input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-
the VSS pin, the negative power input pin for the amplifiers.
The output ripple is determined by the capacitance, ESR,
leakage tantalum or ceramic capacitor is the best choice.
When polarized capacitors are used, the negative side of
and current ripple of the output capacitor. Increasing the
value of output capacitor and decreasing the ESR can
the capacitor should face the amplifiers’ inputs in most
applications because the DC level of the amplifiers’ in-
reduce the voltage ripple. Using a low-ESR ceramic capacitor greater than 2.2µF is recommended. For reduc-
puts are held at 0V. Please note that it is important to
confirm the capacitor polarity in the application.
ing the parasitic inductance and improving the noise
Power Supply Decoupling (Cs)
decoupling, place the capacitor near the CVSS and the
PGND pins as close as possible.
The APA2176/2176A is a high-performance CMOS audio
Charge Pump Bypass Capacitor (CCPB)
amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD+N)
The bypass capacitor(CCPB) connected with PVDD pin supplies the charge pump with surge current as well as re-
as low as possible. Power supply decoupling also prevents the oscillations caused by long lead length between
duces the voltage ripple on PVDD pin. Using a low-ESR
ceramic capacitor 10µF(typical) is recommended. For
the amplifier and the speaker.
The optimum decoupling is achieved by using two differ-
reducing the parasitic inductance and improving the noise
decoupling, place the capacitor near the PVDD and the
ent types of capacitor that targets on different types of
noise on the power supply leads. For higher frequency
PGND pins as close as possible.
transients, spikes, or digital hash on the line, a good low
equivalent-series- resistance (ESR) ceramic capacitor,
Input Capacitor (Ci)
typically 0.1µF, is placed as close as possible to the device VDD lead for the best performance. For filtering lower
In the typical application, an input capacitor (Ci) is required
to allow the amplifier to bias the input signal to the proper
frequency noise signals, a large aluminum electrolytic
capacitor of 10µF or greater placed near the audio power
DC level for optimum operation. In this case, Ci and the
input impedance Ri from a high-pass filter with the cutoff
amplifier is recommended.
frequency are determined in the following equation:
fC(highpass) =
1
2πRiCi
Thermal Consideration
(1)
Linear power amplifiers dissipate a significant amount
of heat in the package in normal operating condition. The
Copyright  ANPEC Electronics Corp.
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APA2176/2176A
Application Information (Cont.)
Thermal Consideration (Cont.)
first consideration to calculate maximum ambient temperatures is the numbers from the Power Dissipation vs.
ThermalVia
Diameter
0.3mm X 5
0.8mm
Output Power graphs are per channel values, therefore,
the dissipation of the IC heat needs to be doubled for
0.35mm
pation (PD), and the maximum ambient temperature can
be calculated with the following equation. The maximum
4.9mm
2.2mm
two-channel operation. Given θJA, the maximum allowable junction temperature (TJMax), the total internal dissi0.5mm
recommended junction temperature for the APA2176/
2176A is 150°C. The internal dissipation figures are taken
2.2mm
Ground
Plane for
ThermalPAD
from the Power Dissipation vs. Output Power graphs.
The APA2176/2176A is designed with a thermal shutdown
protection that turns the device off when the junction temperature surpasses 150°C to prevent damaging the IC.
Figure 2. TQFN4x4-20B Layout Recommendation
Layout Consideration
1. All components should be placed close to the APA2176/
2176A. For example, the input capacitor (Ci) should be
Thermal Via
Diameter
0.3mm X 5
close to APA2176/2176A’s input pins to avoid causing
noise coupling to APA2176/2176A’s high impedance
1mm
0.3mm
power rail noise.
2. The output traces should be short, wide (>50mil), and
4.0mm
1.55mm
inputs; the decoupling capacitor (CS) should be placed
by the APA2176/2176A’s power pin to decouple the
0.5mm
symmetric.
3. The input trace should be short and symmetric.
1.55mm
Ground
Plane for
Thermal
PAD
4. The power trace width should be greater than 50mil.
5. The TQFN Thermal PAD should be soldered on PCB,
and the ground plane needs soldered mask (to avoid
short circuit) except the Thermal PAD area.
Figure 3. TQFN3x3-16 Layout Recommendation
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
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APA2176/2176A
Package Information
TQFN4x4-20B
D
b
E
A
Pin 1
A1
D2
A3
L K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
TQFN4x4-20B
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
0.012
A3
0.20 REF
0.008 REF
b
0.18
0.30
0.008
D
3.90
4.10
0.154
0.161
D2
2.00
2.70
0.079
0.106
E
3.90
4.10
0.154
0.161
E2
2.00
2.70
0.079
0.106
0.45
0.014
e
0.50 BSC
L
0.35
K
0.20
0.020 BSC
0.018
0.008
Note : 1. Followed from JEDEC MO-220 VGGD-5.
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
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APA2176/2176A
Package Information
TSSOP-16
D
e
E
E1
SEE VIEW A
C
0.25
A
A2
b
GAUGE PLANE
A1
SEATING PLANE
VIEW A
S
Y
M
B
O
L
L
TSSOP-16
MILLIMETERS
MIN.
INCHES
MIN.
MAX.
A
MAX.
0.047
1.20
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.031
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.008
D
4.90
5.10
0.193
0.201
E
6.20
6.60
0.244
0.260
E1
4.30
4.50
0.169
0.177
e
L
0
0.65 BSC
0.026 BSC
0.45
0.75
0.018
0o
8o
0o
0.030
8o
Note : 1. Follow from JEDEC MO-153 AB.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side.
3. Dimension "E1" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
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APA2176/2176A
Package Information
TQFN3x3-16
A
b
E
D
Pin 1
D2
A1
A3
k
E2
Pin 1
Corner
e
S
Y
M
B
O
L
TQFN3x3-16
INCHES
MILLIMETERS
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
0.012
A3
0.20 REF
0.008 REF
b
0.18
0.30
0.007
D
2.90
3.10
0.114
0.122
D2
1.50
1.80
0.059
0.071
E
2.90
3.10
0.114
0.122
E2
1.50
1.80
0.059
0.071
0.50
0.012
e
0.50 BSC
L
0.30
K
0.20
0.020 BSC
0.020
0.008
Note : Follow JEDEC MO-220 WEED-4.
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APA2176/2176A
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN4x4-20B
Application
TSSOP-16
Application
TQFN3x3-16
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±
0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
4.30±0.20
4.30±
0.20
1.30±0.20
4.0±0.10
8.0±0.10
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±
0.10
5.50±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.00±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.90±0.20
5.40±
0.20
1.60±0.20
4.00±0.10
8.00±0.10
A
H
T1
C
d
D
W
E1
F
330±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±
0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±
0.20
1.30±0.20
4.0±0.10
8.0±0.10
(mm)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
24
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APA2176/2176A
Devices Per Unit
Package Type
Unit
Quantity
TQFN4x4-20B
Tape & Reel
3000
TSSOP-16
Tape & Reel
2500
TQFN3x3-16
Tape & Reel
3000
Taping Direction Information
TQFN4x4-20B
USER DIRECTION OF FEED
TSSOP-16
USER DIRECTION OF FEED
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
25
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APA2176/2176A
Taping Direction Information (Cont.)
TQFN3x3-16
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
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APA2176/2176A
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3
Package
Thickness
<2.5 mm
Volume mm
<350
235 °C
Volume mm
≥350
220 °C
≥2.5 mm
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
27
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APA2176/2176A
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Jan., 2013
28
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