ANPEC 2011A

APA2011/2011A
2.8W Mono Class D Audio Power Amplifier with AGC
Features
•
•
•
General Description
Operating Voltage: 2.4V-5.5V
High Efficiency up to 90%
The APA2011/2011A is a mono, filter-free Class-D audio
amplifier available in WLCSP1.5x1.5-9 or TDFN3x3-8
Supply Current
–IDD=3mA at VDD=5V
package.
The default gains without the external input resistor is
•
–IDD=2.5mA at VDD=3.6V
Low Shutdown Current
27dB. Besides, the gain can be low down by external
input resistance. APA2011 provides an Dynamic-Range-
•
– IDD=1µA at VDD=5V
Output Power
Control (DRC) function, and this function can low down
the dynamic range for large input signal. APA2011 can
at 1% THD+N
– 1.3W, at VDD=5V, RL=8Ω
provide maximun 15dB gain control. APA2011A can provide maximum 15dB gain decrease for non-clipping
– 0.6W, at VDD=3.6V, RL=8Ω
– 2.0W, at VDD=5V, RL=4Ω
function, and this function can avoid output signal clipping.
High PSRR and differential architecture provide increased
– 1.0W, at VDD=3.6V, RL=4Ω
at 10% THD+N
immunity to noise and RF rectification. In addition to these
features, a fast start-up time and small package size
– 1.6W, at VDD=5V, RL=8Ω
– 0.8W, at VDD=3.6V, RL=8Ω
make the APA2011/2011A an ideal choice for portable
devices.
– 2.8W, at VDD=5V, RL=4Ω (WLCSP-9)
– 2.4W, at VDD=5V, RL=4Ω
The APA2011/2011A is capable of driving 1.6W at 5V or
0.8W at 3.6V into 8Ω. It is also capable of driving 4Ω. The
•
– 1.2W, at VDD=3.6V, RL=4Ω
APA2011 Dynamic Range Control (DRC) Provide
APA2011/2011A is designed with a Class-D architecture
and operating with highly efficiency compared with Class-
•
Maximum 15dB Control (2:1 Compression Ratio)
APA2011A Non-Clip Function can Provide Maxi-
AB amplifier. It’s suitable for power sensitive application,
such as battery-powered devices. The filter-free architec-
mum 15dB Control (Gain Decreasing)
Less External Components Required
ture eliminates the output filter, reduces the external component count, board area, and system costs, and simpli-
•
•
•
•
•
Fast Start-up Time (4ms)
High PSRR: 70dB at 217Hz
fies the design.
Moreover, the APA2011/2011A provides thermal and short
Thermal and Over-Current Protections
Space Saving Packages
circuit protection.
•
WLCSP1.5x1.5-9 Bump, TDFN3x3-8
Lead Free and Green Devices Available
Simplified Application Circuit
(RoHS Compliant)
INP
Audio Input
Signals
Applications
•
•
•
•
OUTP
APA2011/2011A
INN
Audio
Speaker
OUTN
Mobil Phones
Handset
PDAs
Portable Multimedia Device
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
1
www.anpec.com.tw
APA2011/2011A
Ordering and Marking Information
Package Code
HA : WLCSP1.5x1.5-9 QB : TDFN3x3-8
Operating Ambient Temperature Range
I : - 40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APA2011/2011A
Assembly Material
Handling Code
Temperature Range
Package Code
HA :
A11
X
X - Date Code
APA2011A HA :
A11A
X
X - Date Code
APA2011
QB :
APA
2011
XXXXX
XXXXX - Date Code
APA2011A QB :
APA
2011A
XXXXX
XXXXX - Date Code
APA2011
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
OUTN
(A3)
PGND
(B3)
OUTP
(C3)
GND
(A2)
VDD
(B2)
SD
(C2)
INP
(A1)
DR
(B1)
INN
(C1)
A11
A11A
X
X
Marking
DR 2
7 GND
INP 3
6 VDD
INN 4
5 OUTP
Date Code
Absolute Maximum Ratings
VPGND_GND
8 OUTN
Marking
PIN A1
WLCSP1.5x1.5-9
Top View
Symbol
SD 1
TDFN3x3-8
Top View
(Note 1)
Parameter
Rating
PGND to GND
-0.3 to +0.3
VDD
Supply Voltage (VDD to PGND, VDD to GND)
VIN
Input Voltage (INN, INP to GND)
-0.3 to VDD+0.3
VSD, VDR
Input Voltage (SD, DR to GND)
-0.3 to VDD+0.3
TJ
Maximum Junction Temperature
TSTG
-0.3 to 6
150
Storage Temperature Range
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
Unit
o
-65 to +150
2
V
C
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APA2011/2011A
Absolute Maximum Ratings (Cont.)
Symbol
TSDR
PD
(Note 1)
Parameter
Rating
Maximum Lead Soldering Temperature, 10 Seconds
Unit
o
260
Power Dissipation
C
Internally Limited
W
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under
"recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Thermal Resistance -Junction to Ambient
Typical Value
Unit
(Note 2)
WLCSP1.5x1.5-9
TDFN3x3-8
165
50
TDFN3x3-8
10
ο
C/W
Thermal Resistance -Junction to Case (Note 3)
ο
C/W
Note 2: Please refer to “ Layout Recommendation”, the Thermal Pad on the bottom of the IC should soldered directly to the PCB’s
Thermal Pad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz
copper thickness.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TDFN3x3-8 package.
Recommended Operating Conditions
Symbol
Range
Parameter
Min.
Max.
VDD
Supply Voltage
2.4
5.5
VIH
High Level Threshold Voltage
SD
1
-
VIL
Low Level Threshold Voltage
SD
-
0.4
VIC
Common Mode Input Voltage
-
VDD-1
TA
Ambient Temperature Range
-40
85
TJ
Junction Temperature Range
-40
125
RL
Speaker Resistance
2.8
-
Unit
V
ο
C
Ω
Electrical Characteristics
VDD=5V, GND=0V, AV=15dB, TA=25oC (unless otherwise noted)
Symbol
Parameter
Test Conditions
APA2011/2011A
Min.
Typ.
Max.
Unit
IDD
Supply Current
-
3
6
ISD
Shutdown Current
SD = 0V
-
1
5
Input Current
SD
-
0.1
1
400
500
600
kHz
-
4
8
ms
23.75
25
26.25
9.5
10
10.5
-
780
-
II
FOSC
twake-up
Ri
RDR
RDS(ON)
Oscillator Frequency
Recovery Time from Shutdown
Input Resistor
INN, INP
DR Pin Pull-high Resistor
Static Drain-Source On-State
Resistance
(PMOSFET+NMOSFET)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
VDD=5V, IL=0.8A
3
WLCSP1.5x1.5-9
mA
µA
kΩ
mΩ
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APA2011/2011A
Electrical Characteristics (Cont.)
VDD=5V, GND=0V, AV=15dB, TA= 25oC (unless otherwise noted)
Symbol
RDS(ON)
η
Parameter
Static Drain-Source On-State
Resistance
(PMOSFET+NMOSFET)
Efficiency
Test Conditions
APA2011/2011A
Min.
Typ.
Max.
VDD=3.6V,
IL=0.6A
WLCSP1.5x1.5-9
-
900
-
VDD=2.4V,
IL=0.4A
WLCSP1.5x1.5-9
-
1000
-
PO=1.2W,
RL=8Ω+33µH
WLCSP1.5x1.5-9
-
90
-
PO=2W,
RL=4Ω+33µH
WLCSP1.5x1.5-9
-
82
-
RL=3Ω
-
2.45
-
RL=4Ω,
WLCSP1.5x1.5-9
-
2.2
-
RL=4Ω
-
2.0
-
RL=8Ω
1
1.3
-
RL=3Ω
-
3.0
-
RL=4Ω,
WLCSP1.5x1.5-9
-
2.8
-
RL=4Ω
-
2.4
-
RL=8Ω
-
1.6
-
RL=4Ω
PO=1.4W
-
0.05
0.1
RL=8Ω
PO=0.9W
-
0.04
0.1
RL=8Ω
PO=1.5W, VDR=VDD
-
3
5
Unit
mΩ
%
VDD=5V
THD+N=1%,
fin=1kHz
PO
Output Power
THD+N=10%,
fin=1kHz
THD+N
Total Harmonic Distortion Plus
Noise
fin=1kHz
W
%
VOS
Output Offset Voltage
RL=8Ω
-
-
20
mV
Vn
Noise Output Voltage
With A-weighting Filter, RL=8Ω
-
100
200
µVrms
S/N
Signal to Noise Ratio
With A-weighting Filter, PO=0.9W,
RL=8Ω
82
89
-
PSRR
Power Supply Rejection Ratio
RL=8Ω, fin=217Hz,Vrr=0.5Vpp
-
-70
-60
CMRR
Common Mode Rejection Ratio
fin=1kHz, RL=8Ω, Vin=0.1Vpp
-
-60
-50
Shutdown Attenuation
fin=1kHz, RL=8Ω, Vin=1Vpp
-
-100
-90
RL=4Ω
-
1.0
-
RL=8Ω
-
0.6
-
RL=4Ω
-
1.2
-
RL=8Ω
-
0.8
-
RL=4Ω
PO=0.7W
-
0.07
0.15
RL=8Ω
PO=0.4W
-
0.05
0.1
Attshutdown
dB
VDD=3.6V
THD+N=1%,
fin=1kHz
PO
Output Power
THD+N=10%,
fin=1kHz
W
Total Harmonic Distortion Plus
Noise
fin=1kHz
VOS
Output Offset Voltage
RL=8Ω
-
-
20
mV
Vn
Noise Output Voltage
With A-weighting Filter, RL=8Ω
-
100
200
µVrms
THD+N
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
4
%
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APA2011/2011A
Electrical Characteristics (Cont.)
VDD=5V, GND=0V, AV=15dB, TA= 25oC (unless otherwise noted)
Symbol
Parameter
Test Conditions
APA2011/2011A
Min.
Typ.
Max.
79
85
-
-
-70
-60
Unit
VDD=3.6V (CONT.)
Signal to Noise Ratio
With A-weighting Filter, PO=0.4W,
RL=8Ω
PSRR
Power Supply Rejection Ratio
RL=8Ω, fin=217Hz,Vrr=0.2Vpp
CMRR
Common Mode Rejection Ratio
fin=1kHz, RL=8Ω, Vin=0.1Vpp
-
-60
-50
Shutdown Attenuation
fin=1kHz, RL=8Ω, Vin=1Vpp
-
-100
-90
S/N
Attshutdown
dB
VDD=2.4V
THD+N=1%,
fin=1kHz
PO
Output Power
THD+N=10%,
fin=1kHz
RL=4Ω
-
0.45
-
RL=8Ω
-
0.3
-
RL=4Ω
-
0.55
-
RL=8Ω
-
0.35
-
RL=4Ω
PO=0.32W
-
0.2
0.5
RL=8Ω
PO=0.2W
-
0.1
0.3
W
Total Harmonic Distortion Plus
Noise
fin=1kHz
Vos
Output Offset Voltage
RL=8Ω
-
-
20
mV
Vn
Noise Output Voltage
With A-weighting Filter, RL=8Ω
-
110
220
µVrms
S/N
Signal to Noise Ratio
With A-weighting Filter, PO=0.2W,
RL=8Ω
75
81
-
PSRR
Power Supply Rejection Ratio
RL=8Ω, fin=217Hz,Vrr=0.1Vpp
-
-65
-60
CMRR
Common Mode Rejection Ratio
fin=1kHz, RL=8Ω, Vin=0.1Vpp
-
-60
-50
Shutdown Attenuation
fin=1kHz, RL=8Ω, Vin=1Vpp
-
-100
-90
THD+N
Attshutdown
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
5
%
dB
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APA2011/2011A
Typical Operating Characteristics
Efficiency vs. Output Power (4Ω)
Efficiency vs. Output Power (8Ω)
90
90
VDD=5V
80
VDD=5V
70
70
VDD=2.4V
60
Efficiency (%)
Efficiency (%)
VDD=3.6V
80
VDD=3.6V
50
40
RL=8Ω+33µH
fin=1kHz
Rin=75kΩ
AV=15dB
AUX-0025
AES-17(20kHz)
30
20
10
0
0
VDD=2.4V
60
50
40
RL=4Ω+33µH
fin=1kHz
Rin=75kΩ
AV=15dB
AUX-0025
AES-17(20kHz)
30
20
10
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0
0.5
1.0
Output Power vs. Load Resistance
THD+N=10%
fin=1kHz
Rin=75kΩ
AV=15dB
AUX-0025
AES-17(20kHz)
WLCSP1.5x1.5-9
2.0
1.5
3.0
2.0
1.0
VDD=3.6V
1.5
VDD=5V
1.0
0.5
TDFN3x3-8
8
0
12
16
20
24
28
32
VDD=3.6V
VDD=2.4V
VDD=2.4V
4
THD+N=1%
fin=1kHz
Rin=75kΩ
AV=15dB
AUX-0025
AES-17(20kHz)
WLCSP1.5x1.5-9
VDD=5V
0.5
TDFN3x3-8
4
Load Resistance (Ω)
8
12
16
20
24
28
32
Load Resistance (Ω)
THD+N vs. Output Power
THD+N vs. Output Power
10
10
VDD=5.5V
VDD=5V
VDD=4.2V
VDD=3.6V
VDD=2.4V
fin=1kHz
Rin=75kΩ
RL=8Ω
AV=15dB
AUX-0025
AES-17(20kHz)
TDFN3x3-8
0.1
0
1
2
fin=1kHz
Rin=75kΩ
RL=4Ω
AV=15dB
AUX-0025
AES-17(20kHz)
TDFN3x3-8
0.1
0.01
0
2.5
Output Power (W)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
VDD=5.5V
VDD=5V
VDD=4.2V
VDD=3.6V
VDD=2.4V
1
THD+N (%)
1
THD+N (%)
2.5
Output Power vs. Load Resistance
Output Power (W)
Output Power (W)
2.5
0.01
2.0
2.5
3.0
0
1.5
Output Power (W)
Output Power (W)
1
2
3
4
Output Power (W)
6
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APA2011/2011A
Typical Operating Characteristics (Cont.)
THD+N vs. Output Power
THD+N vs. Output Power
10
10
THD+N (%)
1
fin=1kHz
Rin=75kΩ
RL=8Ω
AV=15dB
AUX-0025
AES-17(20kHz)
WLCSP1.5x1.5-9
0.1
0.01
0
1
2
Output Power (W)
VDD=5.5V
VDD=5V
VDD=4.2V
VDD=3.6V
VDD=2.4V
1
THD+N (%)
VDD=5.5V
VDD=5V
VDD=4.2V
VDD=3.6V
VDD=2.4V
fin=1kHz
Rin=75kΩ
RL=4Ω
AV=15dB
AUX-0025
AES-17(20kHz)
WLCSP1.5x1.5-9
0.1
0.01
0
2.8
1
THD+N vs. Output Power
10
V DD=5V
V DD=4.2V
1
THD+N (%)
THD+N (%)
V DD=3.6V
V DD=2.4V
fin =1kHz
Rin =75kΩ
RL =3Ω
A V=15dB
AUX-0025
AES-17(20kHz)
WLCSP1.5x1.5-9
0.1
0 .01
0
1
2
3
4
R
VDD=2.4V
Ci=0.1µF
Rin=75kΩ
RL=8Ω
AV=15dB
AUX-0025
AES-17(20kHz)
PO=0.1W
0.01
20
5
THD+N vs. Frequency
100
1k
Frequency (Hz)
10k 20k
THD+N vs. Frequency
10
10
VDD=3.6V
Ci=0.1µF
Rin=75kΩ
RL=8Ω
AV=15dB
AUX-0025
AES-17(20kHz)
1
PO=0.5W
THD+N (%)
THD+N (%)
PO=0.2W
0.1
Output Power (W)
1
4 4.5
THD+N vs. Frequency
10
1
2
3
Output Power (W)
0.1
VDD=5V
Ci=0.1µF
Rin=75kΩ
RL=8Ω
AV=15dB
AUX-0025
AES-17(20kHz)
0.1
PO=1W
PO=0.3W
0.01 PO=0.1W
0.005
20
100
1k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
PO=0.5W
0.01
0.005
20
10k 20k
7
PO=0.3W
100
1k
Frequency (Hz)
10k 20k
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APA2011/2011A
Typical Operating Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Frequency
10
0.1
PO=0.3W
R
PO=0.2W
R
VDD=3.6V
Ci=0.1µF
Rin=75kΩ
RL=4Ω
AV=15dB
AUX-0025
AES-17(20kHz)
1
THD+N (%)
1
THD+N (%)
10
VDD=2.4V
Ci=0.1µF
Rin=75kΩ
RL=4Ω
AV=15dB
AUX-0025
AES-17(20kHz)
PO=0.8W
0.1
PO=0.4W
0.01
0.005
20
100
1k
Frequency (Hz)
PO=0.2W
0.01
0.005
20
10k 20k
100
THD+N vs. Frequency
10
Amplitude
+120
+14
+40
+10
Phase
+4
PO=0.9W
PO=0.5W
+2
-0
10k 20k
20
100
CMRR vs. Frequency
-30
-40
+0
VDD=5V
Ci=0.1µF
Rin=75kΩ
RL=8Ω
VO=1Vrms
AV=15dB
AUX-0025
AES-17(20kHz)
Power Supply Rejection Ratio (dB)
Common Mode Rejection Ratio (dB)
-20
-50
-60
-70
-80
20
100
1k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
-40
-80
-120
1k
10k
Frequency (Hz)
-160
100k
PSRR vs. Frequency
+0
-10
+0
VDD=5V
Ci=0.1µF
Rin=75kΩ
RL=8Ω
PO=0.13W
AV=15dB
AUX-0025
AES-17(20kHz)
+8
+6
1k
Frequency (Hz)
+80
+12
PO=1.7W
0.1
100
+180
+160
+16
Gain (dB)
THD+N (%)
Frequency Response
Phase (Deg)
VDD=5V
Ci=0.1µF
Rin=75kΩ
RL=4Ω
AV=15dB
AUX-0025
AES-17(20kHz)
0.01
0.005
20
10k 20k
+18
R
1
1k
Frequency (Hz)
-10
-20
-30
-40
-50
-60
-70
-80
10k 20k
8
VDD=5V
Vrr=0.5Vpp
Ci=0.1µF
Rin=75kΩ
RL=8Ω
AV=15dB
Inputs Short
AUX-0025
AES-17(20kHz)
20
100
1k
Frequency (Hz)
10k 20k
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APA2011/2011A
Typical Operating Characteristics (Cont.)
Noise vs. Frequency
Supply Current vs. Output Power
0.40
VDD=5V
Ci=0.1µF
Rin=75kΩ
RL=8Ω
AV=15dB
AUX-0025
AES-17(20kHz)
A-weighting
VDD=5V
0.35
Supply Current (A)
Output Noise Voltage (µV)
1m
100µ
0.30
VDD=3.6V
0.25
0.20
VDD=2.4V
VDD=5V
Ci=1µF
Rin=75kΩ
RL=8Ω
AV=15dB
AUX-0025
AES-17(20kHz)
0.15
0.10
0.05
10µ
20
100
1k
Frequency (Hz)
0
10k 20k
0.7
VDD=5V
0.4
0
0
0.5
VDD=5V
Ci=1µF
Rin=75kΩ
RL=4Ω
AV=15dB
AUX-0025
AES-17(20kHz)
1.0
1.5
Output Power (W)
2.0
APA2011 Dynamic Range Control
Function_WLCSP
1.8
2.5
2
1
+16
+15
VDD=5V
+14
VDR=4.5V
Ci=0.1µF
+13
Rin=75kΩ
+12
RL=4Ω
+11
AV=15dB
+10
+9
+8
+7
+6
+5
AUX-0025
+4 AES-17(20kHz)
+3 TDFN3x3-8
+2
+1
-0
0.1
1
2
Input Voltage (Vrms)
0
3
9
+16
VDD=5V
+15
VDR=4.23V
+14
Ci=0.1µF
+13
Rin=75kΩ
+12
RL=4Ω
+11
AV=15dB
+10
+9
+8
+7
+6
+5 AUX-0025
+4 AES-17(20kHz)
+3 TDFN3x3-8
+2
+1
-0
1
0.1
Input Voltage (Vrms)
2.4
2
1
0
3
1.6
1
Output Power (W)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
1.5
APA2011 Dynamic Range Control
Function_TDFN
Output Power (W)
+16
VDD=5V
+15
VDR=4.5V
+14
Ci=0.1µF
+13
Rin=75kΩ
+12
RL=4Ω
+11
AV=15dB
+10
+9
+8
+7
+6
+5 AUX-0025
+4 AES-17(20kHz)
+3 WLCSP1.5x1.5-9
+2
+1
-0
0.1
1
2
Input Voltage (Vrms)
2.5
Gain (dB)
0.2
0.1
Gain (dB)
Gain (dB)
VDD=3.6V
VDD=2.4V
0.6
0.9
1.2
Output Power (W)
Output Power (W)
Supply Current (A)
0.6
0.3
0.3
APA2011 Dynamic Range Control
Function_TDFN
Supply Current vs. Output Power
0.5
0
0
2 2.5
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APA2011/2011A
1.6
1
AUX-0025
AES-17(20kHz)
WLCSP1.5x1.5-9
0.1
1
2
Gain (dB)
VDD=5V
VDR=4.23V
Ci=0.1µF
Rin=75kΩ
RL=4Ω
AV=15dB
APA2011 Dynamic Range Control
Function_TDFN
0
1.6
AUX-0025
AES-17(20kHz)
WLCSP1.5x1.5-9
Gain (dB)
1
1
0
2
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
-0
VDD=5V
VDR=4.5V
Ci=0.1µF
Rin=75kΩ
RL=4Ω
AV=15dB
1
AUX-0025
AES-17(20kHz)
TDFN-8
0.1
2
Gain (dB)
1
Output Power (W)
Gain (dB)
3
0
AUX-0025
AES-17(20kHz)
WLCSP-9
2
3
0
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
-0
1.6
VDD=5V
VDR=4.23V
Ci=0.1µF
Rin=75kΩ
RL=4Ω
AV=15dB
1
Output Power (W)
VDD=5V
VDR=4.5V
Ci=0.1µF
Rin=75kΩ
RL=4Ω
AV=15dB
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
1
APA2011A Non-Clipping Function_TDFN
2.4
1
Input Voltage (Vrms)
2
Input Voltage (Vrms)
APA2011A Non-Clipping Function_WLCSP
0.1
0
2
2.4
Input Voltage (Vrms)
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
-0
1
APA2011A Non-Clipping Function_TDFN
VDD=5V
VDR=4V
Ci=0.1µF
Rin=75kΩ
RL=4Ω
AV=15dB
0.1
1.2
Output Power (W)
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
-0
APA2011 Dynamic Range Control
Function_WLCSP
Output Power (W)
Gain (dB)
Input Voltage (Vrms)
+16
VDD=5V
+15
VDR=4V
+14
Ci=0.1µF
+13
Rin=75kΩ
+12
RL=4Ω
+11
AV=15dB
+10
+9
+8
+7
+6
+5 AUX-0025
+4 AES-17(20kHz)
+3 TDFN3x3-8
+2
+1
-0
0.1
1
Input Voltage (Vrms)
Output Power (W)
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
-0
APA2011 Dynamic Range Control
Function_WLCSP
Output Power (W)
Gain (dB)
Typical Operating Characteristics (Cont.)
AUX-0025
AES-17(20kHz)
TDFN-8
0.1
1
2
0
Input Voltage (Vrms)
10
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APA2011/2011A
Typical Operating Characteristics (Cont.)
APA2011A Non-Clipping Function_TDFN
1.6
Gain (dB)
1
AUX-0025
AES-17(20kHz)
WLCSP-9
0.1
1
2
0
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
-0
1.2
VDD=5V
VDR=4V
Ci=0.1µF
Rin=75kΩ
RL=4Ω
AV=15dB
AUX-0025
AES-17(20kHz)
TDFN-8
0.1
Input Voltage (Vrms)
0
5
No load
VDD=5V
VDR=4V
Ci=0.1µF
Rin=75kΩ
RL=4Ω
AV=15dB
1
Supply Current (mA)
4
AUX-0025
AES-17(20kHz)
WLCSP-9
0.01
3
2
1
1
2
0
0
0
1
Input Voltage (Vrms)
2
3
4
Supply Voltage (V)
5 5.5
VDR vs. Output Power (8Ω)
Shutdown Current vs. Supply Voltage
1.2
2
No load
Typ
1.0
Max
Output Power (W)
Shutdown Current (µA)
2
Supply Current vs. Supply Voltage
1.2
Output Power (W)
Gain (dB)
1
Input Voltage (Vrms)
APA2011A Non-Clipping Function_WLCSP
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
-0
1
Output Power (W)
VDD=5V
VDR=4.23V
Ci=0.1µF
Rin=75kΩ
RL=4Ω
AV=15dB
Output Power (W)
Gain (dB)
APA2011A Non-Clipping Function_WLCSP
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
-0
0.8
0.6
0.4
Min
VDD=5V
1
0.2
0
0
1
2
3
4
Supply Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
0
3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0
VDR (V)
5 5.5
11
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APA2011/2011A
Typical Operating Characteristics (Cont.)
VDR vs. Output Power (4Ω)
Output Power (W)
4
Typ
Max
Min
3
VDD=5V
2
1
0
3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0
VDR(V)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
12
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APA2011/2011A
Operating Waveforms
Power On
Power Off
VDD
VDD
1
1
M1
M1
VOUT
VOUT
VOUTP & VOUTN
VOUTP & VOUTN
2&3
2&3
CH1: VDD, 5V/Div, DC
CH2: VOUTP, 1V/Div, DC
CH3: VOUTN, 1V/Div, DC
CHM1: VOUT(CH2-CH3), 100mV/Div, DC
TIME: 40ms/Div
CH1: VDD, 5V/Div, DC
CH2: VOUTP, 1V/Div, DC
CH3: VOUTN, 1V/Div, DC
CHM1: VOUT(CH2-CH3), 100mV/Div, DC
TIME: 2ms/Div
Shutdown Release
Shutdown
VDD
VDD
1
1
M1
M1
VOUT
VOUT
VOUTP & VOUTN
VOUTP & VOUTN
2&3
2&3
CH1: VSD, 5V/Div, DC
CH2: VOUTP, 1V/Div, DC
CH3: VOUTN, 1V/Div, DC
CHM1: VOUT(CH2-CH3), 100mV/Div, DC
TIME: 20ms/Div
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
CH1: VSD, 5V/Div, DC
CH2: VOUTP, 1V/Div, DC
CH3: VOUTN, 1V/Div, DC
CHM1: VOUT(CH2-CH3), 100mV/Div, DC
TIME: 1ms/Div
13
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APA2011/2011A
Pin Description
PIN
NO.
NAME
I/O/P
FUNCTION
WLCSP1.5x1.5-9
TDFN3x3-8
A1
3
INP
I
Positive Input of Power Amplifier.
A2
7
GND
P
Ground Connection for Circuitry.
A3
8
OUTN
O
Negative Output of Power Amplifier.
Setting the Maximum Output Power; Disable the DRC/Non-clipping,
when VDR<0.2VDD, and if the 0.2VDD<VDR<0.55VDD, the VDR is set to
0.55VDD by internal, this is maximum power limit (Minimum the
output power).
B1
2
DR
I
VDR =
R1
× VDD
R1 + 10kΩ
* PO =
2( VDR − 0.5 VDD )2
R SPK
RSPK: Speaker Resistor
Note: The setting value has 15% variation by IC process and this equation only for
WLCSP1.5x1.5-9 package, the TDFN3x3-8 package's output power will less than the
calculation.
B2
6
VDD
P
Supply Voltage Input Pin.
B3
-
PGND
P
Ground Connection for Power Stage
C1
4
INN
I
Negative Input of Power Amplifier.
C2
1
SD
I
Shutdown Mode Control Input, Place entire IC in shutdown mode
when held low.
C3
5
OUTP
O
Positive Output of Power Amplifier.
Block Diagram
AV=27dB(22.4V/V)
AV=15dB (5.6V/V)
100kΩ
Gate
Drive
25kΩ
INN
OUTN
VDD
AGC
INP
25kΩ
Gate
Drive
100kΩ
GND
DR
OUTP
PGND
AGC
Setting
VDD
OSC
VDD
SD
Shutdown
Control
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
Bias &
Reference
14
Protection
Function
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APA2011/2011A
Typical Application Circuit
Differential input mode (TDFN3x3-8)
VDD
CS2
0.1µF
Shutdown
Control
*R1
Ci1
Differential
Ci2
Signals
SD
1
DR
2
INP
3
INN
4
0.1µF
0.1µF
CS1
10µF
8
7
APA2011/
2011A
OUTN
GND
VDD
6
VDD
5
OUTP
4Ω
*R1: Setting the Maximum Output Power
VDR =
R1
2(VDR − 0.5VDD )2
× VDD * PO =
R1 + 10k Ω
R SPK
RSPK: Speaker Resistor
Note : *The setting value has 15% variation by IC process and this equation only for WLCSP1.5x1.5-9 package, the TDFN3x3-8
package’s output power will less than the calculation.
Single-Ended input mode (TDFN3x3-8) and AV=15dB
VDD
CS2
0.1µF
Shutdown
Control
CS1
10µF
8 OUTN
SD 1
*R1
DR 2
Ri1
Single-ended Ci1
INP 3
Signals
75kΩ
Ci20.022µF Ri2
INN 4
75kΩ
0.022µF
APA2011/
2011A
7
6
GND
VDD
VDD
4Ω
5 OUTP
*R1: Setting the Maximum Output Power
VDR =
R1
2(VDR − 0.5VDD )2
× VDD * PO =
R1 + 10kΩ
R SPK
AV =
100k Ω
× 5.6 = 5.6(V/V), A V = 20Log5.6 = 15dB
75k Ω (Ri1 & R i2 ) + 25kΩ
RSPK: Speaker Resistor
Note : *The setting value has 15% variation by IC process and this equation only for WLCSP1.5x1.5-9 package, the TDFN3x3-8
package’s output power will less than the calculation.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
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APA2011/2011A
Function Description
Fully Differential Amplifier
The APA2011/2011A modulation scheme is shown in fig-
The APA2011/2011A is a fully differential amplifier with
differential inputs and outputs. The fully differential has
ure 1. The outputs VOUTP and VOUTN are in phase with each
other when no input signals. When output > 0V, the duty
some advantages versus traditional amplifier. First, don’t
need the input coupling capacitors because the com-
cycle of VOUTP is greater than 50% and VOUTN is less than
50%; when output <0V, the duty cycle of VOUTP is less than
mon-mode feedback will compensate the input bias. The
inputs can biased from 0.5V to VDD-0.5V, and the outputs
50% and VOUTN is greater than 50%. This method reduces
the switching current across the load and reduces the I2R
still be biased at mid-supply of APA2011/2011A. If the inputs are biased out of the input range, the coupling ca-
losses in the load that improves the amplifier’s efficiency.
This modulation scheme has very short pulses across
pacitors are required. Second, don’t need the mid-supply capacitor (CB) because any shift of the mid-supply of
the load, this making the small ripple current and very
little loss on the load, and the LC filter can be eliminated
APA2011/2011A will have the same affect for both positive
& negative channel, and will cancel at the differential
in most applications. Added the LC filter can increase the
efficiency by filter the ripple current.
outputs. Third, the fully differential amplifier will cancel
the GSM RF transmitter’s signal (217Hz).
Non-Clipping Function (APA2011A)
Maximum Output Power
Class D Operation
Output = 0V
AV=0dB
VOUT
VOUTP
AV=15dB
VOUTN
VOUT
(VOUTP-VOUTN)
VIN
IOUT
Output > 0V
Figure 2. APA2011A Non-Clipping Control Function
VOUTP
The APA2011A provides the 15 steps Non-Clipping
VOUTN
Control, and the range is from 15dB to 0dB, 1dB/step.
When the output reaches the maximum power setting
VOUT
(VOUTP-VOUTN)
value, the internal Programmable Gain Amplifier (PGA)
will decrease the gain for prevent the output waveform
IOUT
clipping. This feature prevents speaker damage from
occurring clipping.
Output < 0V
Using the DR pin to set the non-clipping function and
limit the output power. Disable the AGC, when VDR<0.2VDD,
VOUTP
and if the 0.2VDD<VDR<0.55VDD, the VDR is set to 0.55VDD by
internal, this is maximum power limit (Minimum the out-
VOUTN
put power).
VOUT
(VOUTP-VOUTN)
IOUT
VDR =
R1
× VDD
R1 + 10kΩ
* PO =
2( VDR − 0.5 VDD )2
RSPK
(1)
RSPK: Speaker Resistor (2)
Figure 1. APA2011/2011 Output Waveform (Voltage &
Current)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
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APA2011/2011A
Function Description (Cont.)
Non-Clipping Function (APA2011A) (Cont.)
Attack Time and Release Time
Note: *The setting value has 15% variation by IC process and
this equation only for WLCSP1.5x1.5-9 package, the TDFN3x3-8
package’s output power will less than the calculation.
Attack Time
Release
Time
Gain
Dynamic Range Control Function
Limit Level
Maximum Output Power
VOUT
VOUT
AV
AV=15dB
Power Limit
Time
AGC Start Point
AV=0dB
A
VIN
B C
D
Limit Level
Figure 4. APA2011 Output Signal vs. Time
Figure 3. APA2011 Auto Gain Control Function
A.
B.
The APA2011 provides the 15 steps Dynamic Range Control (DRC), and the range is from 15dB to 0dB, 1dB/step.
C.
D.
DRC provides continuous automatic gain adjustment to
the amplifier through an internal Programmable Gain
Amplifier (PGA). This feature enhances the perceived
audio loudness and prevents speaker damage from oc-
The output level excesses the AGC start point.
A to B is the attack time (32ms), but the Gain needs to
change at output signal zero crossing.
The output level is under the limit level.
D to E is release time (512ms), but the Gain needs to change
at output signal zero crossing..
When the APA2011/2011A senses the input signal excesses the start point of DRC/Non-clipping, it needs 32ms
curring clipping at the same time.
The equations 1 & 2 are the method that set the maxi-
to decrease the gain, this calls “Attack Time”. And if the
input signal is small than the threshold about 512ms, the
mum output power. If the R 1=40kΩ, the V DR is 4V.
Therefore, the maximum output power is 1.125W
gain will be recovery, this time calls “ release time”.
The APA2011’s compress ratio is 2:1, it means when the
(RL=4Ω), and the output voltage swing is limited at 3Vpp
(1.5Vp) [The limited voltage can be calculated by 4V(VDR)-
input signal has the 2dB change, the output signal will
change 1dB. Because most small form speakers have
2.5V(Internal Bypass Voltage)=1.5V]. The AGC start point
is 0.536VPP (1.5Vp/5.6(AV)=0.268VP) at output, it means
only small dynamic range, the compress allows input
signal with large dynamic range to fit into a small speaker
when the output power excesses 0.036W, the AGC will
start work and decrease the gain by 1dB. If the input sig-
with small dynamic rage.
And the APA2011A is just decrease the gain to avoid the
nal increase un-limit, the gain will be decreased until the
maximum gain attenuation (15dB).
output signal clipping, and the maximum control is 15dB
gain.
Limit Level
VIN
Shutdown Operation
In order to reduce power consumption while not in use,
Time
the APA2011/2011A contains a shutdown function to externally turn off the amplifier bias circuitry. This shutdown
Limit Level
feature turns the amplifier off when logic low is placed on
the SD pin for APA2011/2011A. The trigger point between
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
17
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APA2011/2011A
Function Description (Cont.)
Shutdown Operation (Cont.)
a logic high and logic low level is typically 1.4V. It is best to
switch between the ground and the supply voltage VDD to
provide maximum device performance. By switching the
SD pin to a low level, the amplifier enters a low-consumption- current state, IDD for APA2011/2011A is in shutdown
mode. On normal operating, APA2011/2011A’s SD pin
should pull to a high level to keep the IC out of the shutdown mode. The SD pin should be tied to a definite voltage to avoid unwanted state changes.
Over-Current Protection
The APA2011/2011A monitors the output current. When
the current exceeds the current-limit threshold, the
APA2011/2011A turns off the output stage to prevent the
output device from damages in over-current or short-circuit condition. The IC will turn on the output buffer after
1ms, but if the over-current or short-circuits condition still
remains, it enters the Over-Current protection again. The
situation will circulate until the over-current or short-circuits has be removed.
Thermal Protection
The over-temperature circuit limits the junction temperature of the APA2011/2011A. When the junction temperature exceeds TJ = +150 oC, a thermal sensor turns off the
output buffer, allowing the devices to cool. The thermal
sensor allows the amplifier to start-up after the junction
temperature down about 125 oC. The thermal protection
is designed with a 25 oC hysteresis to lower the average
TJ during continuous thermal overload conditions, increasing lifetime of the IC.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
18
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APA2011/2011A
Application Information
tor is the leakage path from the input source through the
input network (Ri + Rf, Ci) to the load. This leakage current
Square Wave Into The Speaker
Apply the square wave into the speaker may cause the
creates a DC offset voltage at the input to the amplifier
that reduces useful headroom, especially in high gain
voice coil of speaker jump out the air gap and deface the
voice coil. However, this depends on the amplitude of
applications. For this reason, a low-leakage tantalum or
ceramic capacitor is the best choice. When polarized ca-
square wave is high enough and the bandwidth of speaker
is higher than the square wave’s frequency. For 500kHz
pacitors are used, the positive side of the capacitor should
face the amplifier input in most applications because the
switching frequency, this is not issued for the speaker
because the frequency is beyond the audio band and
DC level of the amplifier input is held at VDD/2. Please note
that it is important to confirm the capacitor polarity in the
can’t significantly move the voice coil, as cone movement
is proportional to 1/f2 for frequency out of audio band.
application.
Input Resistor, Ri
Ferrite Bead Selection
The APA2011/2011A’s input resistor is fixed and the value
is 25kΩ. The input resistance has wide variation (+/-5%)
is caused by manufacture. The gain also can be set by
the external resistors (Riexr).
AV =
If the traces form APA2011/2011A to speaker is short, the
ferrite bead filters can reduce the high frequency radiated
to meet the FCC & CE required.
A ferrite that has very low impedance at low frequencies
and high impedance at high frequencies (above 1 MHz)
100kΩ
100kΩ
× 5 .6 =
× 5.6 (3)
25kΩ + Riexr (Ri1 & Ri2 )
Ri + Riexr
is recommended.
For fully differential operating, the Riexr (Ri1& Ri2) match is
Output Low-Pass Filter
very important for CMRR, PSRR, and harmonic distortion
performance. It’s recommended to use 1% tolerance re-
If the traces form APA2011/2011A to speaker are short, it
don’t require output filter for FCC & CE standard.
sistor or better. Keep the input trace as short as possible
to limit the noise injection. The gain is recommended to
A ferrite bead may be needed if it’s failing the test for FCC
or CE tested without the LC filter. The figure 5 is the sample
set 5.6V/V or lower for optimal the APA2011/2011A’s
performance.
for added ferrite bead; the ferrite show choosing high
impedance in high frequency.
Input Capacitor, Ci
In the typical application, an input capacitor, Ci, is required
to allow the amplifier to bias the input signal to the proper
DC level for optimum operation. In this case, Ci and the
input impedance Ri form a high-pass filter with the corner
frequency determined in the following equation:
1
fC(highpass ) =
2πRiCi
VON
Ferrite
Bead
1nF
(4)
Ferrite
Bead
The value of Ci must be considered carefully because it
directly affects the low frequency performance of the circuit.
VOP
4Ω
1nF
Where Ri is 25kΩ (minimum) and the specification calls
for a flat bass response down to 100Hz. Equation is
reconfigured as below:
Ci =
1
2πRifc
Figure 5. Ferrite Bead Output Filter
(5)
Figure 6 and 7 and are examples for added the LC filter
(Butterworth), it’s recommended for the situation that the
trace form amplifier to speaker is too long, and needs to
When the input resistance variation is considered, the Ci
is 0.064µF, so a value in the range of 0.1µF to 0.22µF
would be chosen. A further consideration for this capaciCopyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
eliminate the radiated emission or EMI.
19
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APA2011/2011A
Application Information (Cont.)
typically 0.1µF placed as close as possible to the device
VDD pin for works best. For filtering lower frequency noise
Output Low-Pass Filter (Cont.)
signals, a large aluminum electrolytic capacitor of 10µF
or greater placed near the audio power amplifier is
recommended.
OUTP 36µH
Layout Recommendation
1µF
9XΦ0.275mm
OUTN
36µH
8Ω
.
1µF
0.5mm
Figure 6. LC output filter for 8Ω speaker
OUTP 18µH
2.2µF
0.5mm
OUTN
18µH
4Ω
Figure 8. WLCSP1.5x1.5-9 Land Pattern Recommendation
2.2µF
ThermalVia Diamater
12milx5
Ground Plane for
ThermalPAD
0.275mm
1.2mm
Figure 7. LC Output Filter for 4Ω Speaker
0.35mm
Figure 6 and 7’s low pass filter cut-off frequency are 25kHz
fC(lowpass) =
1
2π LC
2.5mm
(FC).
(6)
Power-Supply Decoupling Capacitor, CS
0.65mm
The APA2011/2011A is a high-performance CMOS audio
1.8mm
amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as
Figure 9. TDFN3x3-8 Land Pattern Recommendation
low as possible. Power supply decoupling also prevents
the oscillations being caused by long lead length be-
1. All components should be placed close to the APA2011/
tween the amplifier and the speaker.
The optimum decoupling is achieved by using two differ-
2011A. For example, the input capacitor (Ci) should be
close to APA2011/2011A’s input pins to avoid causing
ent types of capacitors that targets on different types of
noise on the power supply leads. For higher frequency
noise coupling to APA2011/2011A’s high impedance
inputs; the decoupling capacitor (CS) should be placed
transients, spikes, or digital hash on the line, a good low
equivalent-series-resistance (ESR) ceramic capacitor,
by the APA2011’s power pin to decouple the power rail
noise.
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Rev. A.4 - Aug., 2013
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APA2011/2011A
Application Information (Cont.)
Layout Recommendation (Cont.)
2. The output traces should be short, wide (>50mil) and
symmetric.
3. The input trace should be short and symmetric.
4. The power trace width should greater than 50mil.
5. The TDFN3x3-8 Thermal PAD should be soldered on
PCB, and the ground plane needs soldered mask (to
avoid short circuit) except the Thermal PAD area.
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Rev. A.4 - Aug., 2013
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APA2011/2011A
Package Information
E
WLCSP1.5x1.5-9
PIN A1
D
A2
A1
e
b
A
e
WLCSP1.5x1.5-9
S
Y
M
B
O
L
MIN.
MAX.
MIN.
MAX.
A
0.53
0.67
0.021
0.026
A1
0.20
0.24
0.008
0.009
A2
0.33
0.43
0.013
0.017
MILLIMETERS
INCHES
b
0.29
0.31
0.011
0.012
D
1.47
1.53
0.058
0.060
E
1.47
1.53
0.058
0.060
e
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
0.50 BSC
0.020 BSC
22
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APA2011/2011A
Package Information
TDFN3x3-8
A
b
E
D
Pin 1
A1
D2
A3
L K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
TDFN3x3-8
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
b
0.25
0.35
0.010
0.014
D
2.90
3.10
0.114
0.122
D2
1.90
2.40
0.075
0.094
E
2.90
3.10
0.114
0.122
E2
1.40
1.75
0.055
0.069
0.50
0.012
e
0.65 BSC
L
0.30
K
0.20
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
0.026 BSC
0.020
0.008
23
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APA2011/2011A
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
WLCSP1.5x1.5-9
Application
TDFN3x3-8
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
1.70±0.20
1.70±0.20
0.90±0.20
W
E1
F
4.0±0.10
4.0±0.10
A
H
T1
C
d
D
178.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±0.20
1.30±0.20
12.0±0.30 1.75±0.10
5.5±0.05
(mm)
Devices Per Unit
Package Type
WLCSP1.5x1.5-9
TDFN3x3-8
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
Unit
Quantity
Tape & Reel
Tape & Reel
3000
3000
24
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APA2011/2011A
Taping Direction Information
WLCSP1.5x1.5-9
USER DIRECTION OF FEED
TDFN3x3-8
USER DIRECTION OF FEED
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APA2011/2011A
Classification Profile
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
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APA2011/2011A
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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