Ordering number : ENN*7056 CMOS IC LC35V1000BM, BTS-70U Asynchronous Silicon Gate 1M (131,072 words ×8 bits) SRAM Preliminary Overview Package Dimensions The LC35V1000BM and LC35V1000BTS-70U are asynchronous silicon gate CMOS static RAM devices with a 131,072-word by 8-bit structure. They provide two chip enable pins (CE1 and CE2) for device select/deselect control and one output enable pin (OE) for output control. They feature high speed, low power, and a wide operating temperature range.This makes them optimal for use in systems that require high speed, low power, and battery backup. They also support easy memory expansion. unit: mm 3205A-SOP32 [LC35V1000BM-70U] 0.8 20.5 17 14.0 11.2 32 1 1.27 16 0.4 0.15 0.2 (2.7) (0.73) SANYO: SOP32 unit: mm 3228A-TSOP32DA [LC35V1000BTS-70U] 0.5 8.0 17 1 0.5 16 0.2 0.08 (0.25) (1.0) 14.0 12.4 32 1.2max • Low-voltage operation: 3.0 to 3.6 V • Wide operating temperature range: –40 to +85°C • Access time: 70 ns (maximum): LC35V1000BM and LC35V1000BTS-70U. • Low current drain Standby mode: 0.05 µA (typical*) at Ta = +25°C *: When VCC = 3.0 V 10.0 µA (maximum) at Ta = +70°C 20.0 µA (maximum) at Ta = +85°C • Data retention voltage: 2.0 to 3.6 V • No clock required (fully static circuits) • Input/output shared function pins, 3-state output pins • Package 32-pin SOP (525 mil) plastic package: LC35V1000BM 32-pin TSOP (8 ×14 mm) plastic package: LC35V1000BTS 3.1max Features 0.125 SANYO: TSOP32DA Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 41902RM (OT) No. 7056-1/9 LC35V1000BM, BTS-70U Pin Assignment No. 7056-2/9 LC35V1000BM, BTS-70U Raw Decoder Address buffer Block Diagram Memory cell array Output buffer Data control circuit Input data buffer Pin Functions A0 to A16 Control circuit Address input WE Ready/write control input OE Output enable input CE, CE2 Chip enable input I/O1 to I/O8 Data I/O VCC, GND Power supply, ground Function Table Mode CE1 CE2 OE WE I/O Supply current Ready cycle L H L H Data output ICCA Write cycle L H X L Data input ICCA Output disable L H H H High impedance ICCA H X X X High impedance ICCS X L X X High impedance ICCS Unselected Note: X indicates H or L. Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Maximum supply voltage Conditions Ratings VCC max Unit 4.6 V V Input pin voltage VIN –0.3* to VCC + 0.3 I/O pin voltage VI/O –0.3 to VCC + 0.3 V Operating temperature Topr –40 to +85 °C –55 to +125 °C Storage temperature Tstg *: For pulse widths under 30 ns: –2.0 V Note: This chip may be destroyed if any stress in excess of the absolute maximum ratings is applied. I/O Capacitances at Ta = 25°C, f = 1 MHz Parameter Symbol Conditions Ratings min typ Unit max Input capacitance CIN VIN = 0 V 6 10 pF I/O capacitance CI/O VI/O = 0 V 6 10 pF Note: These parameters are not measured for all devices, but are sampled values. No. 7056-3/9 LC35V1000BM, BTS-70U DC Allowable Operating Range at Ta = –40 to +85°C Parameter Symbol Ratings Conditions min typ Unit max Supply volgate VCC 3.0 3.6 V High-level input voltage VIH 0.8VCC VCC + 0.3 V Low-level input voltage VIL –0.3* 0.2VCC V 3.3 Note: * The minimum value is –2.0 V for pulse width under 30 ns. DC Electrical Characteristics at Ta = –40 to +85°C, VCC = 3.0 to 3.6 V Parameter Input leakage current I/O leakage current Outpu high-level voltage Outpu low-level voltage Operating supply current (CMOS inputs) Symbol (CMOS inputs) min typ Unit max ILI VIN = 0 to VCC –1.0 +1.0 µA ILO VCE1 = VIH or VCE2 = VIL or VOE = VIH or VWE = VIL, VI/O = 0 to VCC –1.0 +1.0 µA VOH1 VOH1 = –2.0 mA VCC – 0.4 VOH2 VOH2 = –100 µA VCC – 0.1 VOL1 VOL1 = 2.0 mA 0.4 VOL2 VOL2 = –100 µA 0.1 V ICCA2 VCE1 = VIL, VCE2 = VIH, II/O = 0 mA, VIN = VIH or VIL 1.2 mA ICCA3 Standby mode supply current (VCC – 0.2 V/0.2 V inputs) Ratings Conditions ICCS1 ICCS2 VCE1 = VIL, VCE2 = VIH, min cycle II/O = 0 mA, VIN = VIH or VIL, DUTY100% 1 µs cycle VCE2 ≤ 0.2 V or Ta ≤ 85°C (VCE1 ≥ VCC – 0.2 V, Ta ≤ 70°C VCE2 ≥ VCC – 0.2 V) Ta ≤ 25°C VCE1 = VIH or VCE2 = VIL, VIN = 0 to VCC V V 25 2 V mA 20 10 µA 0.4 mA 0.05 Note: * Reference values when VCC = 3.0 V and Ta = 25°C. No. 7056-4/9 LC35V1000BM, BTS-70U AC Electrical Characteristics at Ta = –40 to +85°C, VCC = 3.0 to 3.6 V AC test conditions Input pulse voltage levels: VIL = 0.2 VCC, VIH = 0.8 VCC Input rise and fall times: 5 ns Input and output timing leves: 0.5 VCC Output load: 30 pF (including the jig capacitance) Read cycle Symbol min Read cyle time Parameter tRC 70 max Unit Address access time tAA 70 ns CE1 access time tCA1 70 ns CE2 access time tCA2 70 ns OE access time tOA 40 ns Output hold time tOH 10 ns CE1 output enable time tCOE1 5 ns CE2 output enable time tCOE2 5 ns OE output enable time tOCE 0 CE1 output disable time tCOD1 35 ns CE2 output disable time tCOD2 35 ns OE output disable time tOOD 30 ns max Unit ns ns Write cycle Symbol min Write cyle time Parameter tWC 70 ns Address setup time tAS 0 ns Write pulse width tWP 50 ns CE1 setup time tCW1 60 ns CE2 setup time tCW2 60 ns Write recovery time tWR 0 ns OE1 write recovery time tWR1 0 ns CE2 write recovery time tWR2 0 ns tDS 40 ns Data hold time tDH 0 ns OE1 data hold time tDH1 0 ns CE2 data hold time tDH2 0 ns WE output enable time tWOE 5 WE output disable time tWOD Data setup time ns 35 ns No. 7056-5/9 LC35V1000BM, BTS-70U Timing Charts Read cycle (1) *5 Write cycle (1) (WE write) *3 *4 *4 *5 *7 *2 *2 No. 7056-6/9 LC35V1000BM, BTS-70U Write cycle (2) (CE1 write) *3 *4 *4 *5 Write cycle (2) (CE2 write) *3 *4 *4 *5 No. 7056-7/9 LC35V1000BM, BTS-70U Notes: 1. The times tCOD1, tCOD2, tOOD, and tWOD are stipulated as the times until the output reaches the high-impedance state. They are not stipulated by output voltage level. 2. Do not apply reverse phase signals to the data outputs when the data outputs are in the output state. 3. tWP is the period that CE1 and WE are at the low level and CE2 is at the high level, and is defined as the time from the fall of WE until the rise of CE1 or WE or the fall of CE2, whichever occurs first. 4. tCW1 and tCW2 are the period that CE1 and WE are at the low level and CE2 is at the high level, and are defined as the time from the fall of CE1 or the rise of CE2 to the rise of either CE1 or WE or the fall of CE2, whichever occurs first. 5. The data outputs go to the high-impedance state when any one of the following states hold: OE is at the high level, CE1 is at the high level, CE2 is at the low level, or WE is at the low level. 6. If OE is at the high level during the write cycle, the data outputs will go to the high-impedance state. Data Retention Characteristics at Ta = –40 to +85°C Parameter Data retention supply voltage Conditions VDR1 VCE1 ≥ VCC – 0.2 V, VCE2 ≥ VCC – 0.2 V or VCE2 ≤ 0.2 V 2.0 3.6 V VDR2 VCE2 ≤ 0.2 V 2.0 3.6 V VCC = 3.0 V, VCE1 ≥ VCC – 0.2 V, Data retention supply current Ratings Symbol ICCDR1 min typ –40°C to +85°C VCE2 ≥ VCC – 0.2 V, –40°C to +70°C or VCE2 ≤ 0.2 V +25°C Unit max 16 8 µA 0.05 Chip enable setup time tCDR 0 ns Chip enable hold time tR 5 ms Note: * Ta = +25°C Data Retention Waveforms (1) (CE1 control) Data retention mode Data Retention Waveforms (2) (CE2 control) Data retention mode No. 7056-8/9 LC35V1000BM, BTS-70U Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 2002. Specifications and information herein are subject to change without notice. PS No. 7056-9/9