Ordering number : EN*4974 CMOS LSI LC89201 9600-bps Facsimile Modem Preliminary Overview The LC89201 is a CMOS single-chip, synchronous, halfduplex, 9600-bps fax modem designed for use with public telephone networks. Built in are such essential features for Group III facsimile systems as modulator, demodulator, transmission filters, and V.24 interface. The LSI supports the V.29, V.27ter, V.21ch2, T.30, and T.4 telecommunications standards promulgated by the ITU-T (formerly the CCITT) for transmission at 9600, 7200, 4800, 2400 and 300 bps. Advanced signal processing provides reliable data transmissions even under adverse circuit conditions. Built-in High-level Data Link Control (HDLC) support permits the construction of Error Correction Mode (ECM) facsimile machines. • • • • • • • Built-in eye pattern generator. Adaptive differential pulse-code modulation (ADPCM). Caller ID detection. Built-in diagnostics. Energy-saving CMOS design (typ. 250 mW). Single 5 V power supply. 80-pin flat package (QIP-80E). Package Dimensions unit: mm 3174-QFP80E [LC89201] Features • Support for the following ITU-T standards: V.29 (9600, 7200 and 4800 bps), V.27ter (4800 and 2400 bps), V.21ch2 (300 bps), T.30, and T.4. • Half-duplex operation. • Group III facsimile support. • Automatic switching between high- (V.29 and V.27ter) and low-speed (V.21ch2) incoming facsimiles. • Short training (for ITU-T V.27ter only). • HDLC framing and deframing (V.29, V.27ter, and V.21ch2). • Tone generation and detection. • Dual-tone multifrequency (DTMF) generation and detection. • Call progress tone detection. • Pseudo link back tone generation. • Built-in automatic adaptive equalizer. • Built-in fixed-amplitude amplifier. — Link amplitude equalizer — Cable amplitude equalizer • Built-in transmission filters (digital filters). • Programmable transmission level adjustment. • Dynamic range for reception of 0 to –47 dBm. • Programmable reception sensitivity adjustment. • DTE interface. — Serial interface (ITU-T V.24) — Parallel interface (4 words × 8 bits, with built-in FIFO) • Programmable interrupt generator. SANYO: QIP80E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 92995HA (OT) No. 4974-1/8 LC89201 System Block Diagram No. 4974-2/8 LC89201 Internal Block Diagram No. 4974-3/8 LC89201 Pin Assignment Pin Functions 1. Power Supply, Clock and Test Pins Pin No. Symbol I/O 14 31 54 63 73 Function DVDD P Digital power supply 8 13 24 35 53 64 74 DGND P Digital ground 38 51 AVDD P Analog power supply 37 52 AGND P Analog ground Frequency multiplier PLL power supply 1 PVDD P 7 PGND P Frequency multiplier PLL ground 50 VREF P Reference power supply. This must be half AVDD. System clock input (29.4912 MHz) 9 X2 I 10 X1 O Oscillator amplifier output 80 CLKOUT O Output clock, one-quarter the frequency of the internal master clock (9.216 MHz). 56 TESTMB I Test pin. Connect to DVDD. 55 CKSB I Test pin. Connect to DVDD. No. 4974-4/8 LC89201 2. DTE Interface Pins Pin No. Symbol I/O 29 28 27 26 25 23 22 21 D0 D1 D2 D3 D4 D5 D6 D7 Function B Data bus to host CPU 20 19 18 17 16 A0 A1 A2 A3 A4 I Address bus to host CPU 30 CSB I Chip select signal 32 READB I Interface memory read signal 33 WRITEB I Interface memory write signal 34 IREQB O Interrupt request to host CPU 15 RESETB I System reset signal 3. Eye Pattern Interface Pins Pin No. Symbol I/O 67 EYECLK O Timing clock for generating eye pattern data. This may be used as the shift clock for an external shift register. Function 68 EYESYNC O Eye pattern synchronization signal 66 65 EYEX EYEY O Eye pattern data serial outputs (8 bits, MSB first) 4. V.24 (RS-232C) Interface Pins Pin No. Symbol I/O 57 RTSB I Request to send signal. The low level at this pin starts transmission; the high level suspends it. Function 59 CTSB O Clear to send signal. The low level at this pin signals the availability of data for transmission; the high level indicates that the data is invalid. 58 RLSDB O Received line signal data signal. The low level at this pin gives the timing for transferring the data received to the terminal. 61 TXD I Transmit data input 60 RXD O Receive data output 62 DCLK O Transmission data clock output 5. Analog Signal Pins Pin No. Symbol I/O 39 TXA O Transmitter analog output Function 44 RXA I Receiver analog input 43 AUXIN I Auxiliary analog input 40 OPA2P I 41 OPA2M I 42 OPA2O O 47 OPA1P I 46 OPA1M I 45 OPA1O O Transmission buffer input/output pins. (For details, see circuit diagram.) Reception buffer input/output pins (For details, see circuit diagram.) 49 PGCI I Reception gain adjustment circuit input. (For details, seecircuit diagram.) 48 PGCO O Reception gain adjustment circuit output. No. 4974-5/8 LC89201 6. System signal pins Pin No. Symbol I/O 11 MC I Program mode control signal. Connect to DVDD. Function 78 HOLDB I System hold signal. Connect to DVDD. 77 HOLDAB O System hold confirmation signal. 6 PRTSB I Frequency multiplier PLL reset input. (For details, see circuit diagram.) 3 PO O Phase comparator output. (For details, see circuit diagram.) 4 VCOI I Voltage-controlled oscillator input. (For details, seecircuit diagram.) 5 VCOO O Voltage-controlled oscillator output 2 RIN I Voltage-controlled oscillator adjustment input. (For details, see circuit diagram.) 36 STOPB I Oscillator amplifier STOP input Note: All other pins are to be left unconnected. Specifications Absolute Maximum Ratings at DGND, AGND, PGND = 0 V Parameter Symbol Maximum supply voltage I/O voltages Allowable power dissipation Conditions Ratings Unit DVDD max Ta = 25°C –0.3 to +7.0 V AVDD max Ta = 25°C –0.3 to +7.0 V PVDD max Ta = 25°C –0.3 to +7.0 V VI VO Ta = 25°C –0.3 to VDD + 0.3 V Pd max Ta ≤ 70°C 400 mW Operating temperature Topr –30 to +70 Storage temperature Tstg –55 to +125 °C Hand soldering (3 seconds) 350 °C Reflow (10 seconds) 235 °C Soldering heat resistance °C Allowable Operating Ranges at Ta = –30 to +70°C, DGND, AGND, PGND = 0 V Parameter Supply voltage Input voltage Symbol min typ max Unit DVDD 4.5 5.0 5.5 V AVDD 4.5 5.0 5.5 V PVDD 4.5 5.0 5.5 V VDD V VIN Conditions 0 No. 4974-6/8 LC89201 Electrical Characteristics at Ta = –30 to +70°C, DGND, AGND, PGND = 0 V, DVDD, AVDD, PVDD = 4.5 to 5.5 V Parameter Symbol Input high level voltage VIH Input low level voltage VIL Input leak current IL Conditions TTL levels: RESETB, PRSTB, STOPB, A0 to A4, D0 to D7, CSB, READB, WRITEB, RTSB, TXD, HOLDB, MC, TESTMB, CKSB min typ VIN = DGND, AGND, PGND, DVDD, AVDD, PVDD: RESETB, PRSTB, STOPB, A0 to A4, D0 to D7, CSB, READB, WRITEB, RTSB, TXD, HOLDB, MC, TESTMB, CKSB –1 2.4 Output high level voltage VOH IOH = –3 mA, TTL levels: WEB, MENB, CLKOUT, HOLDAB, PA0 to PA5, D0 to D7, IREQB, CTSB, RLSDB, RXD, DCLK, VCOO, EYEX, EYEY, EYECLK, EYESYNC Output low level voltage VOL IOL = 3 mA, TTL levels: WEB, MENB, CLKOUT, HOLDAB, PA0 to PA5, D0 to D7, IREQB, CTSB, RLSDB, RXD, DCLK, VCOO, EYEX, EYEY, EYECLK, EYESYNC Output leak current IOZ For high-impedance output: D0 to D7 Oscillator frequency fOSC X2, X1 VREF input voltage VREF VREF VREF impedance RREF VREF max Unit 2.2 V 0.8 V +1 µA V 0.4 –10 +10 µA 29.4912 MHz VDD/2 V 1 MΩ Input voltage range VIA RIN, VCOI, OPA1M, OPA1P, RAX, OPA2M, OPA2P, PGCI VDD*0.2 VDD*0.8 Output voltage range VOA TXA, PGCO, OPA1O, OPA2O VDD*0.2 VDD*0.8 Output impedance RO TXA, PGCO, OPA1O, OPA2O Current drain IDD VDD = 5.5 V VDD = 5.0 V V 50 V V 7 kΩ 80 mA mA AC Characteristics 1. DTE interface timing Read cycle timing No. 4974-7/8 LC89201 Parameter Symbol Conditions min typ max Unit Address stabilization time (relative to READB signal) TAR 15 ns Chip select stabilization time (relative to READB signal) TCR 0 ns Data propagation delay TRD Data float propagation delay TDF 10 ns Address hold time (relative to READB signal) TRA 10 ns Address stabilization time (relative to WRITEB signal) TAW 15 ns Chip select stabilization time (relative to WRITEB signal) TCW 0 ns Data setup time TDW 20 ns Data hold time TWD 5 ns Address hold time (relative to WRITEB signal) TWA 10 ns 30 ns 2. Reset timing Parameter Symbol Conditions min typ max Unit PRTSB pulse width T1 500 µs PRTSB propagation delay relative to RESETB T2 5 ms RESETB pulse width T3 500 ns ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1995. Specifications and information herein are subject to change without notice. PS No. 4974-8/8 Caption P.7/8 A4 to A0 D7 to D0 A4 to A0 D7 to D0 P.2 1. Host CPU 2. 29.4912-MHz crystal oscillator or crystal resonator 3. Telephone line 4. Power supply 5. Auxiliary analog input 6. Eye pattern generator 7. Oscilloscope 8. Power-on reset circuit P.3 1. Interface memory 2. Timing generator 3. V.24 interface 4. Eye pattern generator 5. HDLC block 6. Analog front end New P2/8 2. 29.4912-MHz crystal oscillator or crystal resonator 8. Power-on reset circuit D0 to D7 A0 to A4 P3/8 D7 to D0 A4 to A0