ETC LE28DW3215AT-80

32 Megabit FlashBank Memory
LE28DW3215AT-80
1
FEATURES:
Single 3.0-Volt Read and Write Operations
Separate Memory Banks by Address Space
− Bank1: 16Mbit(1024K x 16) Flash
− Bank2: 16Mbit(1024K x 16) Flash
− Simultaneous Read and Write Capability
Superior Reliability
− Endurance: 10,000Cycles
100,000Cycies(Erase Verify Mode)
− Data Retention: 10years
Low Power Consumption
− Active Current, Read:
10mA(typical)
− Active Current, Read & Write: 30mA(typical)
− Standby Current:
5uA(typical)
− Auto Low Power Mode Current: 5uA(typical)
Fast Write Operation
− Bank Erase + Program:
15sec(typical)
− Block Erase + Program:
500ms(typical)
− Sector Erase + Program:
45ms(typical)
•
•
• Read Access Time
•
• Flash Bank: Two Small Erase Element Sizes
•
•
•
Product Description
The LE28DW3215AT-80 consists of two memory banks,
2each contains of 1024Kx16bits sector mode flash EEPROM
manufactured With SANYO’s proprietary, high performance
Flash Technology. The LE28DW3215AT-80 writes with a 3.0volt-only power supply.
All memory banks share common I/O lines, WE#, and OE#.
Memory bank selection is by bank select address (A20).
WE# is used with SDP to control the Erase and Program
operation in each memory bank.
− 80nsec
• Latched Address and Data
• End of Write Detection
− Toggle Bit / Data# Polling
•
− 2K Words per Sector or 32K Words per Block
− Erase either element before Word Program
CMOS I/O Compatibility
Packages Available
− 48-Pin TSOP (10mm x 14mm)
Continuous Hardware and Software Data
Protection (SDP)
•
The LE28DW3215AT-80 is divided into two separate memory
banks. Each Flash Bank is typically used for program storage
and contains 512sectors of 2K words or 32blocks of 32K
words.
Any bank may be used for executing code while writing data
to a different bank. Each memory bank is controlled by
separate Bank selection address (A20) lines.
LE28DW3215AT-80 inherently uses less energy during
Erase, and Program than alternative flash technologies. The
total energy consumed is a function of the applied voltage,
current, and time of application. Since for any given voltage
range, the Flash technology uses less current to program and
has a shorter Erase time, the total energy consumed during
any Erase or Program operation is less than alternative flash
technologies. The Auto Low Power mode automatically
reduces the active read current to approximately the same as
standby; thus, providing an average read current of
approximately 1mA/MHz of Read cycle time.
Device Operation
The LE28DW3215AT-80 operates as two independent
16Megabit Word Program, Sector Erase flash EEPROMs.
Two memory Banks are spareted by the address space.
The LE28DW3215AT-80 provides the added functionality of
being able to simultaneously read from one memory bank
while erasing, or programming to one other memory bank.
Once the internally controlled Erase or Program cycle in a
memory bank has commenced, a different memory bank can
be accessed for read. Also, once WE# and CE# are high
during the SDP load sequence, a different bank may be
accessed to read. LE28DW3215AT-80 which selectes banks
(A20) by a address. It can be used as a normal conventinal
flash memory when operats erase or program operation to
only a bank at non-concurrent operation.
The device ID cannot be accessed while any bank is writing,
erasing, or programming.
The Auto Low Power Mode automatically puts the
LE28DW3215AT-80 in a near standby mode after data has
been accessed with a valid Read operation. This reduces the
IDD active read current from typically 10mA to typically 5uA.
The Auto Low Power mode reduces the typical IDD active
read current to the range of 1mA/MHz of Read cycle time. If a
concurrent Read while Write is being performed, the IDD is
reduced to typically 40mA. The device exits the Auto Low
Power mode with any address transition or control signal
transition used to initiate another Read cycle, with no access
time penalty.
The Bank1 is assigned as 000000h to 0FFFFFh, Bank2 is
assigned as 100000h to 1FFFFFh.
SANYO Electric Co.,Ltd.Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
The Flash Bank product family was jointly developed by SANYO and sillicon storage Technology, Inc. (SST), under SST’s technology license. This preliminary secification is subject to change without noticc.
R.0.00 (2002/2/6) No.XXXX -1/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
Read
The Read operation of the LE28DW3215AT-80 Flash banks
is controlled by CE# and OE#, a chip enable and output
enable both have to be low for the system to obtain data from
the outputs. OE# is the output control and is used to gate
data from the output pins. The data bus is in high impedance
state when OE# is high. Refer to the timing waveforms for
further details (Figure3).
When the read operation is executed without address change
after power switch on, CE# should be changed the level high
to low. If the read operation is executed after programming,
CE# should be changed the level high to low.
Write
All Write operations are initiated by first issuing the Software
Data Protect (SDP) entry sequence for Bank, Block, or Sector
Erase. Word Program in the selected Flash Bank. Word
Program and all Erase commands have a fixed duration, that
will not vary over the life of the device, i.e., are independent
of the number of Erase/Program cycles endured.
Either Flash bank may be read to another Flash Bank during
the internally controlled write cycle.
The device is always in the Software Data Protected mode
for all write operations Write operations are controlled by
toggling WE# or CE#. The falling edge of WE# or CE#,
whichever occurs last, latches the address. The rising edge
of WE# or CE#, whichever occurs first, latches the data and
initiates the Erase or Program cycle.
For the purposes of simplification, the following descriptions
will assume WE# is toggled to initiate an Erase or Program.
toggling the applicable CE# will accomplish the same
function. (Note, there are separate timing diagrams to
illustrate both WE# and CE# controlled Program or Write
commands.)
Word Program
The Word Program operation consists of issuing the SDP
Word Program command, initiated by forcing CE# and WE#
low, and OE# high. The words to be programmed must be in
the erased state, prior to programming. The Word Program
command programs the desired addresses word by word.
During the Word Program cycle, the addresses are latched
by the falling edge of WE#. The data is latched by the rising
edge of WE#. (See Figure4-1 for WE# or 4-2 for CE#
controlled Word Program cycle timing waveforms, Table3 for
the command sequence, and Figure15 for a flowchart.)
During the Erase or Program operation, the only valid reads
from that bank are Data# Polling and Toggle Bit. The other
bank may be read.
2
Erase Operations
The Bank Erase is initiated by a specific six-word load
sequence (See Tables3). A Bank Erase will typically be less
than 70ms. An alternative to the Bank Erase in the Flash
bank is the Block or Sector Erase. The Block Erase will erase
an entire Block (32K words) in typically 15ms. The Sector
Erase will erase an entire sector (2048 Words) in typically
15ms. The Sector Erase provides a means to alter a single
sector using the Sector Erase and Word Program modes.
The Sector Erase is initiated by a specific six-word load
sequence (see Table3).
During any Sector, Block, or Bank Erase within a bank, any
other bank may be read.
Bank Erase
The LE28DW3215AT-80 provides a Bank Erase mode, which
allows the user to clear the Flash bank to the ”1” state. This is
useful when the entire Flash must be quickly erased.
The software Flash Bank Erase mode is initiated by issuing
the specific six-word loading sequence, as in the Software
Data Protection operation. After the loading cycle, the device
enters into an internally timed cycle. (See Table3 for specific
codes, Figure5-1 for a timing waveform, Figure12 for a
flowchart.)
Block Erase
The LE28DW3215AT-80 provides a Block Erase mode,
which allows the user to clear any block in the Flash bank to
the ”1” state.
The software Block Erase mode is initiated by issuing the
specific six-word loading sequence, as in the Software Data
Protect operation. After the loading cycle, the device enters
into an internally timed Erase cycle. (See Table3 for specific
codes, Figure5-2 for a timing waveform, and Figure13 for a
flowchart.) During the Erase operation, the only valid reads
are Data# Polling and Toggle Bit from the selected bank,
other banks may perform normal read.
Sector Erase
The LE28DW3215AT-80 provides a Sector Erase mode,
which allows the user to clear any sector in the Flash bank to
the ”1” state.
The software Sector Erase mode is initiated by issuing the
specific six-word loading sequence, as in the Software Data
Protect operation. After the loading cycle, the device enters
into an internally timed Erase cycle. (See Table3 for specific
codes, Figure5-3 for the timing waveform, and Figure14 for a
flowchart.) During the Erase operation, the only valid reads
are Data# Polling and Toggle Bit from the selected bank,
other banks may perform normal read.
The specified Bank, Block, or Sector Erase time is the only
time required to erase. There are no preprogramming or
other commands or cycles required either internally or
externally to erase the Bank, block, or sector.
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -2/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
Write Operation Status Detection
The LE28DW3215AT-80 provides two software means to
detect the completion of a Flash bank Program cycle, in order
to optimize the system Write cycle time. The software
detection includes two status bits: Data# Polling (DQ7) and
Toggle Bit (DQ6). The end of Write Detection mode is
enabled after the rising edge of WE#, which initiates the
Internal Erase or Program cycle.
The actual completion of the nonvolatile write is a
synchronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system will
possibly get an erroneous result, i.e. valid data may appear
to conflict with either DQ7 or DQ6. In order to prevent
spurious device rejection, if an erroneous result occurs, the
software routine should include a loop to read the accessed
location an additional two (2) times. If both reads are valid,
then the device has completed the Write cycle, otherwise the
rejection is valid.
There is no provision to abort an Erase or Program operation,
once initiated. For the SANYO Flash technology, the
associated Erase and Program times are so fast, relative to
system reset times, there is no value in aborting the
operation. Note, reads can always occur from any bank not
performing an Erase or Program operation.
Should the system reset, while a Block or Sector Erase or
Word Program is in progress in the bank where the boot
code is stored, the system must wait for the completion of the
operation before reading the bank. Since the maximum time
the system would have to wait is 25ms(for a Block Erase), the
system ability to read the boot code would not be affected.
Data# Polling (DQ7)
When the LE28DW3215AT-80 is in the internal Flash bank
Program cycle, any attempt to read DQ7 of the last word
loaded during the Flash bank Word Load cycle will receive
the complement of the true data. Once the Write cycle is
completed, DQ7 will show true data. The device is then ready
for the next operation. (See Figure 6 for the Flash bank Data
Polling timing waveforms and Figure16 for a flowchart.)
3
The LE28DW3215AT-80 provides a protect area by hardware
protection. The assigned address is the all area of Bank1,
which is set up by WP# when low.
When this operation is executed, the functions which are
Sector erase, Block erase or Word program can not be
accepted.
When the Bank erase operation is executed, all area will be
erased except protected area.
Software Data Protection (SDP)
The LE28DW3215AT-80 provides the JEDEC approved
software data protection scheme as a requirement for
initiating a Write, Erase, or Program operation. With this
scheme, any Write operation requires the inclusion of a
series of three word-load operations to precede the Word
Program operation. The three-word load sequence is used to
initiate the Program cycle, providing optimal protection from
inadvertent Write operations, e. g., during the system powerup or power-down. The six-word sequence is required to
initiate any Bank, Block, or Sector Erase operation.
The requirements for JEDEC compliant SDP are in byte
format. The LE28DW8163T is organized by word; therefore,
the contents of DQ8 to DQ15 are ” Don’t Care ” during any
SDP (3-word or 6-word) command sequence.
During the SDP load command sequence, the SDP load
cycle is suspended when WE# is high. This means a read
may occur to any other bank during the SDP load sequence.
The bank reserve in SDP load sequence is reserved by the
bus cycle of command materialization. If the command
sequence is aborted, e. g., an incorrect address is loaded, or
incorrect data is loaded, the device will return to the Read
mode within TRC of execution of the load error.
Toggle Bit (DQ6)
During the Flash bank internal Write cycle, any consecutive
attempts to read DQ6 will produce alternating 0’s and 1’s, i. e.
toggling between 0 and 1. When the Write cycle is completed,
the toggling will stop. The device is then ready for the next
operation. (See Figure 7 for the Flash bank Toggle Bit timing
waveforms and Figure16 for a flowchart.)
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5ns will not
initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5voits
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high
will inhibit the Write operation. This prevents inadvertent
writes during power-up or power-down.
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -3/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
4
Concurrent Read and Write Operations
The LE28DW3215AT-80 provides the unique benefit of being
able to read any bank, while simultaneously erasing, or
programming one other bank, This allows data alteration
code to be executed from one bank, while altering the data in
another bank. The next table lists all valid states.
Concurrent Read/Write State Table
Bank1
Bank2
Read
No Operation
Read
Write
Write
Read
No Operation
Write
Write
No Operation
No Operation
Read
Note: For the purposes of this table, write means to Block,
Sector, or Bank Erase, or Word Program as applicable
to the appropriate bank.
The device will ignore all SDP commands and toggling of
WE# when an Erase or Program operation is in progress.
Note, Product Identification entry commands use SDP;
therefore, this command will also be ignored while an Erase
or Program, operation is in progress.
Product Identification
The product identification mode identifies the device
manufacturer as SANYO and provides a code to identify each
bank. The manufacturer ID is the same for each bank;
however, each bank has a separate device ID. Each bank is
individually accessed using the applicable Bank Address and
a software command. Users may wish to use the device ID
operation to identify the write algorithm requirements for each
bank. (For details, see Table 3 for software operation and
Figure 8 for timing waveforms.)
Product Identification Table
Data
Maker ID
0062H
Device Code(Bank1)
25B9H
Device Code(Bank2)
25BAH
Device ID codes are unique to each bank. Should a chip ID
be required, any of the bank IDs may be used as the chip ID.
While in the read software ID mode, no other operation is
allowed until after exiting these modes.
Product Identification Mode Exit
In order to return to the standard Read mode, the Product
Identification mode must be exited. Exit is accomplished by
issuing the Software ID exit command, which returns the
device to normal operation. This command may also be used
to reset the device to the Read mode after any inadvertent
transient condition that apparently causes the device to
behave abnormally, e. g., not read correctly. For details, (see
Table3 for software operation and Figures9 for timing
waveforms.)
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -4/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
A15
A14
A13
A12
A11
A10
A9
A8
WE#
A19
A20
NC
NC
CE#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TSOP-48
TypeI
Normal Bend
(10mm x 14mm)
5
A16
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
NC
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
Figure1: Pin Description: TSOP48 (10mm x 14mm)
Symbol
A20
A19-A0
A19-A15
A19-A10
DQ15-DQ0
CE#
OE#
WE#
VDD
VSS
NC
Pin Name
Bank Select address
Flash Bank address
Flash Bank Block address
Flash Bank Sector address
Data Input/ Output
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Function
To activate the Bank1 when low, to activate the Bank2 when high.
To provide Flash Bank address.
To select a Flash Bank Block for erase
To select a Flash Bank Sector for erase
To output data during read cycle and receive input data during write cycle.
The output are in tristate when OE# is high or CE# is high.
To activate the Flash Bank when CE# is low.
To gate the data output buffers.
To control the write, erase or program operations.
To provide 3.0volts supply.(2.7volts to 3.6volts)
Unconnected Pins
Table1: Pin Description
Charge Pump
&
Vref.
Y-Decoder
1024K x 16
Address Buffer
&
Data Latchs
X-Decoder
Flash Bank2
1024K x 16
A20-A0
CE#
OE#
WE#
Flash Bank1
DQ15-DQ0
Control Logic
I/O Buffers
&
Data Latches
Figure2-1: Functionally Block Diagram
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -5/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
Bank1
6
Bank2
Total 32 Block
Total 512 Sector
Total 32 Block
Total 512 Sector
0F8000h-0FFFFFh
0FF800h-0FFFFFh
0FF000h-0FF7FFh
0FE800h-0FEFFFh
0FE000h-0FE7FFh
0FD800h-0FDFFFh
0FD000h-0FD7FFh
0FC800h-0FCFFFh
0FC000h-0FC7FFh
0FB800h-0FBFFFh
0FB000h-0FB7FFh
0FA800h-0FAFFFh
0FA000h-0FA7FFh
0F9800h-0F9FFFh
0F9000h-0F97FFh
0F8800h-0F8FFFh
0F8000h-0F87FFh
1F8000h-1FFFFFh
1FF800h-1FFFFFh
1FF000h-1FF7FFh
1FE800h-1FEFFFh
1FE000h-1FE7FFh
1FD800h-1FDFFFh
1FD000h-1FD7FFh
1FC800h-1FCFFFh
1FC000h-1FC7FFh
1FB800h-1FBFFFh
1FB000h-1FB7FFh
1FA800h-1FAFFFh
1FA000h-1FA7FFh
1F9800h-1F9FFFh
1F9000h-1F97FFh
1F8800h-1F8FFFh
1F8000h-1F87FFh
0F0000h-0F7FFFh
0E8000h-0EFFFFh
0E0000h-0E7FFFh
0D8000h-0DFFFFh
0D0000h-0D7FFFh
0C8000h-0CFFFFh
0C0000h-0C7FFFh
0B8000h-0BFFFFh
0B0000h-0B7FFFh
0A8000h-0AFFFFh
1F0000h-1F7FFFh
1E8000h-1EFFFFh
1E0000h-1E7FFFh
1D8000h-1DFFFFh
1D0000h-1D7FFFh
1C8000h-1CFFFFh
1C0000h-1C7FFFh
1B8000h-1BFFFFh
1B0000h-1B7FFFh
1A8000h-1AFFFFh
0A0000h-0A7FFFh
1A0000h-1A7FFFh
098000h-09FFFFh
198000h-19FFFFh
090000h-097FFFh
190000h-197FFFh
088000h-08FFFFh
188000h-18FFFFh
080000h-087FFFh
180000h-187FFFh
078000h-07FFFFh
178000h-17FFFFh
070000h-077FFFh
170000h-177FFFh
068000h-06FFFFh
168000h-16FFFFh
060000h-067FFFh
160000h-167FFFh
058000h-05FFFFh
050000h-057FFFh
048000h-04FFFFh
040000h-047FFFh
038000h-03FFFFh
030000h-037FFFh
028000h-02FFFFh
020000h-027FFFh
018000h-01FFFFh
010000h-017FFFh
008000h-00FFFFh
000000h-007FFFh
007800h-007FFFh
007000h-0077FFh
006800h-006FFFh
006000h-0067FFh
005800h-005FFFh
005000h-0057FFh
004800h-004FFFh
004000h-0047FFh
003800h-003FFFh
003000h-0037FFh
002800h-002FFFh
002000h-0027FFh
001800h-001FFFh
001000h-0017FFh
000800h-000FFFh
000000h-0007FFh
158000h-15FFFFh
150000h-157FFFh
148000h-14FFFFh
140000h-147FFFh
138000h-13FFFFh
130000h-137FFFh
128000h-12FFFFh
120000h-127FFFh
118000h-11FFFFh
110000h-117FFFh
108000h-10FFFFh
100000h-107FFFh
107800h-107FFFh
107000h-1077FFh
106800h-106FFFh
106000h-1067FFh
105800h-105FFFh
105000h-1057FFh
104800h-104FFFh
104000h-1047FFh
103800h-103FFFh
103000h-1037FFh
102800h-102FFFh
102000h-1027FFh
101800h-101FFFh
101000h-1017FFh
100800h-100FFFh
100000h-1007FFh
Figure2-2: Flash Sector Structure
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -6/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
7
Table: 2 Operating Modes Selection
Array Operating Mode
CE#
OE#
WE#
DQ
A20
A19-A0
Bank1
VIL
VIL
VIH
DOUT
VIL
AIN
Bank2
VIL
VIL
VIH
DOUT
VIH
AIN
Bank1
VIL
VIH
VIL
DIN
VIL
See Table3
Bank2
VIL
VIH
VIL
DIN
VIH
See Table3
Bank1
VIL
VIH
VIL
DIN
VIL
See Table3
Bank2
VIL
VIH
VIL
DIN
VIH
See Table3
Bank1
VIL
VIH
VIL
DIN
VIL
See Table3
Bank2
VIL
VIH
VIH
VIH
X
VIL
VIL
X
VIL
DIN
High Z
X
VIH
X
X
X
X
VIL
VIH
VIL
DIN
VIL
See Table3
See Table3
Read
Block Erase
Sector Erase
Program
Stand-by
Write Inhibit
See Table3
Bank Erase
Bank1
VIL
VIH
VIL
DIN
VIH
CE#
OE#
WE#
DQ
A20
Bank1
VIL
VIL
VIH
DOUT
VIL
Bank2
VIL
VIL
VIH
DOUT
VIH
Bank2
Status Operating Mode
A19-A0
Product Identification
Note3)
A19-A1=VIL
A0=VIL or VIH
Note1: Entering an illegal state during an Erase, Program, or Write operation will not affect the operation, i. e., the
erase program, or write will continue to normal completion
Table: 3 Software Command Codes
1st Bus Cycle
Command Code Address Data
Note1,4 Note5
2nd Bus Cycle
Address Data
Note1,4 Note5
Software ID Entry
5555
AA
2AAA
55
Software ID Exit
5555
AA
2AAA
55
Word Program
5555
AA
2AAA
55
Sector Erase
5555
AA
2AAA
Block Erase
5555
AA
Bank Erase
5555
AA
3rd Bus Cycle
Address Data
Note1,4 Note5
5555
+BAX
5555
+BAX
4th Bus Cycle
Address Data
Note1,4 Note5
5th Bus Cycle
Address Data
Note1,4 Note5
90
Note2
F0
Note3
5555
A0
Word
Address
Data
In
55
5555
80
5555
AA
2AAA
55
2AAA
55
5555
80
5555
AA
2AAA
55
2AAA
55
5555
80
5555
AA
2AAA
55
6th Bus Cycle
Address Data
Note1,4 Note5
SAX
+BAX
LAX
+BAX
5555
+BAX
30
50
10
Notes for Software Command Code:
1.Command Code Address format: A14 - A0 are in HEX code.
When Byte Mode, the format is only used by A14-A0.
2.With A19-A0=0;
Sanyo Manufacturer Code = 0062H is read with A0=0.
Sanyo LE28DW3215AT-80 Device code 25B9h, 25BAh is read with A0=1.
3.The device does not remain in software product ID Mode if powered down.
4.Address A20 to A15 are ” Don’t Care ” for Command sequences.
A20 is bank selection address have been reserved in last bus cycle of command sequence.
5.Data format DQ0 to DQ7 are in HEX and DQ8 to DQ15 are “Don’t care”.
6.BAX = Bank address: A20, LAX= Block address: A19 to A15, SAX = Sector address: A19 to A11.
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -7/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
8
[ Absolute Maximum Stress Ratings ]
Applied conditions greater then those listed under “absolute maximum Stress Ratings “may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device
reliability.
Storage Temperature
D.C.Voltage on Any Pin to Ground Potential
Transient Voltage (<20ns) on Any Pin to Ground Potential
RESET# pin Voltage to Ground Potential
Package Power Dissipation Capability (Ta=25°C)
[ Operating Range ]
Ambient Temperature
VDD
: 0°C to +70°C
: 2.7V to 3.6V
[ AC condition of Test ]
Input Rise/Fall Time
Output Load (See Figures 10 and 11)
[ DC Operating Characteristics]
Symbol
Parameter
Power Supply current
Read
IDD
ISB
ILI
IOL
VIL
VILC
VIH
VIHC
VOL
VOH
: -65°C to +150°C
: -0.5V to VDD+0.5V
: -1.0V to VDD+1.0V
: -0.5V to +13.0V
: 1.0W
: 5ns
: CL=30pF
Max
20
Unit
mA
Erase / Program
40
mA
Read+Erase / Program
60
mA
CE#=VIL ,OE#=WE#=VIH ,
Address Input=VIL / VIH ,at f=10MHz,
WE#=VIH , VDD=VDD(Max)
40
uA
CE#=VIHC , VDD=VDD(Max)
10
10
VDD*0.2
0.2
uA
uA
V
V
V
V
V
V
VIN=VSS to VDD , VDD=VDD(Max)
VOUT= VSS to VDD , VDD=VDD(Max)
Standby current
(CMOS input)
Input Leak current
Output Leak current
Input Low Voltage
Input Low Voltage(CMOS)
Input High Voltage
Input High Voltage(CMOS)
Output Low Voltage
Output High Voltage
Min
VDD*0.8
VDD-0.2
0.2
VDD-0.2
[ Recommand System Power-up Timings ]
Symbol
Parameter
(1)
TPU-READ
(1)
TPU-WRITE
Power-up to Read Operation
Power-up to Write Operation
Test Condition
CE#=VIL ,WE#=VIH , I/O’s open,
Address Input=VIL / VIH ,at f=10MHz,
VDD=VDD(Max)
CE#=WE#=VIL ,OE#=VIH , VDD=VDD(Max)
IOL=100uA , VDD=VDD(Min)
IOH=-100uA , VDD=VDD(Min)
Max
Units
200
200
us
us
Note (1): This Parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
[ Capacitance (Ta=25°C, f=1MHz,other pins open) ]
Symbol
Parameter
Test Condition
(1)
CDQ
I/O Pin Capacitance
VDQ=0V
(1)
CIN
Input Capacitance
VIN=0V
Max
12pF
6pF
Note (1): This Parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
[ Reliability Characteristic ]
Symbol
(1)
NEND
(1)
TDR
Parameter
Endurance
Data Retention
Min Spec
10,000
(2)
100,000
10
Units
Cycle / Sector
Years
Note (1): This Parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Note (2): In case of Erase Verify Mode.
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -8/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
9
[ AC Characteristic ]
Read Cycle Timing Parameters
Symbol
Parameter
Min
Max
TRC
Read Cycle Time
TCE
CE# Access Time
80
ns
TAA
Address Access Time
80
ns
TOE
OE# Access Time
40
ns
TCLZ
80
Units
ns
(1)
CE# Low to Active Output
0
ns
(1)
OE# Low to Active Output
0
ns
(1)
CE#High to High-Z Output
30
ns
(1)
OE#High to High-Z Output
30
ns
TOLZ
TCHZ
TOHZ
(1)
TOH
Output Hold from Address Change
0
ns
Write, Erase, Program Cycle, Timing Parameters
Symbol
Parameter
Min
Max
Units
TBP
Word Program Time
20
us
TSE
Sector Erase Time
25
ms
TLE
Block Erase Time
25
ms
TBE
Bank Erase Time
100
ms
TAS
Address Setup Time
0
ns
TAH
Address Hold Time
50
ns
TCES
CE# Setup Time
0
ns
TCEH
CE# Hold Time
0
ns
TWES
WE# Setup Time
0
ns
TWEH
WE# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
0
ns
TWP
WE# Puls Low Width
50
ns
TWPH
WE# Puls High Time
30
ns
TDS
Data Setup Time
50
ns
TDH
Data Hold Time
0
ns
(1)
TVDDR
VDD Rise Time
0.1
ID READ / Exit Cycle Time
150
TIDA
50
ms
ns
Note (1): This Parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -9/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
TRC
10
TAA
ADDRESS A20-A0
TCE
CE#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
TCLZ
TOH
HIGH-Z
DQ15-DQ0
DATA VALID
TCHZ
DATA VALID
HIGH-Z
Figure3: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS
TBP
ADDRESS A20-A0
5555
2AAA
5555
ADDR
TAH
TDH
TWP
WE#
TAS
TDS
TWPH
OE#
TCEH
CE#
TCES
DQ15-DQ0
AA
SW0
55
SW1
A0
SW2
DATA
WORD
(ADDR/DATA)
Figure4-1: WE# Controlled Word Program Cycle Timing Diagram
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -10/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
11
INTERNAL PROGRAM OPERATION STARTS
TBP
ADDRESS A20-A0
5555
2AAA
5555
ADDR
TAH
TDH
TWP
CE#
TAS
TDS
TWPH
OE#
TWEH
WE#
TWES
AA
SW0
DQ15-DQ0
55
SW1
A0
SW2
DATA
WORD
(ADDR/DATA)
Figure4-2: CE# Controlled Word Program Cycle Timing Diagram
TBE
SIX-BYTE CODE FOR BANK ERASE
ADDRESS A20-A0
5555
TAS
2AAA
5555
5555
2AAA
5555+BAX
TAH
CE#
OE#
TWPH
TWP
TDS
WE#
DQ15-DQ0
TDH
AA
SW0
55
SW1
80
SW2
AA
SW3
55
SW4
10
SW5
Figure5-1: Bank Erase Cycle Timing Diagram
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -11/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
12
TLE
SIX-BYTE CODE FOR BLOCK ERASE
ADDRESS A20-A0
5555
TAS
2AAA
5555
5555
2AAA
LAX+BAX
TAH
CE#
OE#
TWPH
TWP
TDS
WE#
TDH
DQ15-DQ0
AA
SW0
55
SW1
80
SW2
AA
SW3
55
SW4
50
SW5
Figure5-2: Block Erase Cycle Timing Diagram
TSE
SIX-BYTE CODE FOR SECTOR ERASE
ADDRESS A20-A0
5555
TAS
2AAA
5555
5555
2AAA
SAX+BAX
TAH
CE#
OE#
TWPH
TWP
TDS
WE#
DQ15-DQ0
TDH
AA
SW0
55
SW1
80
SW2
AA
SW3
55
SW4
30
SW5
Figure5-3: Sector Erase Cycle Timing Diagram
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -12/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
13
ADDRESS A20-A0
TCE
CE#
TOEH
OE#
TOES
TOE
WE#
DQ7
Data#
Data#
Data#
Data#
Figure6: Data# Polling Timing Diagram
ADDRESS A20-A0
TCE
CE#
TOEH
OE#
WE#
TOES
TOE
TWO READ CYCLE
WITH SAME OUTPUTS
DQ6
Figure7: Toggle Bit Timing Diagram
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -13/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
14
Three-Byte Sequence for
Software ID Entry
ADDRESS A20-A0
5555
2AAA
5555+BAX
0000+BAX 0001+BAX
CE#
OE#
TWP TWPH
TIDA
WE#
TAA
DQ15-DQ0
AA
SW0
55
SW1
90
SW2
0062
25B9/25BA
Figure8: Software ID Entry and Read
Three-Byte Sequence for
Software ID Exit
ADDRESS A20-A0
DQ15-DQ0
5555
2AAA
AA
5555+BAX
55
F0
CE#
OE#
TWP TWPH
TIDA
WE#
SW0
SW1
SW2
Figure9: Software ID Exit
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -14/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
15
V IH T
V HT
V HT
R E FE R E N C E P O IN TS
IN P U T
O U TP U T
V LT
V LT
V ILT
AC test inputs are driven at VIHT (VDD*0.9) for a logic “1” and VILT (VDD*0.1) for a logic ”0” Measurement reference
points for inputs and outputs are at VHT (VDD*0.7) and VLT (VDD*0.3) input rise and fall times (10% to 90%) are<10ns.
Figure10: AC I/O Reference Waveforms
VDD
TO TESTER
RL HIGH
TO DUT
CL
RL LOW
Figure11: A Test Load Example
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -15/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
Bank Erase
16
Block Erase
Start
Start
Software Data Protect
Bank Erase Command
Software Data Protect
Block Erase Command
Wait for End of Erase
(TBE, Data# Polling,or
Toggle Bit)
Set Block Address
Bank Erase Complete
Wait for End of Erase
(TLE, Data# Polling, or
Toggle Bit)
Block Erase Complete
Figure12: Bank Erase Flowchart
Sector Erase
Figure13: Block Erase Flowchart
Word Program
Start
Start
Software Data Protect
Sector Erase Command
Software Data Protect
Word Program Command
Set Sector Address
Set Word Address
Wait for End of Erase
(TSE, Data# Polling,or
Toggle Bit)
Sector Erase Complete
Load Word Data
Wait for End of Program
(TBP, Data# Polling or
Toggle Bit)
Word Program Complete
Figure14: Sector Erase Flowchart
Figure15: Word Program Flowchart
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -16/17
32 Megabit FlashBank Memory
LE28DW3215AT-80
Internal
Timer
Toggle Bit
Data# Polling
Erase or Program
Operation Initiated
Erase or Program
Operation Initiated
Erase or Program
Operation Initiated
Wait for
TBP, TBE, TLE, TSE
Read a Word from
Selected bank, block,
sector, or word
Read DQ7 of the last
address set
( or any address with in
selected bank, block,
sector, for erase )
Erase of Program
Completed
Read the same
Word again
No
No
Is DQ6 the same?
Yes
17
Is DQ7 same
As bit loaded?
Yes
Erase or Program
Completed
Erase or Program
Completed
Figure16: End of Erase or Program Wait Options Flowchart
SANYO Electric Co., Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.0.00 (2002/2/6) No.XXXX -17/17