INTEL TE28F008BET120

E
PRODUCT PREVIEW
8-MBIT (512K X 16, 1024K X 8)
SmartVoltage BOOT BLOCK
FLASH MEMORY FAMILY
28F800BV-T/B, 28F800CV-T/B, 28F008BV-T/B
28F800CE-T/B, 28F008BE-T/B
Intel SmartVoltage Technology
 5V or 12V Program/Erase
 2.7V, 3.3V or 5V Read Operation
 Program Time Reduced 60% at
12V VPP
Extended Cycling Capability
 100,000 Block Erase Cycles
(Commercial Temperature)
 10,000 Block Erase Cycles
(Extended Temperature)
Very High Performance Read
 5V: 70/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time
 3V: 120/150 ns Max Access
65 ns Max. Output Enable Time
 2.7V: 120 ns Max Access
65 ns Max. Output Enable Time
Automated Word/Byte Write and Block
Erase
 Industry-Standard Command User
Interface
 Status Registers
 Erase Suspend Capability
Low Power Consumption
 Max 60 mA Read Current at 5V
 Max 30 mA Read Current at 2.7–3.6V
Automatic Power Savings Feature
 1 mA Typical ICC Active Current in
Static Operation
x8/x16-Selectable Input/Output Bus
 28F800 for High Performance 16- or
32-bit CPUs
Reset/Deep Power-Down Input
 0.2 µA ICCTypical
 Provides Reset for Boot Operations
x8-Only Input/Output Architecture
 28F008B for Space-Constrained
8-bit Applications
Hardware Data Protection Feature
 Erase/Write Lockout during Power
Transitions
Optimized Array Blocking Architecture
 One 16-KB Protected Boot Block
 Two 8-KB Parameter Blocks
 One 96-KB Main Block
 Seven 128-KB Main Blocks
 Top or Bottom Boot Locations
Industry-Standard Surface Mount
Packaging
 40-Lead TSOP
 44-Lead PSOP: JEDEC ROM
Compatible
 48-Lead TSOP
Absolute Hardware-Protection for Boot
Block
Footprint Upgradeable from 2-Mbit and
4-Mbit Boot Block Flash Memories
Software EEPROM Emulation with
Parameter Blocks
ETOX™ IV Flash Technology
SRAM-Compatible Write Interface
Extended Temperature Operation
 –40°C to +85°C
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION 1995
September 1995
Order Number: 290539-002
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
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CONTENTS
PAGE
1.0 PRODUCT FAMILY OVERVIEW . 3
1.1 New Features in the
SmartVoltage Products.....................3
1.2 Main Features................................... 4
1.3 Applications ..................................... 7
1.4 Pinouts..............................................8
1.5 Pin Descriptions .............................10
2.0 PRODUCT DESCRIPTION ........... 13
2.1 Memory Organization....................13
2.1.1 Blocking................................... 13
3.0 PRODUCT FAMILY PRINCIPLES
OF OPERATION............................. 12
3.1 Bus Operations...............................16
3.2 Read Operations.............................16
3.2.1 Read Array...............................16
3.2.2 Intelligent Identifiers................14
3.3 Write Operations ............................19
3.3.1 Command User Interface.......... 19
3.3.2 Status Register..........................17
3.3.3 Program Mode..........................18
3.3.4 Erase Mode ..............................27
3.4 Boot Block Locking.......................19
3.4.1 VPP = VIL for Complete
Protection.................................. 28
3.4.2 WP# = VIL for Boot Block
Locking..................................... 28
3.4.3 RP# = VHH or WP# = VIH for
Boot Block Unlocking..............29
2
PAGE
3.5 Power Consumption....................... 33
3.5.1 Active Power............................ 33
3.5.2 Automatic Power Savings........ 33
3.5.3 Standby Power......................... 33
3.5.4 Deep Power-Down Mode......... 33
3.6 Power-Up/Down Operation............ 34
3.6.1 RP# Connected to System Reset34
3.6.2 VCC, VPP and RP# Transtions ... 34
3.7 Power Supply Decoupling.............. 34
3.7.1 VPP Trace on Printed Circuit
Boards ...................................... 35
4.0 ABSOLUTE MAXIMUM RATINGS 36
5.0 COMMERCIAL OPERATING
CONDITIONS ................................. 37
5.1 Applying VCC Voltages .................. 37
5.2 DC Characteristics.......................... 38
5.3 AC Characteristics.......................... 32
6.0 EXTENDED OPERATING
CONDITIONS ................................. 57
6.1 Applying VCC Voltages .................. 57
6.2 DC Characteristics.......................... 58
6.3 AC Characteristics.......................... 67
7.0 ADDITIONAL INFORMATION ... 75
7.1 Ordering Information..................... 75
7.2 References...................................... 77
7.3 Revision History ............................ 77
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
1.0
PRODUCT FAMILY
OVERVIEW
This datasheet contains the specifications
for the two branches of products in the
SmartVoltage 8-Mbit boot block flash
memory family: the -BE/CE suffix
products feature a low VCC operating range
of 2.7–3.6V; the -BV/CV suffix products
offer
3.0–3.6V operation. Both BE/CE and
BV/CV products also operate at 5V for
high-speed access times. Throughout this
datasheet, the 28F800 refers to all x8/x16
8-Mbit products, while 28F008B refers to
all x8 8-Mbit boot block products (but not
to the 28F008SA FlashFile™ Memory).
Also, the term “2.7V” generally means the
full voltage range 2.7–3.6V. Section 1
provides an overview of the flash memory
family including applications, pinouts and
pin descriptions. Sections 2 and 3 describe
the memory organization and operation for
these products. Finally, Sections 4, 5 and 6
contain the family’s operating
specifications.
1.1
New Features in the
SmartVoltage Products
The new 8-Mbit SmartVoltage boot block
flash memory family provides a
convenient density upgrade path from the
2-Mbit and 4-Mbit boot block products.
The 8-Mbit boot block functions similarly
to lower density boot block products in
both command sets and operation,
providing similar pinouts to ease density
upgrades.
PRODUCT PREVIEW
To upgrade from lower density -BX/BLsuffix 12V program products, please note
the following differences and guidelines:
•
WP# pin has replaced DU (Don’t Use)
pin #12 in the 40-lead TSOP package.
In the 44-lead PSOP, DU pin #2 is
replaced with A18 (see Figure 1 and
Section 3.4 for details). Connect the
WP# pin to control signal or to VCC or
GND (in this case, a logic-level signal
can be placed on DU pin #12 for 40lead TSOP). See Tables 2 and 9 to see
how the WP# pin works.
• 5V program/erase operation has been
added. If switching VPP for write
protection, switch to GND (not 5V) for
complete write protection. To take
advantage of 5V write-capability, allow
for connecting 5V to VPP and
disconnecting 12V from VPP line.
• Enhanced circuits optimize low VCC
performance, allowing operation down
to VCC = 2.7V (using the BE/CE
products).
To upgrade from lower density
SmartVoltage boot block products, the
similar pinouts in the 40-lead and 48-lead
TSOP packages provide easy upgrades by
adding extra address lines (see Figures1
and 3). In the 44-lead TSOP, the WP# pin
on the 2-Mbit and 4-Mbit BV parts
becomes A18, removing the capability to
unlock the boot block with a logic-level
signal in this package only. The boot block
can still be unlocked with 12V on RP# (see
Figure 2 and Section 3.4 for details).
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 1. SmartVoltage Provides Total Voltage Flexibility
4
Product
Name
Bus
Width
28F008BVT/B
x8
√
√
√
√
28F800BVT/B
x8 or x16
√
√
√
√
28F800CVT/B
x8 or x16
√
√
√
√
28F008BET/B
x8
√
√
√
√
28F800CET/B
x8 or x16
√
√
√
√
2.7–3.6V
VCC
3.3 ± 0.3V
5V ± 5%
5V ± 10%
VPP
5 ± 10%V 12 ± 5%V
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
1.2
Main Features
Intel’s SmartVoltage technology is the most
flexible voltage solution in the flash
industry, providing two discrete voltage
supply pins: VCC for read operation, and VPP
for program and erase operation. Discrete
supply pins allow system designers to use
the optimal voltage levels for their design.
All products (28F800BV/CV, 28F008BV,
28F800CE and 28F008BE) provide
program/erase capability at 5V or 12V. The
28F800BV/CV and 28F008BV allows reads
with VCC at 3.3 ± 0.3V or 5V, while the
28F800CE and 28F008BE allows reads
with VCC at 2.7–3.6V or 5V. Since many
designs read from the flash memory a large
percentage of the time, 2.7V VCC operation
can provide great power savings. If read
performance is an issue, however, 5V VCC
provides faster read access times. For
program and erase operations, 5V VPP
operation eliminates the need for in system
voltage converters, while 12V VPP operation
provides faster program and erase for
situations where 12V is available, such as
manufacturing or designs where 12V is insystem. For design simplicity, however, just
hook up VCC and VPP to the same 5V ± 10%
source.
The 28F800/28F008B boot block flash
memory family is a high-performance,
8-Mbit (8,388,608 bit) flash memory family
organized as either
512 Kwords of 16 bits each (28F800 only)
or
1024 Kbytes of 8 bits each (28F800 and
28F008B).
Separately erasable blocks, including a
hardware-lockable boot block (16,384
bytes), two parameter blocks (8,192 bytes
each) and main blocks (one block of 98,304
bytes and seven blocks of 131,072 bytes)
define the boot block flash family
PRODUCT PREVIEW
architecture. See Figures 4 and 5 for
memory maps. Each block can be
independently erased and programmed
100,000 times at commercial temperature or
10,000 times at extended temperature.
The boot block is located at either the top
(denoted by -T suffix) or the bottom (-B
suffix) of the address map in order to
accommodate different microprocessor
protocols for boot code location. The
hardware-lockable boot block provides
complete code security for the kernel code
required for system initialization. Locking
and unlocking of the boot block is
controlled by WP# and/or RP# (see Section
3.4 for details).
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
The Command User Interface (CUI) serves
as the interface between the microprocessor
or microcontroller and the internal
operation of the boot block flash memory
products. The internal Write State Machine
(WSM) automatically executes the
algorithms and timings necessary for
program and erase operations, including
verifications, thereby unburdening the
microprocessor or microcontroller of these
tasks. The Status Register (SR) indicates the
status of the WSM and whether it
successfully completed the desired program
or erase operation.
Program and erase automation allows
program and erase operations to be
executed using an industry-standard twowrite command sequence to the CUI. Data
writes are performed in word (28F800
family) or byte (28F800 or 28F008B
families) increments. Each byte or word in
the flash memory can be programmed
independently of other memory locations,
unlike erases, which erase all locations
within a block simultaneously.
The 8-Mbit SmartVoltage boot block flash
memory family is also designed with an
Automatic Power Savings (APS) feature
which minimizes system battery current
drain, allowing for very low power designs.
To provide even greater power savings, the
boot block family includes a deep powerdown mode which minimizes power
consumption by turning most of the flash
memory’s circuitry off. This mode is
controlled by the RP# pin and its usage is
discussed in Section 3.5, along with other
power consumption issues.
Additionally, the RP# pin provides
protection against unwanted command
writes due to invalid system bus conditions
that may occur during system reset and
power-up/down sequences. For example,
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when the flash memory powers-up, it
automatically defaults to the read array
mode, but during a warm system reset,
where power continues uninterrupted to the
system components, the flash memory
could remain in a non-read mode, such as
erase. Consequently, the system Reset
signal should be tied to RP# to reset the
memory to normal read mode upon
activation of the Reset signal (see Section
3.6).
The 28F800 provides both byte-wide or
word-wide input/output, which is
controlled by the BYTE# pin. Please see
Table 2 and Figure 13 for a detailed
description of BYTE# operations,
especially the usage of the DQ15/A–1 pin.
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
The 28F800 products are available in the
44-lead PSOP (Plastic Small Outline)
package (a ROM/EPROM-compatible
pinout) and the 48-lead TSOP (Thin Small
Outline, 1.2 mm thick) package as shown in
Figures 2, and 3, respectively. The 28F800
is not available in 56-lead TSOP. The
28F008B products are available in the 40lead TSOP package as shown in Figure1.
Refer to the DC Characteristics Table,
Section 5.2 (commercial temperature)
and Section 6.2 (extended temperature),
for complete current and voltage
specifications. Refer to the AC
Characteristics Table, Section 5.3
(commercial temperature) and Section
6.3 (extended temperature), for read,
write and erase performance
specifications.
1.3
Applications
The 8-Mbit boot block flash memory family
combines high-density, low-power, highperformance, cost-effective flash memories
with blocking and hardware protection
capabilities. Their flexibility and versatility
reduce costs throughout the product life
cycle. Flash memory is ideal for just-intime production flow, reducing system
inventory and costs, and eliminating
component handling during the production
phase.
When your product is in the end-user’s
hands, and updates or feature enhancements
become necessary, flash memory reduces
the update costs by allowing userperformed code changes instead of costly
product returns or technician calls.
PRODUCT PREVIEW
The 8-Mbit boot block flash memory family
provides full-function, blocked flash
memories suitable for a wide range of
applications. These applications include
ROM-able applications storage, digital
cellular phone program and data storage,
telecommunication boot/firmware, printer
firmware/font storage and various other
embedded applications where program and
data storage are required.
The 8-Mbit flash memory products are also
excellent design solutions for digital
cellular phone and telecommunication
switching applications requiring very low
power consumption, high-performance,
high-density storage capability, modular
software designs, and a small form factor
package. The 8-Mbit’s blocking scheme
allows for easy segmentation of the
embedded code with
16 Kbytes of hardware-protected boot code,
eight main blocks of program code and two
parameter blocks of 8 Kbytes each for
frequently updated data storage and
diagnostic messages (e.g., phone numbers,
authorization codes).
Intel’s boot block architecture provides a
flexible solution for the different design
needs of various applications. The
asymmetrically-blocked memory map
allows the integration of several memory
components into a single flash device. The
boot block provides a secure boot PROM;
the parameter blocks can emulate EEPROM
functionality for parameter store with
proper software techniques; and the main
blocks provide code and data storage with
access times fast enough to execute code in
place, decreasing RAM requirements.
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
1.4
Pinouts
Intel’s SmartVoltage Boot Block
architecture provides pinout upgrade paths
to the 8-Mbit density. 8-Mbit pinouts are
given on the chip illustration in the center,
with 2-Mbit and 4-Mbit pinouts going
outward from the center for reference.
28F004B
A 16
A 15
A 14
A 13
A 12
A 11
A9
A8
WE#
RP#
VPP
WP#
A 18
A7
A6
A5
A4
A3
A2
A1
The 28F008B 40-lead TSOP pinout for
space-constrained designs is shown in
Figure 1. For designs that require x16
operation but have space concerns, refer to
the 48-lead pinout in Figure 3. The 28F800
44-lead PSOP pinout follows the industrystandard ROM/EPROM pinout, as shown in
Figure 2.
28F002B
A 16
A 15
A 14
A 13
A 12
A 11
A9
A8
WE#
RP#
VPP
W P#
NC
A7
A6
A5
A4
A3
A2
A1
28F002B
A 16
A 15
A 14
A 13
A 12
A 11
A9
A8
WE#
RP#
VPP
WP#
A 18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28F008B
40-LEAD TSOP
Boot Block
10 mm x 20 mm
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A 17
GND
NC
A 19
A 10
DQ 7
DQ 6
DQ 5
DQ 4
VCC
VCC
NC
DQ 3
DQ 2
DQ 1
DQ 0
OE#
GND
CE#
A0
A 17
GND
NC
NC
A 10
DQ 7
DQ 6
DQ 5
DQ 4
VCC
VCC
NC
DQ 3
DQ 2
DQ 1
DQ 0
OE#
GND
CE#
A0
28F004B
A 17
GND
NC
NC
A 10
DQ 7
DQ 6
DQ 5
DQ 4
VCC
VCC
NC
DQ 3
DQ 2
DQ 1
DQ 0
OE#
GND
CE#
A0
0539_01
NOTE:
1. Pin 12 is DU for -BX/BL 12V VPP Versions.
2. The 28F008B pinout is for the 8-Mbit boot block and not for the 28F008SA FlashFile™ Memory.
Figure 1. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained
Applications
8
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
28F400
28F200
V PP
VPP
WP#
A 17
A7
A6
A5
A4
A3
A2
A1
A0
WP#
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE#
GND
OE#
VPP
A 18
A 17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
GND
OE#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CE#
GND
OE#
DQ 0
DQ 8
DQ 1
DQ 9
DQ 2
DQ 10
DQ 3
DQ 11
0
8
1
9
2
10
3
11
0
8
1
9
2
10
3
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PA28F800
Boot Block
44-LEAD PSOP
0.525" x 1.110"
TOP VIEW
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP#
WE#
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
BYTE#
GND
DQ 15 /A -1
DQ 7
DQ 14
DQ 6
DQ 13
DQ 5
DQ 12
DQ 4
V CC
28F200
28F400
RP#
WE#
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
RP#
WE#
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
BYTE#
GND
DQ 15 /A -1
DQ 7
DQ 14
DQ 6
DQ 13
DQ 5
DQ 12
DQ 4
V CC
BYTE#
GND
DQ 15 /A -1
DQ 7
DQ 14
DQ 6
DQ 13
DQ 5
DQ 12
DQ 4
V CC
0539_02
NOTE:
Pin 2 is DU for BX/BL 12V VPP Versions, but for the 8-Mbit device, pin 2 has been changed to A18 (WP# on 2/4 Mbit). Designs
planning on upgrading to the 8-Mbit density from the 2/4-Mbit density in this package should design pin 2 to control WP# functionality
at the 2/4-Mbit level and allow for pin 2 to control A18 after upgrading to the 8-Mbit density.
Figure 2. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM
Standards
28F200
28F400
A16
A 16
BYTE#
GND
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ 4
BYTE#
GND
DQ15 /A -1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
A 16
BYTE#
GND
DQ15 /A -1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ 0
OE#
GND
CE#
A0
28F400 28F200
A 15
A 14
A 13
A 12
A 11
A 10
A9
A8
NC
NC
WE#
RP#
VPP
WP#
NC
NC
A 17
A7
A6
A5
A4
A3
A2
A1
A 15
A 14
A 13
A 12
A 11
A 10
A9
A8
NC
NC
WE#
RP#
A 15
A 14
A 13
A 12
A 11
A 10
A9
A8
NC
NC
WE#
RP#
VPP
VPP
WP#
NC
NC
NC
WP#
NC
A 18
A 17
A7
A6
A5
A4
A3
A2
A1
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28F800C
Boot Block
48-LEAD TSOP
12 mm x 20 mm
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ 0
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ 0
A0
A0
OE#
GND
CE#
OE#
GND
CE#
0539_03
Figure 3. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
1.5
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Pin Descriptions
Table 2. 28F800/008B Pin Descriptions
Symbol
Type
Name and Function
A0–A19
INPUT
ADDRESS INPUTS for memory addresses. Addresses are
internally latched during a write cycle.The 28F800 only has
A0–A18 pins, while
the 28F008B has A 0–A19.
A9
INPUT
ADDRESS INPUT: When A9 is at VHH the signature mode is
accessed. During this mode, A0 decodes between the
manufacturer and device IDs. When BYTE# is at a logic low,
only the lower byte of the signatures are read. DQ15/A–1 is a
don’t care in the signature mode when BYTE# is low.
DQ0–
DQ7
INPUT/OUT
PUT
DATA INPUTS/OUTPUTS: Inputs array data on the second
CE# and WE# cycle during a Program command. Inputs
commands to the Command User Interface when CE# and
WE# are active. Data is internally latched during the Write
cycle. Outputs array, Intelligent Identifier and Status Register
data. The data pins float to tri-state when the chip is deselected or the outputs are disabled.
DQ8–
DQ15
INPUT/OUT
PUT
DATA INPUTS/OUTPUTS: Inputs array data on the second
CE# and WE# cycle during a Program command. Data is
internally latched during the Write cycle. Outputs array data.
The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# =
“0”). In the byte-wide mode DQ15/A–1 becomes the lowest
order address for data output on DQ0–DQ7. The 28F008B
does not include these DQ 8–DQ15 pins.
CE#
INPUT
CHIP ENABLE: Activates the device’s control logic, input
buffers, decoders and sense amplifiers. CE# is active low.
CE# high de-selects the memory device and reduces power
consumption to standby levels. If CE# and RP# are high, but
not at a CMOS high level, the standby current will increase
due to current flow through the CE# and RP# input stages.
OE#
INPUT
OUTPUT ENABLE: Enables the device’s outputs through
the data buffers during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command Register
and array blocks. WE# is active low. Addresses and data are
latched on the rising edge of the WE# pulse.
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RP#
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
INPUT
RESET/DEEP POWER-DOWN: Uses three voltage levels
(VIL, VIH, and VHH) to control two different functions:
reset/deep power-down mode and boot block unlocking. It is
backwards-compatible with the BX/BL/BV products.
When RP# is at logic low, the device is in reset/deep
power-down mode, which puts the outputs at High-Z, resets
the Write State Machine, and draws minimum current.
When RP# is at logic high, the device is in standard
operation. When RP# transitions from logic-low to logichigh, the device defaults to the read array mode.
When RP# is at V HH, the boot block is unlocked and can be
programmed or erased. This overrides any control from the
WP# input.
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
E
Table 2. 28F800/008B Pin Descriptions (Continued)
Symbol
WP#
Type
INPUT
Name and Function
WRITE PROTECT: Provides a method for unlocking the
boot block in a system without a 12V supply.
When WP# is at logic low, the boot block is locked ,
preventing program and erase operations to the boot block. If
a program or erase operation is attempted on the boot block
when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the Status Register to
indicate the operation failed.
When WP# is at logic high, the boot block is unlocked and
can be programmed or erased.
NOTE: This feature is overridden and the boot block
unlocked when RP# is at VHH. This pin is not available on the
44-lead PSOP package. See Section 3.4 for details on write
protection.
BYTE#
INPUT
BYTE# ENABLE: Not available on 28F008B. Controls
whether the device operates in the byte-wide mode (x8) or
the word-wide mode (x16). BYTE# pin must be controlled at
CMOS levels to meet the CMOS current specification in the
standby mode.
When BYTE# is at logic low, the byte-wide mode is
enabled, where data is read and programmed on DQ0–DQ7
and DQ15/A–1 becomes the lowest order address that decodes
between the upper and lower byte. DQ8–DQ14 are tri-stated
during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is
enabled, where data is read and programmed on DQ0–DQ15.
VCC
DEVICE POWER SUPPLY: 5.0V ± 10%, 3.3V ± 0.3V,
2.7V–3.6V
VPP
PROGRAM/ERASE POWER SUPPLY: For erasing
memory array blocks or programming data in each block, a
voltage either of 5V ± 10% or 12V ± 5% must be applied to
this pin. When VPP < VPPLK all blocks are locked and
protected against Program and Erase commands.
GND
GROUND: For all internal circuitry.
12
PRODUCT PREVIEW
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NC
2.0
2.1
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
NO CONNECT: Pin may be driven or left floating.
PRODUCT DESCRIPTION
Memory Organization
2.1.1
BLOCKING
This product family features an
asymmetrically- blocked architecture
providing system memory integration. Each
erase block can be erased independently of
the others up to 100,000 times for
commercial temperature or up to 10,000
times for extended temperature. The block
sizes have been chosen to optimize their
functionality for common applications of
nonvolatile storage. The combination of
block sizes in the boot block architecture
allow the integration of several memories
into a single chip. For the address locations
of the blocks, see the memory maps in
Figures 4 and 5.
2.1.1.2
Parameter Blocks - 2 x 8 KB
The boot block architecture includes
parameter blocks to facilitate storage of
frequently updated small parameters that
would normally require an EEPROM. By
using software techniques, the byte-rewrite
functionality of EEPROMs can be
emulated. These techniques are detailed in
Intel’s AP-604,
2.1.1.1
Boot Block - 1 x 16 KB
The boot block is intended to replace a
dedicated boot PROM in a microprocessor
or microcontroller-based system. The 16Kbyte (16,384 bytes) boot block is located
at either the top (denoted by -T suffix) or
the bottom (-B suffix) of the address map to
accommodate different microprocessor
protocols for boot code location. This boot
block features hardware controllable writeprotection to protect the crucial
microprocessor boot code from accidental
modification. The protection of the boot
block is controlled using a combination of
the VPP, RP#, and WP# pins, as is detailed
in Section 3.4.
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
“Using Intel’s Boot Block Flash Memory
Parameter Blocks to Replace EEPROM.”
Each boot block component contains two
parameter blocks of
8 Kbytes (8,192 bytes) each. The parameter
blocks are not write-protectable.
2.1.1.3
Main Blocks - 1 x 96 KB + 7 x
128 KB
After the allocation of address space to the
boot and parameter blocks, the remainder is
divided into main blocks for data or code
storage. Each 8-Mbit device contains one
96-Kbyte (98,304 byte) block and seven
128-Kbyte (131,072 byte) blocks. See the
memory maps for each device for more
information.
28F800-B
28F800-T
7FFFFH
7FFFFH
128-Kbyte MAIN BLOCK
70000H
6FFFFH
128-Kbyte MAIN BLOCK
60000H
5FFFFH
16-Kbyte BOOT BLOCK
7E000H
7DFFFH
7D000H
7CFFFH
7C000H
7BFFFH
70000H
6FFFFH
128-Kbyte MAIN BLOCK
60000H
5FFFFH
128-Kbyte MAIN BLOCK
50000H
4FFFFH
128-Kbyte MAIN BLOCK
40000H
3FFFFH
128-Kbyte MAIN BLOCK
30000H
2FFFFH
96-Kbyte MAIN BLOCK
20000H
1FFFFH
128-Kbyte MAIN BLOCK
40000H
3FFFFH
128-Kbyte MAIN BLOCK
30000H
2FFFFH
128-Kbyte MAIN BLOCK
20000H
1FFFFH
128-Kbyte MAIN BLOCK
10000H
0FFFFH
00000H
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
50000H
4FFFFH
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
8-Kbyte PARAMETER BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
10000H
0FFFFH
128-Kbyte MAIN BLOCK
16-Kbyte BOOT BLOCK
00000H
0539_04
NOTE:
In x8 operation, the least significant system address should be connected to A
–1. Memory maps are shown for x16 operation.
Figure 4. Word-Wide x16-Mode Memory Maps
14
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
28F800-T
FFFFFH
28F800-B
FFFFFH
16-Kbyte BOOT BLOCK
FC000H
FBFFFH
FA000H
F9FFFH
F8000H
F7FFFH
8-Kbyte PARAMETER BLOCK
128-Kbyte MAIN BLOCK
E0000H
DFFFFH
8-Kbyte PARAMETER BLOCK
128-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
C0000H
BFFFFH
128-Kbyte MAIN BLOCK
A0000H
9FFFFH
128-Kbyte MAIN BLOCK
80000H
7FFFFH
128-Kbyte MAIN BLOCK
60000H
5FFFFH
128-Kbyte MAIN BLOCK
40000H
3FFFFH
128-Kbyte MAIN BLOCK
20000H
1FFFFH
E0000H
DFFFFH
128-Kbyte MAIN BLOCK
C0000H
BFFFFH
128-Kbyte MAIN BLOCK
A0000H
9FFFFH
128-Kbyte MAIN BLOCK
80000H
7FFFFH
128-Kbyte MAIN BLOCK
60000H
5FFFFH
128-Kbyte MAIN BLOCK
40000H
3FFFFH
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
20000H
1FFFFH
128-Kbyte MAIN BLOCK
08000H
07FFFH
06000H
05FFFH
04000H
03FFFH
00000H
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
00000H
0539_05
NOTE:
These memory maps apply to the 28F008B or the 28F800 (in x8 mode).
Figure 5. Byte-Wide x8-Mode Memory Maps
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
3.0
PRODUCT FAMILY
PRINCIPLES OF OPERATION
Flash memory combines EPROM
functionality with in-circuit electrical write
and erase. The boot block flash family
utilizes a Command User Interface (CUI)
and automated algorithms to simplify write
and erase operations. The CUI allows for
100% TTL-level control inputs, fixed power
supplies during erasure and programming,
and maximum EPROM compatibility.
When VPP < VPPLK, the device will only
successfully execute the following
commands: Read Array, Read Status
Register, Clear Status Register and
intelligent identifier mode. The device
provides standard EPROM read, standby
and output disable operations. Manufacturer
identification and device identification data
can be accessed through the CUI or through
the standard EPROM A9 high voltage
access (VID) for PROM programming
equipment.
The same EPROM read, standby and output
disable functions are available when 5V or
12V is applied to the VPP pin. In addition,
5V or 12V on VPP allows write and erase of
the device. All functions associated with
altering memory contents: Program and
Erase, Intelligent Identifier Read, and Read
Status are accessed via the CUI.
The internal Write State Machine (WSM)
completely automates program and erase,
beginning operation signaled by the CUI
and reporting status through the Status
Register. The CUI handles the WE#
interface to the data and address latches, as
well as system status requests during WSM
operation.
16
E
3.1
Bus Operations
Flash memory reads, erases and writes insystem via the local CPU. All bus cycles to
or from the flash memory conform to
standard microprocessor bus cycles. These
bus operations are summarized in Tables 3
and 4.
3.2
Read Operations
3.2.1
READ ARRAY
When RP# transitions from VIL (reset) to
VIH, the device will be in the read array
mode and will respond to the read control
inputs (CE#, address inputs, and OE#)
without any commands being written to the
CUI.
When the device is in the read array mode,
five control signals must be controlled to
obtain data at the outputs.
•
WE# must be logic high (VIH)
• CE# must be logic low (VIL)
• OE must be logic low (VIL)
• RP# must be logic high (VIH)
• BYTE# must be logic high or logic low.
In addition, the address of the desired
location must be applied to the address
pins. Refer to Figures 12 and 13 for the
exact sequence and timing of these signals.
If the device is not in read array mode, as
would be the case after a program or erase
operation, the Read Mode command (FFH)
must be written to the CUI before reads can
take place.
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Table 3. Bus Operations for Word-Wide Mode (BYTE# = V IH)
Mode
Note
s
RP#
CE#
OE#
WE#
A9
A0
VPP
DQ0–15
1,2,3
VIH
VIL
VIL
VIH
X
X
X
DOUT
Output Disable
VIH
VIL
VIH
VIH
X
X
X
High Z
Standby
VIH
VIH
X
X
X
X
X
High Z
Read
Deep PowerDown
9
VIL
X
X
X
X
X
X
High Z
Intelligent
Identifier (Mfr.)
4
VIH
VIL
VIL
VIH
VID
VIL
X
0089 H
4,5
VIH
VIL
VIL
VIH
VID
VIH
X
See
Table 5
6,7,8
VIH
VIL
VIH
VIL
X
X
X
DIN
Intelligent
Identifier
(Device)
Write
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 4. Bus Operations for Byte-Wide Mode (BYTE# = V IL)
Mode
Note
s
RP# CE# OE
#
WE
#
A9
1,2,3
VIH
VIL
VIL
VIH
X
X
X
X
DOUT
High
Z
Output
Disable
VIH
VIL
VIH
VIH
X
X
X
X
High
Z
High
Z
Standby
VIH
VIH
X
X
X
X
X
X
High
Z
High
Z
Read
A0
A–1
VPP
DQ0–7
DQ8–
14
Deep
PowerDown
9
VIL
X
X
X
X
X
X
X
High
Z
High
Z
Intelligent
Identifier
(Mfr.)
4
VIH
VIL
VIL
VIH
VID
VIL
X
X
89H
High
Z
Intelligent
Identifier
(Device)
4,5
VIH
VIL
VIL
VIH
VID
VIH
X
X
See
Table
6
High
Z
6,7,8
VIH
VIL
VIH
VIL
X
X
X
X
DIN
High
Z
Write
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for VPP.
3. See DC Characteristics for VPPLK, VPPH1, VPPH2, VHH, VID voltages
4. Manufacturer and device codes may also be accessed via a CUI write sequence, A
1–A18 = X, A1–A19 = X.
5. See Table 5 for device IDs.
6. Refer to Table 7 for valid DIN during a write operation.
7. Command writes for Block Erase or Word/Byte Write are only executed when V
PP = VPPH1 or VPPH2.
8. To write or erase the boot block, hold RP# at VHH or WP# at VIH. See Section 3.4.
9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
18
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
3.2.2
INTELLIGENT IDENTIFIERS
To read the manufacturer and device codes,
the device must be in intelligent identifier
read mode, which can be reached using two
methods: by writing the intelligent identifier
command (90H) or by taking the A9 pin to
VID. Once in intelligent identifier read
mode, A0 = 0 outputs the manufacturer’s
identification code and A0 = 1 outputs the
device code. In byte-wide mode, only the
lower byte of the above signatures is read
(DQ15/A–1 is a “don’t care” in this mode).
See Table 5 for product signatures. To
return to read array mode, write a Read
Array command (FFH).
Table 5. Intelligent Identifier Table
Produc
t
Mfr.
ID
Device ID
-T
(Top
Boot)
-B
(Bottom
Boot)
28F800
0089
H
889C H
889D H
28F008
B
89 H
9C H
9D H
3.3
Write Operations
3.3.1
COMMAND USER
INTERFACE (CUI)
The Command User Interface (CUI) is the
interface between the microprocessor and
the internal chip controller. Commands are
written to the CUI using standard
microprocessor write timings. The available
commands are Read Array, Read Intelligent
Identifier, Read Status Register, Clear
Status Register, Erase and Program
(summarized in Tables 6 and 7). The three
read modes are read array, intelligent
identifier read, and Status Register read. For
Program or Erase commands, the CUI
informs the Write State Machine (WSM)
that a write or erase has been requested.
During the execution of a Program
command, the WSM will control the
programming sequences and the CUI will
only respond to status reads. During an
erase cycle, the CUI will respond to status
reads and erase suspend. After the WSM
has completed its task, it will set the WSM
Status bit to a “1” (ready), which indicates
that the CUI can respond to its full
command set. Note that after the WSM has
returned control to the CUI, the CUI will
stay in the current command state until it
receives another command.
3.3.1.1
Command Function
Description
Device operations are selected by writing
specific commands into the CUI. Tables6
and 7 define the available commands.
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Table 6. Command Codes and Descriptions
Code Device Mode
Description
00
Invalid/
Reserved
Unassigned commands that should not be used. Intel reserves the
right to redefine these codes for future functions.
FF
Read Array/
Program or
Erase Abort
Places the device in read array mode, so that array data will be
output on the data pins. This command can also be used to cancel
erase and program sequences after their set-up commands have been
issued. To cancel after issuing an Erase Set-Up command, issue this
command, which will reset to read array mode. To cancel a program
operation after issuing a Program Set-Up command, issue two Read
Array commands in sequence to reset to read array mode. If a
program or erase operation has already been initiated to the WSM
this command can not cancel that operation in progress.
40
Program
Set-Up
Sets the CUI into a state such that the next write will load the
Address and Data registers. After this command is executed, the
outputs default to the Status Register. Atwo Read Array command
sequence (FFH) is required to reset to Read Array after the Program
Set-Up command.
The second write after the Program Set-Up command will latch
addresses and data, initiating the WSM to begin execution of the
program algorithm. The device outputs Status Register data when
OE# is enabled. A Read Array command is required after
programming, to read array data. See Section 3.3.3.
10
Alternate
(See 40H/Program Set-Up)
Program SetUp
20
Erase
Set-Up
Prepares the CUI for the Erase Confirm command. If the next
command is not an Erase Confirm command, then the CUI will set
both the Program Status and Erase Status bits of the Status Register
to a “1,” place the device into the read Status Register state, and
wait for another command. See Section 3.3.4.
D0
Erase
Resume/
Erase
Confirm
If the previous command was an Erase Set-Up command, then the
CUI will close the address and data latches, and begin erasing the
block indicated on the address pins. During erase, the device will
respond only to the Read Status Register and Erase Suspend
commands and will output Status Register data when OE# is
toggled low. Status Register data can be updated by toggling either
20
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 6. Command Codes and Descriptions
Code Device Mode
Description
OE# or CE# low.
B0
Erase
Suspend
Valid only while an erase operation is in progress and will be
ignored in any other circumstance. Issuing this command will begin
to suspend erase operation. The Status Register will indicate when
the device reaches erase suspend mode. In this mode, the CUI will
respond only to the Read Array, Read Status Register, and Erase
Resume commands and the WSM will also set the WSM Status bit
to a “1” (ready). The WSM will continue to idle in the SUSPEND
state, regardless of the state of all input control pins except RP#,
which will immediately shut down the WSM and the remainder of
the chip, if it is made active. During a suspend operation, the data
and address latches will remain closed, but the address pads are able
to drive the address into the read path. See Section 3.3.4.1.
70
Read Status
Register
Puts the device into the read Status Register mode, so that reading
the device will output the contents of the Status Register, regardless
of the address presented to the device. The device automatically
enters this mode after program or erase has completed. This is one
of the two commands that is executable while the WSM is
operating. See Section 3.3.2.
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 6. Command Codes and Descriptions (Continued)
Code Device Mode
50
Clear Status
Register
Description
The WSM can only set the Program Status and Erase Status bits in
the Status Register to “1,” it cannot clear them to “0.”
The Status Register operates in this fashion for two reasons. The
first is to give the host CPU the flexibility to read the status bits at
any time. Second, when programming a string of bytes, a single
Status Register query after programming the string may be more
efficient, since it will return the accumulated error status of the
entire string. See Section 3.3.2.1.
90
Intelligent
Identifier
Puts the device into the intelligent identifier read mode, so that
reading the device will output the manufacturer and device codes.
(A0 = 0 for manufacturer,
A0 = 1 for device, all other address inputs are ignored). See Section
3.2.2.
Table 7. Command Bus Definitions
Command
Note
First Bus Cycle
Oper Addr
Data
Second Bus Cycle
Oper
Addr
Data
Read Array
8
Write
X
FFH
Intelligent Identifier
1
Write
X
90H
Read
IA
IID
Read Status Register
2,4
Write
X
70H
Read
X
SRD
Clear Status Register
3
Write
X
50H
Write
WA
40H
Write
WA
WD
Word/Byte Write
Alternate Word/Byte
Write
6,7
Write
WA
10H
Write
WA
WD
Block Erase/Confirm
6,7
Write
BA
20H
Write
BA
D0H
Write
X
B0H
Write
X
D0H
Erase Suspend/Resume
ADDRESS
BA= Block Address
IA= Identifier Address
WA= Write Address
X= Don’t Care
5
DATA
SRD= Status Register Data
IID= Identifier Data
WD= Write Data
NOTES:
22
PRODUCT PREVIEW
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1.
2.
3.
4.
5.
6.
7.
8.
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Bus operations are defined in Tables3 and 4.
IA = Identifier Address: A0 = 0 for manufacturer code, A0 = 1 for device code.
SRD - Data read from Status Register.
IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and device
codes.
BA = Address within the block being erased.
WA = Address to be written. WD = Data to be written at location WD.
Either 40H or 10H commands is valid.
When writing commands to the device, the upper data bus [DQ
8–DQ15] = X (28F800 only) which is either VIL or VIH, to minimize
current draw.
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 8. Status Register Bit Definition
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 WRITE STATE MACHINE
STATUS
1 = Ready
(WSMS)
0 = Busy
Check Write State Machine bit first to
determine Word/Byte program or Block
Erase completion, before checking
Program or Erase Status bits.
SR.6 = ERASE-SUSPEND STATUS
(ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM
halts execution and sets both WSMS and
ESS bits to “1.” ESS bit remains set to “1”
until an Erase Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” WSM has
applied the max number of erase pulses to
the block and is still unable to verify
successful block erasure.
SR.4 = PROGRAM STATUS (DWS)
1 = Error in Byte/Word Program
0 = Successful Byte/Word Program
When this bit is set to “1,” WSM has
attempted but failed to program a byte or
word.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation
Abort
0 = VPP OK
The VPP Status bit does not provide
continuous indication of VPP level. The
WSM interrogates VPP level only after the
Byte Write or Erase command sequences
have been entered, and informs the system
if VPP has not been switched on. The VPP
Status bit is not guaranteed to report
accurate feedback between VPPLK and
VPPH.
SR.2-SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
These bits are reserved for future use and
should be masked out when polling the
Status Register.
3.3.2
STATUS REGISTER
The device Status Register indicates when a
program or erase operation is complete, and
the success or failure of that operation. To
read the Status Register write the Read
24
Status (70H) command to the CUI. This
causes all subsequent read operations to
output data from the Status Register until
another command is written to the CUI. To
return to reading from the array, issue a
Read Array (FFH) command.
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The Status Register bits are output on DQ0–
DQ7, in both byte-wide (x8) or word-wide
(x16) mode. In the word-wide mode the
upper byte, DQ8–DQ15, outputs 00H during
a Read Status command. In the byte-wide
mode, DQ8–DQ14 are tri-stated and DQ15/A–
1 retains the low order address function.
Important: The contents of the Status
Register are latched on the falling edge of
OE# or CE#, whichever occurs last in the
read cycle. This prevents possible bus
errors which might occur if Status Register
contents change while being read. CE# or
OE# must be toggled with each subsequent
status read, or the Status Register will not
indicate completion of a program or erase
operation.
When the WSM is active, the SR.7 register
will indicate the status of the WSM, and
will also hold the bits indicating whether or
not the WSM was successful in performing
the desired operation.
3.3.2.1
Clearing the Status Register
The WSM sets status bits 3 through 7 to
“1,” and clears bits 6 and 7 to “0,” but
cannot clear status bits 3 through 5 to “0.”
Bits 3 through 5 can only be
PRODUCT PREVIEW
25
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
cleared by the controlling CPU through the
use of the Clear Status Register (50H)
command, because these bits indicate
various error conditions. By allowing the
system software to control the resetting of
these bits, several operations may be
performed (such as cumulatively
programming several bytes or erasing
multiple blocks in sequence) before reading
the Status Register to determine if an error
occurred during that series. Clear the Status
Register before beginning another
command or sequence. Note, again, that a
Read Array command must be issued
before data can be read from the memory or
intelligent identifier.
E
When programming is complete, the
Program Status bits should be checked. If
the programming operation was
unsuccessful, bit 4 of the Status Register is
set to a “1” to indicate a Program Failure. If
bit 3 is set to a “1,” then VPP was not within
acceptable limits, and the WSM did not
execute the programming sequence.
3.3.3
PROGRAM MODE
Programming is executed using a two-write
sequence. The Program Setup command is
written to the CUI followed by a second
write which specifies the address and data
to be programmed. The WSM will execute
a sequence of internally timed events to:
1. Program the desired bits of the
addressed memory word or byte.
2. Verify that the desired bits are
sufficiently programmed.
Programming of the memory results in
specific bits within a byte or word being
changed to a “0.”
If the user attempts to program “1”s, there
will be no change of the memory cell
content and no error occurs.
The Status Register indicates programming
status: while the program sequence is
executing, bit 7 of the Status Register is a
“0.” The Status Register can be polled by
toggling either CE# or OE#. While
programming, the only valid command is
Read Status Register.
26
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
The Status Register should be cleared
before attempting the next operation. Any
CUI instruction can follow after
programming is completed; however, reads
from the Memory Array or Intelligent
Identifier cannot be accomplished until the
CUI is given the appropriate command.
Clear the Status Register before attempting
the next operation. Any CUI instruction can
follow after erasure is completed; however,
reads from the Memory Array, Status
Register, or Intelligent Identifier cannot be
accomplished until the CUI is given the
Read Array command.
3.3.4
ERASE MODE
To erase a block, write the Erase Set-Up
and Erase Confirm commands to the CUI,
along with the addresses identifying the
block to be erased. These addresses are
latched internally when the Erase Confirm
command is issued. Block erasure results in
all bits within the block being set to “1.”
Only one block can be erased at a time.
The WSM will execute a sequence of
internally timed events to:
1. Program all bits within the block to “0.”
2. Verify that all bits within the block are
sufficiently programmed to “0.”
3. Erase all bits within the block to “1.”
4. Verify that all bits within the block are
sufficiently erased.
While the erase sequence is executing, bit 7
of the Status Register is a “0.”
When the Status Register indicates that
erasure is complete, check the Erase Status
bit to verify that the erase operation was
successful. If the Erase operation was
unsuccessful, bit 5 of the Status Register
will be set to a “1,” indicating an Erase
Failure. If VPP was not within acceptable
limits after the Erase Confirm command is
issued, the WSM will not execute an erase
sequence; instead, bit 5 of the Status
Register is set to a “1” to indicate an Erase
Failure, and bit 3 is set to a “1” to identify
that VPP supply voltage was not within
acceptable limits.
PRODUCT PREVIEW
27
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
3.3.4.1
Suspending and Resuming
Erase
Since an erase operation requires on the
order of seconds to complete, an Erase
Suspend command is provided to allow
erase-sequence interruption in order to read
data from another block of the memory.
Once the erase sequence is started, writing
the Erase Suspend command to the CUI
requests that the WSM pause the erase
sequence at a predetermined point in the
erase algorithm. The Status Register will
indicate if/when the erase operation has
been suspended.
At this point, a Read Array command can
be written to the CUI in order to read data
from blocks other than that which is being
suspended. The only other valid command
at this time is the Erase Resume command
or Read Status Register command.
During erase suspend mode, the chip can go
into a pseudo-standby mode by taking CE#
to VIH, which reduces active current draw.
To resume the erase operation, enable the
chip by taking CE# to VIL, then issuing the
Erase Resume command, which continues
the erase sequence to completion. As with
the end of a standard erase operation, the
Status Register must be read, cleared, and
the next instruction issued in order to
continue.
E
3.4.1
VPP = VIL FOR COMPLETE
PROTECTION
For complete write protection of all blocks
in the flash device, the VPP programming
voltage can be held low. When VPP is below
VPPLK, any program or erase operation will
result in a error in the Status Register.
3.4
Boot Block Locking
The boot block family architecture features
a hardware-lockable boot block so that the
kernel code for the system can be kept
secure while the parameter and main blocks
are programmed and erased independently
as necessary. Only the boot block can be
locked independently from the other blocks.
28
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
3.4.2
WP# = V IL FOR BOOT BLOCK
LOCKING
When WP# = VIL, the boot block is locked
and any program or erase operation to the
boot block will result in an error in the
Status Register. All other blocks remain
unlocked in this condition and can be
programmed or erased normally. Note that
this feature is overridden and the boot block
unlocked when RP# = VHH. Since the WP#
pin is not available on the 44-lead PSOP
package, the boot block’s default status is
locked when RP# is at VIH or VIL. For the
44-lead PSOP, the boot block cannot be
unlocked with a logic-level signal; instead,
RP# must be taken to VHH as discussed in
Section 3.4.3 below.
3.4.3
RP# = V HH OR WP# = V IH FOR
BOOT BLOCK UNLOCKING
Two methods can be used to unlock the
boot block:
1. WP# = VIH
2. RP# = VHH
If both or either of these two conditions are
met, the boot block will be unlocked and
can be programmed or erased. Since the
PRODUCT PREVIEW
WP# pin is not available on the 44-lead
PSOP package, the boot block cannot be
unlocked with a logic-level signal on that
package. Instead, RP# must be taken to
VHH.
The truth table, Table 9, clearly defines the
write protection methods.
Table 9. Write Protection Truth Table for
SmartVoltage Boot Block Family
VPP
RP
#
WP
#
Write Protection
Provided
VIL
X
X
All Blocks Locked
≥
VPPLK
VIL
X
All Blocks Locked
(Reset)
≥
VPPLK
VHH
X
All Blocks
Unlocked
≥
VIH
VIL
Boot Block
Locked
VIH
VIH
All Blocks
Unlocked
VPPLK
≥
VPPLK
NOTE:
WP# pin not available on 44-lead PSOP. In this package, treat as
if the WP# pin is internally tied low, effectively eliminating the
last row of the above table.
29
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Start
Bus
Operation
W rite
Write 40H,
Word/Byte Address
Command
Comments
Setup
Program
Data = 40H
Addr = Word/Byte to Program
Program
Data = Data to Program
Addr = Location to Program
W rite
Write Word/Byte
Data/Address
Read
Status Register Data
Toggle CE# or OE#
to Update SRD.
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read
Status Register
NO
SR.7 = 1
?
Repeat for subsequent Word/Byte Writes.
SR Full Status Check can be done after each Word/Byte
Write, or after a sequence of Word/Byte Writes.
Write FFH after the last write operation to reset device to
read array mode.
YES
Full Status
Check if Desired
Word/Byte Program
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read Status Register
Data (See Above)
SR.3=
1
1
0
Word/Byte Program
Successful
Comments
Standby
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4
1 = VPP Byte Program Error
VPP Range Error
0
SR.4 =
Command
Word/Byte Program
Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State Machine.
SR.4 is only cleared by the Clear Status Register Command,
in cases where multiple bytes are programmed before full
status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0539_06
Figure 6. Automated Word/Byte Programming Flowchart
30
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Start
Bus
Operation
W rite
Write 20H,
Block Address
W rite
Write D0H and
Block Address
Command
Erase Setup
E rase
Confirm
Read
Read Status
Register
Suspend Erase
Loop
0
Suspend
Erase
Full Status
Check if Desired
Data = D0H
Addr = Within Block to be Erased
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
YES
1
Data = 20H
Addr = Within Block to be Erased
Status Register Data
Toggle CE# or OE#
to Update Status Register
NO
SR.7 =
Comments
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase,
or after a sequence of block erasures.
Write FFH after the last operation to reset device to read
array mode.
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read Status Register
Data (See Above)
SR.3 =
1
1
Comments
S tandby
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4,5
Both 1 = Command
Sequence Error
Standby
Check SR.5
1 = Block Erase Error
VPP Range Error
0
SR.4,5 =
Command
Command Sequence
Error
0
1
SR.5 =
SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
Block Erase
Error
0
SR.5 is only cleared by the Clear Status Register Command, in
cases where multiple blocks are erase before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Block Erase
Successful
0539_07
Figure 7. Automated Block Erase Flowchart
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Start
Bus
Operation
W rite
Write B0H
Command
Erase
S uspend
Status Register Data
Toggle CE# or OE#
to update SRD.
Addr = X
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.6
1 = Erase Suspended
0 = Erase Completed
0
1
W rite
CSR.6 =
0
Data = B0H
Addr = X
Read
Read
Status Register
SR.7 =
Comments
Read Array
Erase Completed
Read
Data = FFH
Addr = X
Read array data from block other
than the one being erased.
1
W rite
Write FFH
E rase Resume
Data = D0H
Addr = X
Read Array Data
Done
Reading
NO
YES
Write D0H
Write FFH
Erase Resumed
Read Array Data
0539_08
Figure 8. Erase Suspend/Resume Flowchart
32
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3.5
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Power Consumption
3.5.1
ACTIVE POWER
With CE# at a logic-low level and RP# at a
logic-high level, the device is placed in the
active mode. Refer to the DC
Characteristics table for ICC current values.
3.5.2
AUTOMATIC POWER
SAVINGS (APS)
Automatic Power Savings (APS) provides
low-power operation during active mode.
Power Reduction Control (PRC) circuitry
allows the device to put itself into a low
current state when not being accessed. After
data is read from the memory array, PRC
logic controls the device’s power
consumption by entering the APS mode
where typical ICC current is less than 1 mA.
The device stays in this static state with
outputs valid until a new location is read.
(GND ± 0.2V). Note: BYTE# pin must be
at CMOS levels to meet the ICCD
specification.
During read modes, the RP# pin going low
de-selects the memory and places the output
drivers in a high impedance state. Recovery
from the deep power-down state, requires a
minimum access time of tPHQV (see AC
Characteristics table).
During erase or program modes, RP# low
will abort either erase or program
operations, but the memory
3.5.3
STANDBY POWER
With CE# at a logic-high level (VIH), and
the CUI in read mode, the memory is placed
in standby mode, which disables much of
the device’s circuitry and substantially
reduces power consumption. Outputs (DQ0–
DQ15 or DQ0–DQ7) are placed in a highimpedance state independent of the status of
the OE# signal. When CE# is at logic-high
level during erase or program operations,
the device will continue to perform the
operation and consume corresponding
active power until the operation is
completed.
3.5.4
DEEP POWER-DOWN MODE
The SmartVoltage boot block family
supports a low typical ICC in deep powerdown mode, which turns off all circuits to
save power. This mode is activated by the
RP# pin when it is at a logic-low
PRODUCT PREVIEW
33
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
contents are no longer valid as the data has
been corrupted by the RP# function. As in
the read mode above, all internal circuitry is
turned off to achieve the power savings.
RP# transitions to VIL, or turning power off
to the device will clear the Status Register.
3.6
Power-Up/Down Operation
The device is protected against accidental
block erasure or programming during power
transitions. Power supply sequencing is not
required, since the device is indifferent as
to which power supply, VPP or VCC, powersup first. The CUI is reset to the read mode
after power-up, but the system must drop
CE# low or present a new address to ensure
valid data at the outputs.
A system designer must guard against
spurious writes when VCC voltages are
above VLKO and VPP is active. Since both
WE# and CE# must be low for a command
write, driving either signal to VIH will
inhibit writes to the device. The CUI
architecture provides additional protection
since alteration of memory contents can
only occur after successful completion of
the two-step command sequences. The
device is also disabled until RP# is brought
to VIH, regardless of the state of its control
inputs. By holding the device in reset (RP#
connected to system PowerGood) during
power-up/down, invalid bus conditions
during power-up can be masked, providing
yet another level of memory protection.
3.6.1
RP# CONNECTED TO
SYSTEM RESET
The use of RP# during system reset is
important with automated write/erase
devices because the system expects to read
from the flash memory when it comes out
of reset. If a CPU reset occurs without a
flash memory reset, proper CPU
34
E
initialization would not occur because the
flash memory may be providing status
information instead of array data. Intel’s
Flash memories allow proper CPU
initialization following a system reset by
connecting the RP# pin to the same
RESET# signal that resets the system CPU.
3.6.2
VCC, VPP AND RP#
TRANSITIONS
The CUI latches commands as issued by
system software and is not altered by VPP or
CE# transitions or WSM actions. Its default
state upon power-up, after exit from deep
power-down mode, or after VCC transitions
above VLKO (Lockout voltage), is read array
mode.
After any word/byte write or block erase
operation is complete and even after VPP
transitions down to VPPLK, the CUI must be
reset to read array mode via the Read Array
command if accesses to the flash memory
are desired.
Please refer to AP-617, “Additional Flash
Data Protection Using VPP, RP#, and WP#”
for a circuit-level description of how to
implement the protection discussed in
Section 3.6.
3.7
Power Supply Decoupling
Flash memory’s power switching
characteristics require careful device
decoupling methods. System designers
should consider three supply current issues:
1. Standby current levels (ICCS)
2. Active current levels (ICCR)
3. Transient peaks produced by falling and
rising edges of CE#.
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Transient current magnitudes depend on the
device outputs’ capacitive and inductive
loading. Two-line control and proper
decoupling capacitor selection will suppress
these transient voltage peaks. Each flash
device should have a 0.1 µF ceramic
capacitor connected between each VCC and
GND, and between its VPP and GND. These
high- frequency, inherently low-inductance
capacitors should be placed as close as
possible to the package leads.
3.7.1
VPP TRACE ON PRINTED
CIRCUIT BOARDS
Designing for in-system writes to the flash
memory requires special consideration of
the VPP power supply trace by the printed
circuit board designer. The VPP pin supplies
the flash memory cells current for
programming and erasing. One should use
similar trace widths and layout
considerations given to the VCC power
supply trace. Adequate VPP supply traces,
and decoupling capacitors placed adjacent
to the component, will decrease spikes and
overshoots.
NOTE:
Table headings in Sections 5 and 6 (i.e., BV-70, BV-120, TBV-90, TBE-120) refer to
the specific products listed below. See Section 7.1 for more information on product
naming and line items.
Abbreviatio
n
Applicable Product Names
BV-70
E28F008BV-T70, E28F008BV-B70, E28F800CV-T70, E28F800CVB70, PA28F800BV-T70, PA28F800BV-B70
BV-120
E28F008BV-T120, E28F008BV-B120, PA28F800BV-T120,
PA28F800BV-B120
TBV-90
TE28F008BV-T90, TE28F008BV-B90, TE28F800CV-T90,
TE28F800CV-B90, TB28F800BV-T90, TB28F800BV-B90
TBE-120
TE28F008BE-T120, TE28F008BE-B120, TE28F800CE-T120,
TE28F800CE-B120, TB28F800BE-T120, TB28F800BE-B120
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
4.0
ABSOLUTE MAXIMUM
RATINGS*
Commercial Operating Temperature
During Read.....................0°C to +70°C
During Block Erase
and Word/Byte Write.......0°C to +70°C
Temperature Bias .........–10°C to +80°C
Extended Operating Temperature
During Read.................–40°C to +85°C
NOTICE: This datasheet contains information on products in the
sampling and initial production phases of development. The
specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest datasheet
before finalizing a design.
* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These are
stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may effect device
reliability.
NOTES:
1.
2.
During Block Erase
and Word/Byte Write...–40°C to +85°C
Temperature Under Bias–40°C to +85°C
Storage Temperature........–65°C to +125°C
Voltage on Any Pin
(except VCC, VPP, A9 and RP#)
with Respect to GND .–2.0V to +7.0V(2)
E
3.
4.
Operating temperature is for commercial product defined
by this specification.
Minimum DC voltage is –0.5V on input/output pins.
During transitions, this level may undershoot to –2.0V for
periods < 20 ns. Maximum DC voltage on input/output pins
is VCC + 0.5V which, during transitions, may overshoot to
VCC + 2.0V for periods
< 20 ns.
Maximum DC voltage on VPP may overshoot to +14.0V for
periods < 20 ns. Maximum DC voltage on RP# or A9 may
overshoot to 13.5V for periods < 20 ns.
Output shorted for no more than one second. No more than
one output shorted at a time.
Voltage on Pin RP# or Pin A9
with Respect to GND–2.0V to
+13.5V(2,3)
VPP Program Voltage with Respect
to GND during Block Erase
and Word/Byte Write–2.0V to
+14.0V(2,3)
VCC Supply Voltage
with Respect to GND .–2.0V to +7.0V(2)
Output Short Circuit Current......100 mA (4)
36
PRODUCT PREVIEW
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5.0
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
COMMERCIAL OPERATING CONDITIONS
Table 10. Commercial Temperature and V CC Operating Conditions
Symbol
Parameter
TA
Operating Temperature
VCC
3.3V VCC Supply Voltage (±
0.3V)
Notes
Min
Max
Units
0
+70
°C
3.0
3.6
Volts
5V VCC Supply Voltage (10%)
1
4.50
5.50
Volts
5V VCC Supply Voltage (5%)
2
4.75
5.25
Volts
NOTES:
1. 10% VCC specifications apply to the 80 ns and 120 ns product versions in their standard test configuration.
2. 5% VCC specifications apply to the 80 ns versions in their high-speed test configuration.
5.1
Applying V CC Voltages
When applying VCC voltage to the device, a delay may be required before initiating device
operation, depending on the VCC ramp rate. If VCC ramps slower than 1V/100 µs (0.01 V/µs)
then no delay is required. If VCC ramps faster than 1V/100 µs (0.01 V/µs), then a delay of 2
µs is required before initiating device opeation. RP# = GND is recommended during powerup to protect against spurious write signals when VCC is between VLKO and VCCMIN.
VCC Ramp
Rate
Required Timing
≤ 1V/100 µs
No delay required.
> 1V/100 µs
A delay time of 2 µs is required before any device operation is initiated,
including read operations, command writes, program operations, and erase
operations. This delay is measured beginning from the time VCC reaches
VCCMIN (3.0V for 3.3 ± 0.3V operation; and 4.5V for 5V operation).
NOTES:
1. These requirements must be strictly followedto guarantee all other read and write specifications.
2. To switch between 3.3V and 5V operation, the system should first transition V
CC from the existing voltage range to GND, and then
to the new voltage. Any time the VCC supply drops below VCCMIN, the chip may be reset, aborting any operations pending or in
progress.
3. These guidelines must be followed for any VCC transition from GND.
PRODUCT PREVIEW
37
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
5.2
DC Characteristics
Table 11. DC Characteristics (Commercial)
Prod
Sym
E
Parameter
VCC
Note
s
BV-70
BV-120
3.3 ± 0.3V 5V ± 10% Unit
s
Typ Max Typ Max
Test Conditions
IIL
Input Load Current
1
±
1.0
±
1.0
µA
VCC = VCC Max
VIN = VCC or GND
ILO
Output Leakage
Current
1
± 10
± 10
µA
VCC = VCC Max
VIN = VCC or GND
ICCS
VCC Standby
Current
mA VCC = VCC Max
CE# = RP# = BYTE#
=
WP# = VIH
V
= VCC Max
CC
µA
CE# = RP# = VCC ±
0.2V
µA VCC = VCC Max
VIN = VCC or GND
RP# = GND ± 0.2V
ICCD
VCC Deep
1,3
0.4
1.5
0.8
2.0
60
110
50
130
1
0.2
8
0.2
8
1,5,6
15
30
50
60
Power-Down
Current
ICCR
38
VCC Read Current
for Word or Byte
mA CMOS INPUTS
VCC = VCC Max
CE# = GND, OE# =
VCC
f = 10 MHz (5V),
5 MHz (3.3V)
IOUT = 0 mA
Inputs = GND ±
0.2V or
VCC ± 0.2V
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 11. DC Characteristics (Commercial)
ICCW
ICCE
VCC Write Current
for Word or Byte
VCC Erase Current
ICCES VCC Erase Suspend
Current
1,4
1,4
1,2
PRODUCT PREVIEW
15
30
55
65
13
30
30
50
10
25
30
45
13
30
18
35
10
25
18
30
3
8.0
5
10
mA TTL INPUTS
VCC = VCC Max
CE# = VIL, OE# =
VIH
f = 10 MHz (5V),
5 MHz (3.3V)
IOUT = 0 mA
Inputs = VIL or VIH
mA VPP = VPPH1 (at 5V)
Word Write in
Progress
mA VPP = VPPH2 (at 12V)
Word Write in
Progress
mA VPP = VPPH1 (at 5V)
Block Erase in
Progress
mA VPP = VPPH2 (at
12V)
Block Erase in
Progress
mA CE# = VIH
Block Erase Suspend
39
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 11. DC Characteristics (Commercial) (Continued)
Prod
Sym
Parameter
VCC
Note
s
BV-70
BV-120
3.3 ± 0.3V 5V ± 10% Unit
s
Typ Max Typ Max
Test Conditions
IPPS
VPP Standby
Current
1
±
0.5
± 15
±
0.5
± 10
µA
VPP < VPPH2
IPPD
VPP Deep PowerDown
Current
1
0.2
5
0.2
5.0
µA
RP# = GND ± 0.2V
IPPR
VPP Read Current
1
50
200
30
200
µA
VPP ≥ VPPH2
IPPW
VPP Word/Byte
Current
1,4
13
30
13
25
8
25
8
20
13
30
10
20
8
25
5
15
50
200
30
200
mA VPP = VPPH1 (at 5V)
Word Write in
Progress
VPP = VPPH2 (at 12V)
Word Write in
Progress
mA VPP = VPPH1 (at 5V)
Block Erase in
Progress
VPP = VPPH2 (at 12V)
Block Erase in
Progress
µA VPP = VPPH Block
Erase
Suspend in Progress
IPPE
VPP Erase Current
1,4
IPPES
VPP Erase
Suspend Current
1
IRP#
RP# Boot Block
Unlock Current
1,4
500
500
µA
RP# = VHH
IID
A9 Intelligent
Identifier Current
1,4
500
500
µA
A9 = VID
40
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 11. DC Characteristics (Commercial) Continued
Prod
Sym
Parameter
VCC
BV-70
BV-120
3.3 ± 0.3V 5V ± 10%
Unit
Test
Conditions
Notes Min Max Min Max
VID
A9 Intelligent Identifier
Voltage
11.4 12.6 11.4 12.6
V
VIL
Input Low Voltage
–0.5
0.8
–0.5
0.8
V
VIH
Input High Voltage
2.0
VCC
+
0.5V
2.0
VCC
+
0.5V
V
VOL
Output Low Voltage
0.45
V
0.45
VOH1 Output High Voltage
(TTL)
2.4
2.4
V
VOH2 Output High Voltage
(CMOS)
0.85
x
VCC
0.85
x
VCC
V
VCC –
0.4V
VCC –
0.4V
V
VPPL VPP Lock-Out Voltage
3
VCC = VCC
Min
IOL = 5.8 mA
VCC = VCC
Min
IOH = –2.5
mA
VCC = VCC
Min
IOH = –2.5
mA
VCC = VCC
Min
IOH = –100
µA
0.0
1.5
0.0
1.5
V
Complete
Write
Protection
VPPH VPP (Prog/Erase
1
Operations)
4.5
5.5
4.5
5.5
V
VPP at 5V
VPPH VPP (Prog/Erase
2
Operations)
11.4 12.6 11.4 12.6
V
VPP at 12V
2.0
V
K
VLKO VCC Erase/Write Lock
Voltage
PRODUCT PREVIEW
8
2.0
41
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 11. DC Characteristics (Commercial) Continued
VHH
RP# Unlock Voltage
11.4 12.6 11.4 12.6
V
Boot Block
Write/Erase
Table 12. Capacitance (T A = 25 °C, f = 1 MHz)
Symbol
Parameter
Notes
Typ
Max
Units
Conditions
CIN
Input
Capacitance
4
6
8
pF
VIN = 0V
COUT
Output
Capacitance
4, 7
10
12
pF
VOUT = 0V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
CC = 5.0V, T = +25°C. These currents are valid for all product
versions (packages and speeds).
2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum ofCCES
I and
ICCR.
3. Block erases and word/byte writes are inhibited when VPP = VPPLK, and not guaranteed in the range between VPPH1 and VPPLK.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical, in static operation.
6. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.
7. For the 28F008B, address pin A10 follows the COUT capacitance numbers.
8. For all BV/CV parts, VLKO = 2.0V for both 3.3V and 5V operations.
3.0
INPUT
1.5
TEST POINTS
1.5
OUTPUT
0.0
0539_09
NOTE:
AC test inputs are driven at 3.0V for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at 1.5V. Input rise
and fall times (10%–90%) <10 ns.
Figure 9. 3.3V Inputs and Measurement Points
42
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
2.4
2.0
2.0
INPUT
OUTPUT
TEST POINTS
0.8
0.45
0.8
0539_10
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a logic “1” and VOL (0.45 VTTL) for a logic “0.” Input timing begins at VIH (2.0 VTTL)
and VIL (0.8 VTTL) . Output timing ends at VIH and VIL. Input rise and fall times (10%–90%) <10 ns.
Figure 10. 5V Inputs and Measurement Points
Test Configuration Component Values
VCC
R
CL
(pF)
R1
(Ω
Ω)
R2
(Ω
Ω)
3.3V Standard Test
50
990
770
5V Standard Test
100
580
390
5V High-Speed Test
30
580
390
1
Device
under
Test
Out
CL
R
Test Configuration
2
NOTE:
CL includes jig capacitance.
0539-11
NOTE:
See table for component values.
Figure 11. Test Configuration
PRODUCT PREVIEW
43
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
5.3
AC Characteristics
Table 13. AC Characteristics: Read Only Operations (Commercial)
Prod
VCC 3.3±0.3V (
BV-70
5V±5% (6) 5V±10% (
7)
5)
Symbo
l
Parameter
Loa
d
Note
s
50 pF
Min
Max
Min
Max
Min
Unit
s
Max
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE# to Output Delay
tPHQV
RP# to Output Delay
tGLQV
OE# to Output Delay
2
tELQX
CE# to Output in Low Z
3
tEHQZ
CE# to Output in High Z
3
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE# to Output in High Z
3
tOH
Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First
3
tELFL
tELFH
CE# Low to BYTE# High
or Low
3
5
5
5
ns
tAVFL
Address to BYTE# High or
Low
3
5
5
5
ns
tFLQV
tFHQV
BYTE# to Output Delay
3,4
120
70
80
ns
tFLQZ
BYTE# Low to Output in
High Z
3
45
20
25
ns
2
70
100 pF
tAVAV
44
120
30 pF
80
ns
120
70
80
ns
120
70
80
ns
1.5
0.4
5
0.4
5
µs
65
30
35
ns
0
0
55
0
0
20
0
45
0
ns
25
0
20
0
ns
ns
25
0
ns
ns
PRODUCT PREVIEW
E
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 13. AC Characteristics: Read Only Operations (Commercial) (Continued)
Prod
BV-120
Sym
Parameter
VCC
3.3±0.3V (5) 5V±10% (7) Units
Load
50 pF
100 pF
Notes Min Max Min Max
tAVAV
Read Cycle Time
150
tAVQV
Address to Output Delay
tELQV
CE# to Output Delay
tPHQV
RP# to Output Delay
tGLQV
OE# to Output Delay
2
tELQX
CE# to Output in Low Z
3
tEHQZ
CE# to Output in High Z
3
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE# to Output in High Z
3
tOH
Output Hold from Address, CE#,
or OE# Change, Whichever
Occurs First
3
tELFL
tELFH
CE# Low to BYTE# High or Low
3
5
5
ns
tAVFL
Address to BYTE# High or Low
3
5
5
ns
tFLQV
tFHQV
BYTE# to Output Delay
3,4
150
120
ns
tFLQZ
BYTE# Low to Output in High Z
3
60
30
ns
2
120
ns
150
120
ns
150
120
ns
1.5
0.45
µs
90
40
ns
0
0
80
0
ns
30
0
60
0
ns
ns
30
0
ns
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to tCE–tOE after the falling edge of CE# without impact on CE
t .
3. Sampled, but not 100% tested.
4. tFLQV, BYTE# switching low to valid output delay will be equal toAVQV
t
, measured from the time DQ15/A–1 becomes valid.
5. See Test Configurations (Figure11), 3.3V Standard Test component values.
6. See Test Configurations (Figure 11), 5V High-Speed Test component values.
7. See Test Configurations (Figure11), 5V Standard Test component values.
PRODUCT PREVIEW
45
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Device and
Address Selection
VIH
ADDRESSES (A)
VIL
VIH
CE# (E)
VIL
Data
Valid
Standby
Address Stable
t AVAV
t EHQZ
VIH
OE# (G)
VIL
VIH
WE# (W)
VIL
VOH
DATA (D/Q)
VOL
RP#(P)
t GHQZ
t GLQX
t GLQV
t ELQX
High Z
t OH
t ELQV
High Z
Valid Output
t AVQV
VIH
t PHQV
VIL
0539_14
Figure 12. AC Waveforms for Read Operations
VIH
ADDRESSES (A)
VIL
CE# (E)
Standby
Address Stable
t AVAV
VIH
VIL
OE# (G)
Data
Valid
Device
Address Selection
t EHQZ
t AVFL
VIH
t ELFL
VIL
BYTE# (F)
t GHQZ
VIH
VIL
VOH
DATA (D/Q)
t GLQV
t ELQV
t GLQX
High Z
t ELQX
Data Output
on DQ0-DQ7
(DQ0-DQ7)
VOL
DATA (D/Q)
VOH
High Z
VOL
(DQ15/A-1)
High Z
t AVQV
t FLQZ
High Z
High Z
Data Output
on DQ8-DQ14
(DQ8-DQ14)
VOH
t OH
Data Output
on DQ0-DQ7
t AVQV
Data Output
on DQ15
Address Input
High Z
VOL
0539_15
Figure 13. BYTE# Timing Diagram for Read Operations
46
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 14. AC Characteristics: WE#–Controlled Write Operations
Prod
PRODUCT PREVIEW
(1)
(Commercial)
BV-70
47
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 14. AC Characteristics: WE#–Controlled Write Operations
Symbo
l
Parameter
VCC
Loa
d
Note
s
3.3±0.3V
(
5V±5%
(10
(1)
(Commercial)
5V±10% (
9)
)
11)
50 pF
30 pF
100 pF
Mi
n
Ma
x
Mi
n
Ma
x
Mi
n
Unit
Ma
x
tAVAV
Write Cycle Time
120
70
80
ns
tPHWL
RP# Setup to WE# Going
Low
1.5
0.4
5
0.4
5
µs
tELWL
CE# Setup to WE# Going
Low
0
0
0
ns
tPHHWH
Boot Block Lock Setup to
WE# Going High
6,8
200
100
100
ns
tVPWH
VPP Setup to WE# Going
High
5,8
200
100
100
ns
tAVWH
Address Setup to WE#
Going High
3
90
50
50
ns
tDVWH
Data Setup to WE# Going
High
4
90
50
50
ns
tWLWH
WE# Pulse Width
90
50
50
ns
tWHDX
Data Hold Time from WE#
High
4
0
0
0
ns
tWHAX
Address Hold Time from
WE# High
3
0
0
0
ns
tWHEH
CE# Hold Time from WE#
High
0
0
0
ns
tWHWL
WE# Pulse Width High
20
10
20
ns
tWHQV1
Duration of Word/Byte
Programming Operation
2,5
6
6
6
µs
tWHQV2
Duration of Erase
Operation (Boot)
2,5,6
0.3
0.3
0.3
s
tWHQV3
Duration of Erase
Operation (Parameter)
2,5
0.3
0.3
0.3
s
48
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 14. AC Characteristics: WE#–Controlled Write Operations
(1)
(Commercial)
tWHQV4
Duration of Erase
Operation (Main)
2,5
0.6
0.6
0.6
s
tQWL
VPP Hold from Valid SRD
5,8
0
0
0
ns
tQVPH
RP# VHH Hold from Valid
SRD
6,8
0
0
0
ns
tPHBR
Boot-Block Lock Delay
7,8
PRODUCT PREVIEW
200
100
100
ns
49
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 14. AC Characteristics: WE#–Controlled Write Operations (1) (Commercial)
(Continued)
Prod
BV-120
Sym
Parameter
VCC
3.3±0.3V (9) 5V±10% (11) Unit
Load
50 pF
100 pF
Note Min Max Min Max
tAVAV
Write Cycle Time
180
120
ns
tPHWL
RP# Setup to WE# Going Low
1.5
0.45
µs
tELWL
CE# Setup to WE# Going Low
0
0
ns
tPHHWH
Boot Block Lock Setup to WE#
Going High
6,8
200
100
ns
tVPWH
VPP Setup to WE#
Going High
5,8
200
100
ns
tAVWH
Address Setup to WE# Going
High
3
150
50
ns
tDVWH
Data Setup to WE# Going High
4
150
50
ns
tWLWH
WE# Pulse Width
150
50
ns
tWHDX
Data Hold Time from WE# High
4
0
0
ns
tWHAX
Address Hold Time from WE#
High
3
0
0
ns
tWHEH
CE# Hold Time from WE# High
0
0
ns
tWHWL
WE# Pulse Width High
30
30
ns
tWHQV1
Duration of Word/Byte
Programming Operation
2,5
6
6
µs
tWHQV2
Duration of Erase Operation
(Boot)
2,5,6
0.3
0.3
s
tWHQV3
Duration of Erase Operation
(Parameter)
2,5
0.3
0.3
s
tWHQV4
Duration of Erase Operation
(Main)
2,5
0.6
0.6
s
tQWL
VPP Hold from Valid SRD
5,8
0
0
ns
50
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
tQVPH
RP# VHH Hold from Valid SRD
6,8
tPHBR
Boot-Block Lock Delay
7,8
0
0
200
ns
100
ns
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during read mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which
includes verify and margining operations.
3. Refer to command definition table for valid AIN. (Table 7)
4. Refer to command definition table for valid DIN. (Table 7)
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7=1).
6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes successfully.
7. Time tPHBR is required for successful locking of the boot block.
8. Sampled, but not 100% tested.
9. See Test Configurations (Figure11), 3.3V Standard Test component values.)
10. See Test Configurations (Figure11), 5V High-Speed Test component values.
11. See Test Configurations (Figure11), 5V Standard Test component values.
1
VIH
2
CE# (E)
VIL
VIH
VIL
OE# (G)
VIH
3
AIN
ADDRESSES (A)
t AVAV
t ELWL
4
5
6
AIN
tAVWH
t WHAX
tWHEH
VIL
t WHWL
VIH
t WHQV1,2,3,4
WE# (W)
VIL
VIH
DATA (D/Q)
High Z
VIL
6.5V
RP# (P)
VHH
t WLWH
t DVWH
t WHDX
DIN
t PHWL
DIN
Valid
SRD
t PHHWH
tQVPH
t VPWH
t QVVL
DIN
VIH
VIL
VIH
WP#
VIL
VPPH 2
VPPH1
V (V) V
PP
PPLK
VIL
0539_16
Figure 14. AC Waveforms for Write and Erase Operations (WE#–Controlled Writes)
PRODUCT PREVIEW
51
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 15. AC Characteristics: CE#–Controlled Write Operations
(Commercial)
Prod
VCC 3.3±0.3V (
Symbo
l
Parameter
Loa
d
Note
(1,12)
BV-70
5V±5% (10
5V±10% (
9)
)
11)
50 pF
30 pF
100 pF
Min
Max
Min
Max
Min
Unit
Max
tAVAV
Write Cycle Time
120
70
80
ns
tPHEL
RP# High Recovery to CE#
Going Low
1.5
0.4
5
0.4
5
µs
tWLEL
WE# Setup to CE# Going
Low
0
0
0
ns
tPHHEH
Boot Block Lock Setup to
CE# Going High
6,8
200
100
100
ns
tVPEH
VPP Setup to CE# Going
High
5,8
200
100
100
ns
tAVEH
Address Setup to CE#
Going High
3
90
50
50
ns
tDVEH
Data Setup to CE# Going
High
4
90
50
50
ns
tELEH
CE# Pulse Width
90
50
50
ns
tEHDX
Data Hold Time from CE#
High
4
0
0
0
ns
tEHAX
Address Hold Time from
CE# High
3
0
0
0
ns
tEHWH
WE # Hold Time from CE#
High
0
0
0
ns
tEHEL
CE# Pulse Width High
20
10
20
ns
tEHQV1
Duration of Word/Byte
Programming Operation
2,5
6
6
6
µs
tEHQV2
Duration of Erase
Operation (Boot)
2,5,6
0.3
0.3
0.3
s
52
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 15. AC Characteristics: CE#–Controlled Write Operations
(Commercial)
(1,12)
tEHQV3
Duration of Erase
Operation (Parameter)
2,5
0.3
0.3
0.3
s
tEHQV4
Duration of Erase
Operation (Main)
2,5
0.6
0.6
0.6
s
tQWL
VPP Hold from Valid SRD
5,8
0
0
0
ns
tQVPH
RP# VHH Hold from Valid
SRD
6,8
0
0
0
ns
tPHBR
Boot-Block Lock Delay
7,8
200
100
100
ns
Table 15. AC Characteristics: CE#–Controlled Write Operations (1,12) (Commercial)
(Continued)
Prod
BV-120
Sym
Parameter
VCC
3.3±0.3V (9) 5V±10% (11) Unit
Load
50 pF
100 pF
Note Min Max Min Max
tAVAV
Write Cycle Time
180
120
ns
tPHEL
RP# High Recovery to CE# Going
Low
1.5
0.45
µs
tWLEL
WE# Setup to CE# Going Low
0
0
ns
tPHHEH
Boot Block Lock Setup to CE#
Going High
6,8
200
100
ns
tVPEH
VPP Setup to CE# Going High
5,8
200
100
ns
tAVEH
Address Setup to CE# Going High
3
150
50
ns
tDVEH
Data Setup to CE# Going High
4
150
50
ns
tELEH
CE# Pulse Width
150
50
ns
tEHDX
Data Hold Time from CE# High
4
0
0
ns
tEHAX
Address Hold Time from CE#
High
3
0
0
ns
tEHWH
WE # Hold Time from CE# High
0
0
ns
tEHEL
CE# Pulse Width High
30
30
ns
PRODUCT PREVIEW
53
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
tEHQV1
Duration of Word/Byte
Programming Operation
2,5
6
6
µs
tEHQV2
Duration of Erase Operation
(Boot)
2,5,6
0.3
0.3
s
tEHQV3
Duration of Erase Operation
(Parameter)
2,5
0.3
0.3
s
tEHQV4
Duration of Erase Operation
(Main)
2,5
0.6
0.6
s
tQWL
VPP Hold from Valid SRD
5,8
0
0
ns
tQVPH
RP# VHH Hold from Valid SRD
6,8
0
0
ns
tPHBR
Boot-Block Lock Delay
7,8
200
100
ms
NOTES:
See WE# Controlled Write Operations for notes 1 through 11.
12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE# waveform.
54
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
1
VIH
2
3
AIN
ADDRESSES (A)
VIL
VIH
4
5
6
AIN
t EHAX
t AVEH
t AVAV
WE# (W)
VIL
OE# (G)
VIH
tEHWH
t WLEL
VIL
CE# (E)
t
VIH
VIL
VIH
DATA (D/Q)
High Z
VIL
6.5V
RP# (P)
VHH
t EHQV1,2,3,4
EHEL
t ELEH
t DVEH
t EHDX
DIN
t PHEL
DIN
Valid
SRD
DIN
tPHHEH
tQVPH
t VPEH
t QVVL
VIH
VIL
VIH
WP#
VIL
VPPH 2
VPPH1
V (V) V
PP
PPLK
VIL
0539_17
NOTES:
1. VCC Power-Up and Standby.
2. Write program or Erase Setup Command.
3. Write Valid Address and Data (Program) or Erase Confirm Command.
4. Automated Program or Erase Delay.
5. Read Status Register Data.
6. Write Read Array Command.
Figure 15. Alternate AC Waveforms for Write and Erase Operations (CE#–Controlled
Writes)
PRODUCT PREVIEW
55
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 16. Erase and Program Timings (Commercial T A = 0°C to +70°C)
5V ± 10%
VPP
Parameter
12V ± 5%
3.3 ± 0.3V
5V ± 10%
3.3 ± 0.3V
Boot/Parameter Block Erase
Time
0.84
7
0.8
7
0.44
7
0.34
7
s
Main Block Erase Time
2.4
14
1.9
14
1.3
14
1.1
14
s
Main Block Write Time (Byte
Mode)
1.7
1.8
1.6
1.2
s
Main Block Write Time (Word
Mode)
1.1
0.9
0.8
0.6
s
Byte Write Time
10
10
8
8
µs
Word Write Time
13
13
8
8
µs
VCC
5V ± 10% Un
it
Typ Max Typ Max Typ Max Typ Max
NOTES:
1. All numbers are sampled, not 100% tested.
2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value independent of CVC and
VPP. See Note 3 for typical conditions.
3. Typical conditions are 25°C with VCC and VPP at the center of the specifed voltage range. Production programming using
VCC = 5.0V, VPP = 12.0V typically results in a 60% reduction in programming time.
4. Contact your Intel representative for information regarding maximum byte/word write specifications.
56
PRODUCT PREVIEW
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6.0
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
EXTENDED OPERATING CONDITIONS
Table 17. Extended Temperature and V CC Operating Conditions
Symbol
Parameter
Notes
Min
Max
Units
–40
+85
°C
TA
Operating Temperature
VCC
2.7V–3.6V VCC Supply
Voltage
1
2.7
3.6
Volts
3.3V VCC Supply Voltage (±
0.3V)
1
3.0
3.6
Volts
5V VCC Supply Voltage (10%)
2
4.50
5.50
Volts
NOTES:
1. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
2. 10% VCC specifications apply to 100 ns versions in their standard test configuration.
6.1
Applying V CC Voltages
When applying VCC voltage to the device, a delay may be required before initiating device
operation, depending on the VCC ramp rate. If VCC ramps slower than 1V/100 µs (0.01 V/µs)
then no delay is required. If VCC ramps faster than 1V/100 µs (0.01 V/µs), then a delay of 2
µs is required before initiating device opeation. RP# = GND is recommended during powerup to protect against spurious write signals when VCC is between VLKO and VCCMIN.
VCC Ramp
Rate
Required Timing
≤ 1V/100 µs
No delay required.
> 1V/100 µs
A delay time of 2 µs is required before any device operation is initiated,
including read operations, command writes, program operations, and erase
operations. This delay is measured beginning from the time VCC reaches
VCCMIN (2.7V for 2.7V–3.6V operation, 3.0V for 3.3± 0.3V operation; and
4.5V for 5V operation).
NOTES:
1. These requirements must be strictly followed to guarantee all other read and write specifications.
2. To switch between 3.3V and 5V operation, thesystem should first transition VCC from the existing voltage range to GND, and then
to the new voltage. Any time the VCC supply drops below VCCMIN, the chip may be reset, aborting any operations pending or in
progress.
3. These guidelines must be followed for any VCC transition from GND.
PRODUCT PREVIEW
57
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
6.2
DC Characteristics
Table 18. DC Characteristics: Extended Temperature Operation
Sym Paramet
er
Prod
TBE-120
TBV-90
TBV-90
TBE-120
VCC
2.7V–3.6V
3.3V ±
0.3V
Note
s
Typ Ma
x
Typ Ma
x
Typ Ma
x
5V ± 10% Unit
Test Conditions
IIL
Input
Load
Current
1
±
1.0
±
1.0
±
1.0
µA VCC = VCCMax
VIN = VCC or GND
ILO
Output
Leakage
Current
1
± 10
± 10
± 10
µA VCC = VCC Max
VIN = VCC or GND
ICCS
VCC
Standby
Current
1,3
150
µA CMOS Levels
VCC = VCC Max
50
110
60
110
70
CE# = RP# = WP#
=
VCC ± 0.2V
0.4
1.5
0.4
1.5
0.8
2.5
mA TTL Levels
VCC = VCC Max
CE# = RP# =
BYTE#
= VIH
ICCD
58
VCC Deep
PowerDown
Current
1
0.2
8
0.2
8
0.2
8
µA VCC = VCC Max
VIN = VCC or GND
RP# = GND ±
0.2V
PRODUCT PREVIEW
E
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 18. DC Characteristics: Extended Temperature Operation
ICCR
VCC Read
Current
for Word
or Byte
1,5,6
14
30
15
30
50
65
mA CMOS INPUTS
VCC = VCC Max
CE = VIL
f = 10 MHz (5V)
5 MHz (3.3V)
IOUT = 0 mA
Inputs = GND ±
0.2V
or VCC ± 0.2V
14
30
15
30
55
70
mA TTL INPUTS
VCC = VCC Max
CE# = VIL
f = 10 MHz (5V),
5 MHz (3.3V)
IOUT = 0 mA
Inputs = VIL or VIH
PRODUCT PREVIEW
59
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 18. DC Characteristics: Extended Temperature Operation (Continued)
Sym Paramet
er
ICCW
ICCE
VCC Write
Current
for Word
or Byte
VCC Erase
Current
Prod
TBE-120
TBV-90
VCC
2.7V–3.6V
3.3V ±
0.3V
Note
s
Typ Ma
x
Typ Ma
x
1,4
1,4
TBV-90
TBE-120
5V ± 10% Unit
Test Conditions
Typ Ma
x
8
30
13
30
30
50
mA VPP = VPPH1 (at
5V)
Word/Byte
Program
in Progress
9
25
10
25
30
45
mA VPP = VPPH2 (at
12V)
Word/Byte
Program
in Progress
12
30
13
30
22
45
mA VPP = VPPH1 (at
5V)
Block Erase in
Progress
9
25
10
25
18
40
mA VPP = VPPH2 (at
12V)
Block Erase in
Progress
ICCES
VCC Erase
Suspend
Current
1,2
2.5
8.0
3
8.0
5
IPPS
VPP
Standby
Current
VPP Deep
Powerdown
Current
1
±5
± 15
±5
± 15
±5
± 15
µA
VPP < VPPH2
1
0.2
10
0.2
10
0.2
10
µA
RP# = GND ±
0.2V
IPPD
60
12.0 mA VPP = VPPH1 (at
5V)
CE# = VIH
Block Erase
Suspend
PRODUCT PREVIEW
E
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 18. DC Characteristics: Extended Temperature Operation (Continued)
IPPR
IPPW
VPP Read
Current
VPP Write
Current
for
Word/Byt
e
VPP ≥ VPPH2
1
50
200
50
200
50
200
µA
1,4
13
30
13
30
13
30
mA VPP = VPPH
Word Write in
Progress
VPP = VPPH1 (at
5V)
8
25
8
25
8
25
mA VPP = VPPH
Word Write in
Progress
VPP = VPPH2 (at
12V)
PRODUCT PREVIEW
61
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 18. DC Characteristics: Extended Temperature Operation (Continued)
Sym Paramet
er
IPPE
VPP Erase
Current
Prod
TBE-120
TBV-90
VCC
2.7V–3.6V
3.3V ±
0.3V
Note
s
Typ Ma
x
Typ Ma
x
1,4
TBV-90
TBE-120
5V ± 10% Unit
Typ Ma
x
13
30
13
30
15
25
mA VPP = VPPH
Block Erase in
Progress
VPP = VPPH1 (at
5V)
8
25
8
25
10
20
mA VPP = VPPH
Block Erase in
Progress
VPP = VPPH2 (at
12V)
50
200
50
200
50
200
µA
IPPES
VPP Erase
Suspend
Current
1
IRP#
RP# Boot
Block
Unlock
Current
1,4
500
500
500
µA
IID
A9
Intelligen
t
Identifier
Current
1,4
500
500
500
µA
62
Test Conditions
VPP = VPPH
Block Erase
Suspend
in Progress
RP# = VHH
VPP = 12V
A9 = VID
PRODUCT PREVIEW
E
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 18. DC Characteristics: Extended Temperature Operation (Continued)
Sym Paramet
er
Prod
TBE-120
TBV-90
VCC
2.7V–
3.6V
3.3V ±
0.3V
Note
s
Min Ma
x
Min Ma
x
TBV-90
TBE-120
5V ± 10% Unit
Mi
n
Ma
x
VID
A9
Intelligen
t
Identifier
Voltage
11.4 12.
6
11.4 12.6 11.
4
12.6
V
VIL
Input
Low
Voltage
–0.5
0.8
–0.5
0.8
–
0.5
0.8
V
VIH
Input
High
Voltage
2.0
VCC
±
0.5
V
2.0
VCC
±
0.5
V
2.0
VCC
±
0.5
V
V
VOL
Output
Low
Voltage
0.45
V
0.4
5
0.45
Test Conditions
VCC = VCC Min
VPP = 12V
IOL = 5.8 mA (5V)
2 mA (3.3V)
VOH1 Output
High
Voltage
(TTL)
2.4
2.4
2.4
V
VCC = VCC Min
IOH = –2.5 mA
VOH2 Output
High
Voltage
0.85
✕
VCC
0.85
✕
VCC
0.8
5✕
VCC
V
VCC = VCC Min
IOH = –2.5 mA
VCC–
VCC–
VCC
(CMOS)
0.4
V
PRODUCT PREVIEW
0.4V
–
VCC = VCC Min
IOH = –100 µA
0.4
V
63
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 18. DC Characteristics: Extended Temperature Operation (Continued)
VPPL
K
VPPH
1
VPP
Lock-Out
Voltage
VPP
during
Prog/Eras
e
Operation
s
3
VPPH
2
VLKO VCC
Erase/Wri
te Lock
Voltage
VHH
8
RP#
Unlock
Voltage
0.0
1.5
0.0
1.5
0.0
1.5
V
Complete Write
Protection
4.5
5.5
4.5
5.5
4.5
5.5
V
VPP at 5V
11.4 12.
6
11.4 12.6 11.
4
12.6
V
VPP at 12V
2.0
2.0
11.4 12.
6
11.4 12.6 11.
4
2.0
V
12.6
V
Boot Block Write/
Erase
VPP = 12V
Table 19. Capacitance (T A = 25 °C, f = 1 MHz)
Symbol
Parameter
Notes
Typ
Max
Units
Conditions
CIN
Input
Capacitance
4
6
8
pF
VIN = 0V
COUT
Output
Capacitance
4
10
12
pF
VOUT = 0V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
CC = 5.0V, T = +25°C. These currents are valid for all product
versions (packages and speeds).
2. ICCES is specified with device de-selected. If device is read while in erase suspend, current draw is sum ofCCES
I and ICCR.
3. Block erases and word/byte writes inhibited when VPP = VPPLK, and not guaranteed in the range between VPPH1 and VPPLK.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical, in static operation.
6. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.
7. For the 28F008B address pin A10 follows the COUT capacitance numbers.
8. For all BV/CV/BE/CE parts, VLKO = 2.0V for 2.7V, 3.3V and 5.0V operations.
64
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
2.7
INPUT
1.35
TEST POINTS
1.35
OUTPUT
0.0
0539_18
NOTE:
AC test inputs are driven at 2.7 for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at 1.35V. Input rise
and fall times (10%–90%) <10 ns.
Figure 16. 2.7–3.6V Input Range and Measurement Points
3.0
INPUT
1.5
TEST POINTS
OUTPUT
1.5
0.0
0539_09
NOTE:
AC test inputs are driven at 3.0V for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at 1.5V. Input rise
and fall times (10%–90%) <10 ns.
Figure 17. 3.3V Input Range and Measurement Points
2.4
2.0
INPUT
0.8
0.45
2.0
OUTPUT
TEST POINTS
0.8
0539_10
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a logic “1” and VOL (0.45 VTTL) for a logic “0.” Input timing begins at VIH (2.0 VTTL)
and VIL (0.8 VTTL) . Output timing ends at VIH and VIL. Input rise and fall times (10%–90%) < 10 ns.
Figure 18. 5V Input Range and Measurement Points
PRODUCT PREVIEW
65
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Figure 19. Test Configuration
VCC
Test Configuration Component Values
R
Test Configuration
1
Device
under
Test
Out
CL
R
2
0539_11
CL
(pF)
R1
(Ω
Ω)
R2
(Ω
Ω)
2.7V and 3.3V
Standard
Test
50
990
770
5V Standard Test
100
580
390
NOTE:
CL includes jig capacitance.
NOTE:
See table for component values.
66
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
6.3
AC Characteristics
Table 20. AC Characteristics: Read Only Operations (1) (Extended Temperature)
Sym
Parameter
Prod
TBE-120
TBV-90
TBV-90
TBE-120
VCC
2.7–
3.6V(5)
3.3±0.3V (
5V±10% (
Loa
d
50 pF
50 pF
100 pF
Note
s
Mi
n
Ma
x
120
5)
Mi
n
Ma
x
Mi
n
Unit
s
Ma
x
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE# to Output Delay
tPHQV
RP# to Output Delay
tGLQV
OE# to Output Delay
2
tELQX
CE# to Output in Low Z
3
tEHQZ
CE# to Output in High Z
3
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE# to Output in High Z
3
tOH
Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First
3
tELFL
tELFH
CE# Low to BYTE# High
or Low
3
5
5
5
ns
tAVFL
Address to BYTE# High or
Low
3
5
5
5
ns
tFLQV
tFHQV
BYTE# to Output Delay
3,4
120
120
90
ns
tFLQZ
BYTE# Low to Output in
High Z
3
45
45
30
ns
2
120
6)
90
ns
120
120
90
ns
120
120
90
ns
1.5
1.5
0.4
5
µs
65
65
40
ns
0
0
55
0
0
55
0
45
0
ns
30
0
45
0
ns
ns
30
0
ns
ns
NOTES:
PRODUCT PREVIEW
67
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
1.
2.
3.
4.
5.
6.
68
E
See AC Input/Output Reference Waveform for timing measurements.
OE# may be delayed up to tCE–tOE after the falling edge of CE# without impact on CE
t .
Sampled, but not 100% tested.
tFLQV, BYTE# switching low to valid output delay will be equal toAVQV
t
, measured from the time DQ15/A–1 becomes valid.
See Test Configurations (Figure19), 2.7–3.6V and 3.3 ± 0.3V Standard Test component values.
See Test Configurations (Figure19), 5V Standard Test component values.
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 21. AC Characteristics: WE#-Controlled Write Operations (1) (Extended
Temperature)
Sym
Parameter
Prod
TBE-120
TBV-90
TBV-90
TBE-120
VCC
2.7–
3.6V(9)
3.3±0.3V (
5V±10% (
Loa
d
50 pF
50 pF
100 pF
Note
s
Mi
n
Ma
x
9)
Mi
n
Ma
x
10)
Mi
n
Units
Ma
x
tAVAV
Write Cycle Time
120
120
90
ns
tPHWL
RP# High Recovery to
WE# Going Low
1.5
1.5
0.4
5
µs
tELWL
CE# Setup to WE# Going
Low
0
0
0
ns
tPHHWH
Boot Block Lock Setup to
WE# Going High
6,8
200
200
100
ns
tVPWH
VPP Setup to WE#
Going High
5,8
200
200
100
ns
tAVWH
Address Setup to WE#
Going High
3
90
90
60
ns
tDVWH
Data Setup to WE# Going
High
4
70
70
60
ns
tWLWH
WE# Pulse Width
90
90
60
ns
tWHDX
Data Hold Time from WE#
High
4
0
0
0
ns
tWHAX
Address Hold Time from
WE# High
3
0
0
0
ns
tWHEH
CE# Hold Time from WE#
High
0
0
0
ns
tWHWL
WE# Pulse Width High
30
20
20
ns
PRODUCT PREVIEW
69
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 21. AC Characteristics: WE#-Controlled Write Operations (1) (Extended
Temperature)
tWHQV1
Duration of Word/Byte
Write Operation
2,5,8
6
6
6
µs
tWHQV2
Duration of Erase
Operation (Boot)
2,5,6
,8
0.3
0.3
0.3
s
tWHQV3
Duration of Erase
Operation (Parameter)
2,5,8
0.3
0.3
0.3
s
tWHQV4
Duration of Erase
Operation (Main)
2,5,8
0.6
0.6
0.6
s
70
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 21. AC Characteristics: WE#-Controlled Write Operations (1) (Extended
Temperature) (Continued)
Sym
Parameter
Prod
TBE-120
TBV-90
TBV-90
TBE-120
VCC
2.7–
3.6V(9)
3.3±0.3V (
5V±10% (
Loa
d
50 pF
50 pF
100 pF
Note
s
Mi
n
Ma
x
9)
Mi
n
Ma
x
10)
Mi
n
Unit
Ma
x
tQWL
VPP Hold from Valid SRD
5,8
0
0
0
ns
tQVPH
RP# VHH Hold from Valid
SRD
6,8
0
0
0
ns
tPHBR
Boot-Block Lock Delay
7,8
200
200
100
ns
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during read mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algori
thms are now controlled internally which
includes verify and margining operations.
3. Refer to command definition table for valid AIN. (Table 7)
4. Refer to command definition table for valid DIN. (Table 7)
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1)
6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes successfully.
7. Time tPHBR is required for successful locking of the boot block.
8. Sampled, but not 100% tested.
9. See Test Configurations (Figure19), 2.7–3.6V and 3.3 ± 0.3V Standard Test component values.
10. See Test Configurations (Figure19), 5V Standard Test component values.
PRODUCT PREVIEW
71
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 22. AC Characteristics: CE#–Controlled Write Operations
Temperature)
Sym
Parameter
(1,11)
(Extended
Prod
TBE-120
TBV-90
TBV-90
TBE-120
VCC
2.7–
3.6V(9)
3.3±0.3V (
5V±10% (
Loa
d
50 pF
50 pF
100 pF
Note
s
Mi
n
Ma
x
9)
Mi
n
Ma
x
10)
Mi
n
Unit
Ma
x
tAVAV
Write Cycle Time
120
120
90
ns
tPHEL
RP# High Recovery to CE#
Going Low
1.5
1.5
0.4
5
µs
tWLEL
WE# Setup to CE# Going
Low
0
0
0
ns
tPHHEH
Boot Block Lock Setup to
CE# Going High
6,8
200
200
100
ns
tVPEH
VPP Setup to CE# Going
High
5,8
200
200
100
ns
tAVEH
Address Setup to CE#
Going High
90
90
60
ns
tDVEH
Data Setup to CE# Going
High
3
70
70
60
ns
tELEH
CE# Pulse Width
4
90
90
60
ns
tEHDX
Data Hold Time from CE#
High
0
0
0
ns
tEHAX
Address Hold Time from
CE# High
4
0
0
0
ns
tEHWH
WE# Hold Time from CE#
High
3
0
0
0
ns
tEHEL
CE# Pulse Width High
20
20
20
ns
tEHQV1
Duration of Word/Byte
Write Operation
6
6
6
µs
72
2,5
PRODUCT PREVIEW
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 22. AC Characteristics: CE#–Controlled Write Operations
Temperature)
tEHQV2
Duration of Erase
Operation (Boot)
tEHQV3
(1,11)
(Extended
2,5,6
0.3
0.3
0.3
s
Duration of Erase
Operation (Parameter)
2,5
0.3
0.3
0.3
s
tEHQV4
Duration of Erase
Operation (Main)
2,5
0.6
0.6
0.6
s
tQWL
VPP Hold from Valid SRD
5,8
0
0
0
ns
tQVPH
RP# VHH Hold from Valid
SRD
6,8
0
0
0
ns
tPHBR
Boot-Block Lock Delay
7,8
200
200
100
ns
NOTES:
See WE# Controlled Write Operations for notes 1 through 10.
11. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE# defines
the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be measured relative
to the CE# waveform.
PRODUCT PREVIEW
73
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 23. Extended Temperature Operations - Erase and Program Timings
5V ± 10%
VPP
VCC
2.7–3.6V
Parameter
Typ Ma
x
12V ± 5%
3.3 ±
0.3V
Typ Ma
x
5V ±
10%
Typ Ma
x
Boot/Parameter 0.88 TB
Block Erase
D
Time
0.84
7
0.8
7
Main Block
Erase Time
2.5 TB
D
2.4
14
1.9
14
Main Block
Write Time
(Byte Mode)
1.87
1.7
Main Block
Write Time
(Word Mode)
1.21
Byte Write
Time
Word Write
Time
2.7–3.6V
3.3 ±
0.3V
Typ Ma
x
5V ±
10%
Typ Ma Un
x
it
0.46 TB
D
0.44
7
0.34
7
s
1.36 TB
D
1.3
14
1.1
14
s
1.4
1.76
1.6
1.2
s
1.1
0.9
0.88
0.8
0.6
s
11
10
10
8.8
8
8
µs
14.3
13
13
8.8
8
8
µs
Typ Ma
x
NOTES:
1. All numbers are sampled, not 100% tested.
2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value independent ofCC
V and
VPP. See Note 3 for typical conditions.
3. Typical conditions are 25°C with VCC and VPP at the center of the specifed voltage range. Production programming using
VCC = 5.0V, VPP = 12.0V typically results in a 60% reduction in programming time.
4. Contact your Intel representative for information regarding maximum byte/word write specifications.
74
PRODUCT PREVIEW
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7.0
7.1
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
ADDITIONAL INFORMATION
Ordering Information
PRODUCT PREVIEW
75
E
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
E 2 8 F 8 0 0 CV - T 7 0
Access Speed
ns, BE: VCC = 2.7V
BV: VCC = 5V
T = Top Boot
B = Bottom Boot
Operating Temperature
T = Extended Temp
Blank = Commercial Temp
Package
E = TSOP
PA = 44-Lead PSOP
TB = Ext. Temp 44-Lead PSOP
Voltage Options (VPP/ VCC )
V = (5 or 12 / 3.3 or 5)
E = (5 or 12 / 2.7 or 5)
Product line designator
for all Intel Flash products
Architecture
B = Boot Block
C = Compact 48-Lead TSOP
Boot Block
Density / Organization
00X = x8-only (X = 1, 2, 4, 8)
X00 = x8/x16 Selectable (X = 2, 4, 8)
0530-23
VALID COMBINATIONS:
Commercial
Extended
40-Lead TSOP
E28F008BVT70
E28F008BVB70
E28F008BVT120
E28F008BVB120
44-Lead PSOP
PA28F800BVT70
PA28F800BVB70
PA28F800BVT120
PA28F800BVB120
TE28F008BVT90
TE28F008BVB90
TE28F008BET120
TE28F008BEB120
TB28F800BVT90
TB28F800BVB90
48-Lead TSOP
E28F800CVT70
E28F800CVB70
TE28F800CVT90
TE28F800CVB90
TE28F800CET120
TE28F800CEB120
Table 24. Summary of Line Items
Name
VCC
2.7–3.6
28F008
BV
28F800
BV
28F800
CV
28F008
BE
28F800
CE
76
VPP
Package
3.3±0.3
5 ± 10%
5 ± 10%
12 ± 5%
40-Ld
TSOP
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
44-Ld
PSOP
√
Temperature
48-Ld
TSOP
Comm
Ext
√
√
√
√
√
√
√
√
√
√
√
√
√
√
PRODUCT PREVIEW
E
7.2
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
References
Order
Number
Document
290531
2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290530
4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290448
28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet
290449
28F002/200BL-T/B 2-Mbit Low Power Boot Block Flash Memory
Datasheet
290450
28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory
Datasheet
290451
28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet
292148
AP-604 “Using Intel’s Boot Block Flash Memory Parameter Blocks to
Replace
EEPROM”
292172
AP-617 “Additional Flash Data Protection Using VPP, RP#, and WP#”
292130
AB-57 “Boot Block Architecture for Safe Firmware Updates”
292154
AB-60 “2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family”
7.3
Revision History
-001
Initial release of datasheet, no specifications included
-002
Explanation of WP# on 44-lead PSOP added; AC/DC Specifications
added, including BE product text and 2.7V specifications.
-003
28F800BE row removed from Table 1
Applying VCC voltages (Sections 5.1 and 6.1) rewritten for clarity.
Minor cosmetic changes/edits.
PRODUCT PREVIEW
77