LH52D1000 FEATURES • Access time: 85 ns (MAX.), 100 ns (MAX.) • Current consumption: Operating: 40 mA (MAX.) 6 mA (MAX.) (tRC, tWC = 1 µs) Standby: 45 µA (MAX.) CMOS 1M (128K × 8) Static Ram PIN CONNECTIONS 32-PIN TSOP 32-PIN STSOP TOP VIEW A11 1 32 OE A9 2 31 A10 A8 3 30 CE1 A13 4 29 I/O8 WE 5 28 I/O7 CE2 6 27 I/O6 A15 7 26 I/O5 VCC 8 25 I/O4 NC 9 24 GND • Operating temperature: -40°C to +85°C A16 10 23 I/O3 A14 11 22 • Fully-static operation I/O2 A12 12 21 I/O1 • Three-state output A7 13 20 A0 A6 14 19 A1 • Not designed or rated as radiation hardened A5 15 18 A2 A4 16 17 A3 • Data Retention: 1.0 µA (MAX. VCCDR = 3 V, tA = 25°C) • Single power supply: 2.7 V to 3.6 V • Packages: 32-pin 8 × 20 mm2 TSOP 32-pin 8 × 13.4 mm2 STSOP 52D1000S-1 Figure 1. Pin Connections for TSOP and STSOP Packages • N-type bulk silicon DESCRIPTION The LH52D1000 is a static RAM organized as 131,072 × 8 bits which provides low-power standby mode. It is fabricated using silicon-gate CMOS process technology. 1 CMOS 1M (128K × 8) Static RAM LH52D1000 A0 A1 A2 A3 20 8 VCC 19 18 24 GND A7 A8 A9 A10 A11 13 3 2 A12 A13 A14 A15 A16 12 4 11 7 17 A4 16 A5 15 A6 14 10 1024 ROW DECODER MEMORY CELL ARRAY (1024 x 128 x 8) ADDRESS BUFFER 128 x 8 31 1 7 COLUMN DECODER 128 COLUMN GATE 10 CE1 30 CE2 6 WE 5 OE 32 8 CE CONTROL LOGIC I/O BUFFER OE, WE CONTROL LOGIC 21 22 23 25 26 27 28 29 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 52D1000S-2 Figure 2. LH52D1000 Block Diagram PIN DESCRIPTION SIGNAL 2 PIN NAME SIGNAL PIN NAME A0 – A16 Address inputs I/O1 – I/O8 CE1 Chip enable 1 VCC Power supply CE2 Chip enable 2 GND Ground WE Write enable OE Output enable NC Data inputs and outputs No connection CMOS 1M (128K × 8) Static RAM LH52D1000 TRUTH TABLE CE1 CE2 WE OE MODE I/O1 – I/O 8 SUPPLY CURRENT NOTE H L Standby High impedance Standby (ISB ) 1 L H L Write Data input Active (ICC) 1 L H H L Read Data output Active (ICC) L H H H Output disable High impedance Active (ICC) NOTE: 1. = Don’t care L = Low H = High ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Supply voltage VCC -0.3 to +4.6 V 1 Input voltage VIN - 0.3 to VCC + 0.3 V 1, 2 Operating temperature TOPR -40 to +85 °C Storage temperature TSTG -55 to +1 50 °C NOTE: 1. The maximum applicable voltage on any pin with respect to GND. 2. Undershoot of -3.0 V is allowed width of pulse below 50 ns. RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C) PARAMETER Supply voltage Input voltage SYMBOL MIN. TYP. MAX. UNIT NOTE VCC 2.7 3.0 3.6 V VIH 2.0 VCC + 0.3 V VIL –0.3 0.6 V 1 NOTE: 1. Undershoot of –3.0 V is allowed width of pulse below 50 ns. DC ELECTRICAL CHARACTERISTICS (TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Input leakage current ILI VIN = 0 to VCC –1.0 1.0 µA Output leakage current ILO CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = 0 V to VCC –1.0 1.0 µA Operating supply current Standby current Output voltage ICC VIN = VIL or VIH, CE1 = VIL, WE = V IH CE2 = VIH, II/O = 0 mA tCYCLE = Min 40 ICC1 CE1 = 0.2 V, VIN = 0.2 V or VCC - 0.2 V CE2, WE = VCC - 0.2 V, II/O = 0 mA tCYCLE = 1.0 µs 6 ISB CE1 = VCC – 0.2 V or CE2 = 0.2 V 45 µA ISB1 CE1 = VIH or CE2 = VIL 2.0 mA mA VOL IOL = 2.1 mA 0.4 V VOH IOH = –0.5 mA VCC - 0.5 V 3 CMOS 1M (128K × 8) Static RAM LH52D1000 AC ELECTRICAL CHARACTERISTICS AC Test Conditions PARAMETER MODE NOTE 0.4 V to 2.4 V Input rise and fall time 5 ns Input and output timing Ref. level 1.5 V 100 pF + 1TTL 1 Input pulse level Output load NOTE: 1. Including scope and jig capacitance. READ CYCLE (TA = -40°C to +85°C, VCC = 2.7 V to 3.6 V) PARAMETER Read cycle time SYMBOL MIN. tRC 85 MAX. UNIT NOTE ns tAA 85 ns CE 1 access time tACE1 85 ns CE 2 access time tACE2 85 ns tOE 45 ns Output hold from address change tOH 10 ns CE 1 Low to output active tLZ1 5 ns 1 CE 2 High to output active tLZ2 5 ns 1 OE Low to output active tOLZ 0 ns 1 CE 1 High to output in High impedance tHZ1 0 35 ns 1 CE 2 Low to output in High impedance tHZ2 0 35 ns 1 OE High to output in High impedance tOHZ 0 35 ns 1 Address access time Output enable to output valid NOTE: 1. Active output to High impedance and High impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. WRITE CYCLE (TA = -40°C to +85°C, VCC = 2.7 V to 3.6 V) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Write cycle time tWC 85 ns CE 1 Low to end of write tCW1 75 ns CE 2 High to end of write tCW2 75 ns Address setup time tAS 0 ns Write pulse width tWP 60 ns Write recovery time tWR 0 ns Input data setup time tDW 35 ns Input data hold time tDH 0 ns WE High to output active tOW 0 ns 1 WE Low to output in High impedance tWZ 0 ns 1 OE High to output in High impedance tOHZ 0 35 ns 1 NOTE: 1. Active output to High impedance and High impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. 4 CMOS 1M (128K × 8) Static RAM LH52D1000 DATA RETENTION CHARACTERISTICS (TA = -40°C to +85°C) PARAMETER Data retention supply voltage Data retention supply current SYMBOL CONDITIONS MIN. TYP MAX. UNIT NOTE VCCDR CE2 ≤ 0.2 V or CE1 ≥ VCCDR – 0.2 V 2.0 3.6 V 1 TA = 25°C 1.0 1 3.0 35 µA TA = 40°C ICCDR VCCDR = 3.0 V CE2 ≤ 0.2 V or CE1 ≥ VCCDR – 0.2 V Chip enable setup time tCDR 0 ms Chip enable hold time tR 5 ms NOTE: 1. CE2 ≥ VCCDR – 0.2 V or CE2 ≤ 0.2 V 2. Typical values at TA = 25°C PIN CAPACITANCE (TA = 25°C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Input capacitance CIN VIN = 0 V 10 pF 1 I/O capacitance CI/O VI/O = 0 V 10 pF 1 NOTE: 1. This parameter is sampled and not production tested. 5 CMOS 1M (128K × 8) Static RAM LH52D1000 tRC ADDRESS tAA tACE1 CE1 tLZ1 tHZ1 CE2 tLZ2 tACE2 tHZ2 tOE OE tOLZ tOHZ tOH DATA VALID DOUT NOTE: WE is HIGH for Read cycle. 52D1000S-3 Figure 3. Read Cycle 6 CMOS 1M (128K × 8) Static RAM LH52D1000 tWC ADDRESS OE (NOTE 4) tWR tCW (NOTE 2) CE1 tWR tCW (NOTE 2) CE2 tWR tAS tWP (NOTE 3) (NOTE 1) WE tOHZ (NOTE 6) DOUT tDW tDH (NOTE 5) DATA VALID DIN NOTES: 1. A write occurs during the overlap of a LOW CE1, a HIGH CE2 and a LOW WE. A write begins at the latest transition among CE1 going LOW, CE2 going HIGH and WE going LOW. A write ends at the earliest transition among CE1 going HIGH, CE2 going LOW and WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE1 going LOW or CE2 going HIGH to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applies in case a write ends at CE1 or WE going HIGH. tWR2 applies in case a write ends at CE2 going LOW. 5. During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. If CE1 goes LOW simultaneously with WE going LOW or after WE going LOW, the outputs remain in high impedance state. 7. If CE1 goes HIGH simulaneously with WE going HIGH or before WE going HIGH, the outputs remain in high impedance state. 52D1000S-4 Figure 4. Write Cycle (OE Controlled) 7 CMOS 1M (128K × 8) Static RAM LH52D1000 tWC ADDRESS tWR tCW (NOTE 4) (NOTE 2) CE1 tWR tCW (NOTE 2) CE2 tWR tAS tWP (NOTE 3) (NOTE 1) WE (NOTE 6) tWZ tOW (NOTE 7) DOUT tDW DIN (NOTE 5) tDH DATA VALID NOTES: 1. A write occurs during the overlap of a LOW CE1, a HIGH CE2 and a LOW WE, A write begins at the latest transition among CE1 going LOW, CE2 going HIGH and WE going LOW. A write ends at the earliest transition among CE1 going HIGH. CE2 going LOW and WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE1 going LOW or CE2 going HIGH to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applies in case a write ends at CE1 or WE going HIGH. tWR2 applies in case a write ends at CE2 going LOW. 5. During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. If CE1 goes LOW simultaneously with WE going LOW or after WE going LOW, the outputs remain in high impedance state. 7. If CE1 goes HIGH simulaneously with WE going HIGH or before WE going HIGH, the outputs remain in high impedance state. 52D1000S-5 Figure 5. Write Cycle (OE Low Fixed) 8 CMOS 1M (128K × 8) Static RAM LH52D1000 CE1 CONTROL (NOTE) DATA RETENTION MODE VCC 2.7 V tCDR tR 2.2 V VCCDR CE1 ≥ VCCDR - 0.2 V CE1 0V CE2 CONTROL DATA RETENTION MODE VCC 2.7 V tR tCDR CE2 VCCDR 0.6 V 0V CE2 ≤ 0.2 V NOTE: To control the data retention mode at CE1, fix the input level of CE2 between VCCDR and VCCDR - 0.2 V or 0 V to 0.2 V during the data retention mode. 52D1000S-6 Figure 6. Data Retention (CE1 Controlled) 9 CMOS 1M (128K × 8) Static RAM LH52D1000 PACKAGE DIAGRAM 32TSOP (Type I) (TSOP032-P-0820) 0.30 [0.012] 0.10 [0.004] 0.50 [0.020] TYP. 32 17 18.60 [0.732] 18.20 [0.717] 1 20.30 [0.799] 19.70 [0.776] 19.00 [0.748] 16 8.20 [0.323] 7.80 [0.307] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] DIMENSIONS IN MM [INCHES] 10 MAXIMUM LIMIT MINIMUM LIMIT 32TSOP CMOS 1M (128K × 8) Static RAM LH52D1000 1 0.10 [0.004] 0.08 [0.003] M 32TSOP (TSOP032-P-0813) 0.50 [0.020] 17 16 8.40 [0.331] MAX. 0.22 [0.009] 8.10 [0.319] 7.90 [0.311] 32 0.25 [0.010] TYP. 11.90 [0.468] 11.70 [0.461] 0.15 [0.006] 0.05 [0.002] 1.10 [0.043] 0.90 [0.035] 13.60 [0.535] 13.20 [0.520] 1.20 [0.047] MAX. SEE DETAIL DETAIL 0.20 [0.008] 0.90 [0.003] 0° - 10° 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32STSOP 11 CMOS 1M (128K × 8) Static RAM LH52D1000 ORDERING INFORMATION LH52D1000 Device Type X Package - ## Speed LL Power Low-Low power standby 10 100 Access Time (ns) 85 85 T 32-pin, 8 mm x 20 mm2 TSOP (TSOP32-P-0820) S 32-pin, 8 mm x 13 mm2 STSOP (STSOP32-P-0813) CMOS 1M (124K x 8) Static RAM Example: LH52D1000T-85LL (CMOS 1M (124K x 8) Static RAM, 85 ns, Low-Low power standby, 32-pin TSOP) 52D1000S-7 12