SHARP LH51BV1000J

LH51BV1000J
FEATURES
CMOS 1M (128K × 8) Static Ram
PIN CONNECTIONS
• Access time: 70 ns (MAX.)
• Current consumption:
Operating: 30 mA (MAX.)
5 mA (MAX.) (tRC, tWC = 1 µs)
Standby: 60 µA (MAX.)
• Data Retention:
1.0 µA (MAX.) (VCCDR = 3 V, TA = 25°C)
• Single power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Fully-static operation
• Three-state output
1
2
3
A
A2
A3
B
I/O1
A0
C
GND
D
6
7
8
A1
NC
A4
A5
I/O2
A12
A6
A7
I/O3
A14
A16
I/O4
I/O5
A15
VCC
E
I/O7
I/O8 I/O6
CE2
A13
WE
F
A10
OE
A8
A11
A9
CE1
4
5
51BV1000-1
Figure 1. Pin Connections for CSP Package
• Not designed or rated as radiation
hardened
• Package: 32-pin 6 × 10 mm CSP
• N-type bulk silicon
DESCRIPTION
The LH51BV1000JY is a static RAM organized as
131,072 × 8 bits which provides low power standby
mode. It is fabricated using silicon-gate CMOS process
technology.
1
CMOS 1M (128K × 8) Static RAM
LH51BV1000J
VCC
A0
A1
A2
A3
GND
10
A4
A5
A6
A7
A8
A9
A10
A11
1024
ROW
DECODER
MEMORY
CELL ARRAY
(1024 x 128 x 8)
ADDRESS
BUFFER
128 x 8
7
A12
A13
A14
A15
A16
COLUMN
DECODER
128
COLUMN GATE
8
CE1
CE1, CE2
CONTROL
LOGIC
CE2
WE
I/O BUFFER
OE, WE
CONTROL
LOGIC
OE
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
51BV1000-2
Figure 2. LH51BV1000JY Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A0 – A16
Address inputs
I/O1 – I/O8
CE1
Chip enable 1
VCC
Power supply
CE2
Chip enable 2
GND
Ground
WE
Write enable
OE
Output enable
NC
Data inputs and outputs
No connection
TRUTH TABLE
CE1
CE2
WE
OE
MODE
I/O 1 – I/O8
SUPPLY CURRENT
H



Standby
High impedance
Standby (ISB)

L


Standby
High impedance
Standyby (ISB)
L
H
L

Write
Data input
Active (ICC)
L
H
H
L
Read
Data output
Active (ICC)
L
H
H
H
Output disable
High impedance
Active (ICC)
NOTE:
1.  = Don’t care, L = Low, H = High
2
CMOS 1M (128K × 8) Static RAM
LH51BV1000J
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Supply voltage
VCC
– 0.5 to +4.6
V
1
Input voltage
VIN
– 0.5 to VCC + 0.3
V
1, 2
Operating temperature
TOPR
– 25 to +85
°C

Storage temperature
TSTG
– 65 to +150
°C

NOTE:
1. The maximum applicable voltage on any pin with respect to GND.
2. Undershoot of –3.0 V is allowed width of pulse below 50 ns.
RECOMMENDED OPERATING CONDITIONS (TA = -25°C to +85°C)
PARAMETER
Supply voltage
Input voltage
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
VCC
2.7
VIH
2.2
3.0
3.6
V


VCC + 0.3
V
VIL
–0.3


0.4
V
1
NOTE:
1. Undershoot of –3.0 V is allowed width of pulse below 50 ns.
DC ELECTRICALCHARACTERISTICS (TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V)
SYMBOL
CONDITIONS
MIN.
TYP.1
MAX.
UNIT
Input leakage
current
ILI
VIN = 0 V to VCC
–1.0

1.0
µA
Output leakage
current
ILO
CE1 = VIH or CE2 = VIL or
OE = VIH or WE = VIL
VI/O = 0 V to VCC
–1.0

1.0
µA
PARAMETER
Operating supply
current
Standby current
ICC1
CE1 = VIL, VIN = VIL or VIH
CE2 = VIH, II/O = 0 mA
tCYCLE =
MIN.


30
ICC2
CE1 = VIL, VIN = VIL or VIH
CE2 = VIH, II/O = 0 mA
tCYCLE =
1.0 µs


5
ISB
CE1, CE2 ≥ VCC – 0.2 V or CE2 ≤ 0.2 V

0.6
60
µA
ISB1
CE1 = V IH or CE2 = VIL


1.0
mA
VOL
IOL = 2.0 mA, VCC ≥ 3 V
0.4
IOL = –0.1 mA


0.2
IOH = – 2. 0 m A, V CC ≥ 3 V
2.4


IOH = –0.1 mA
VCC – 0.2


Output voltage
VOH
mA
V
NOTE:
1 Typical values at VCC = 5.0 V, TA = 25°C
AC ELECTRICAL CHARACTERISTICS
AC Test Conditions
PARAMETER
Input pulse level
Input rise and fall time
Input and output timing ref. level
Output load
MODE
NOTE
0.4 V to 2.4 V

5 ns

1.5 V

1 TTL + CL (100 pF)
1
NOTE:
1. Including scope and jig capacitance.
3
CMOS 1M (128K × 8) Static RAM
LH51BV1000J
READ CYCLE (TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V)
PARAMETER
Read cycle time
SYMBOL
MIN.
MAX.
UNIT
NOTE
tRC
70

ns

tAA

70
ns

CE 1 access time
tACE1

70
ns

CE 2 access time
tACE2

70
ns

tOE

40
ns

Output hold from address change
tOH
10

ns

CE 1 Low to output active
tLZ1
5

ns
1
CE 2 High to output active
tLZ2
5

ns
1
OE Low to output active
tOLZ
0

ns
1
CE 1 High to output in High impedance
tHZ1

30
ns
1
CE 2 Low to output in High impedance
tHZ2

30
ns
1
OE High to output in High impedance
tOHZ

30
ns
1
Address access time
Output enable to output valid
NOTE:
1. Active output to High impedance to output active tests specified for a
±200 mV transition from steady state levels into the test load.
WRITE CYCLE (TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Write cycle time
tWC
70

ns

Chip enable to end of write
tCW
60

ns

Address valid to end of write
tAW
60

ns

Address setup time
tAS
0

ns

Write pulse width
tWP
55

ns

Write recovery time
tWR
0

ns

Input data setup time
tDW
30

ns

Input data hold time
tDH
0

ns

WE High to output active
tOW
5

ns
1
WE Low to output in High impedance
tWZ

30
ns
1
OE High to output in High impedance
tOHZ

30
ns
1
NOTE:
1. Active output to High impedance to output active tests specified for a
±200 mV transition from steady state levels into the test load.
4
CMOS 1M (128K × 8) Static RAM
LH51BV1000J
DATA RETENTION CHARACTERISTICS (TA = -25°C to +850°C)
PARAMETER
Data retention
supply voltage
Data retention
supply current
SYMBOL
CONDITIONS
MIN.
TYP.1
MAX.
UNIT
NOTES
VCCDR
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR - 0.2 V
2.0

3.6
V
2
TA = 25°C

0.5
1.0
µA

TA = 40°C


3.0




50
µA
2
ICCDR
VCCDR = 3 V
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR - 0.2 V
Chip enable
setup time
tCDR

0


ms

Chip enable
hold time
tR

5


ms

NOTES:
1. Typical value at TA = 25°C
2. CE2 ≥ VCCDR - 0.2 V or CE2 ≤ 0.2 V
PIN CAPACITANCE (TA = 25°C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Input capacitance
CIN
VIN = 0 V


8
pF
1
I/O capacitance
CI/O
VI/O = 0 V


10
pF
1
NOTE:
1. This parameter is sampled and not production tested.
5
CMOS 1M (128K × 8) Static RAM
LH51BV1000J
tRC
ADDRESS
tAA
tACE1
CE1
tLZ1
tHZ1
CE2
tLZ2
tACE2
tHZ2
tOE
OE
tOLZ
tOHZ
tOH
DATA VALID
DOUT
NOTE: WE is HIGH for Read cycle.
51BV1000-3
Figure 3. Read Cycle
6
CMOS 1M (128K × 8) Static RAM
LH51BV1000J
tWC
ADDRESS
OE
(NOTE 4)
tAW
tWR
tCW
(NOTE 2)
CE1
tCW
tWR
(NOTE 2)
CE2
tWR
tAS
tWP
(NOTE 3)
(NOTE 1)
WE
tOHZ
(NOTE 6)
DOUT
tDW
tDH
(NOTE 5)
DATA VALID
DIN
NOTES:
1. A write occurs during the overlap of a LOW CE1, a HIGH CE2 and a LOW WE,
A write begins at the latest transition among CE1 going LOW, CE2 going HIGH
and WE going LOW. A write ends at the earliest transition among CE1 going
HIGH, CE2 going LOW and WE going HIGH. tWP is measured from the beginning
of write to the end of write.
2. tCW is measured from the latter of CE1 going LOW or CE2 going HIGH to the
end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR1 applies
in case a write ends at CE1 or WE going HIGH. tWR2 applies in case a write
ends at CE2 going LOW.
5. During this period, I/O pins are in the output state, therefore the input signals
of opposite phase to the outputs must not be applied.
6. If CE1 goes LOW simultaneously with WE going LOW or after WE going LOW,
the outputs remain in high impedance state.
7. If CE1 goes HIGH simulaneously with WE going HIGH or before WE going HIGH,
the outputs remain in high impedance state.
51BV1000-4
Figure 4. Write Cycle (OE Controlled)
7
CMOS 1M (128K × 8) Static RAM
LH51BV1000J
tWC
ADDRESS
tAW
tWR
tCW
(NOTE 4)
(NOTE 2)
CE1
tWR
tCW
(NOTE 2)
CE2
tWR
tAS
tWP
(NOTE 3)
(NOTE 1)
WE
(NOTE 6)
tWZ
tOW
(NOTE 7)
DOUT
tDW
DIN
(NOTE 5)
tDH
DATA VALID
NOTES:
1. A write occurs during the overlap of a LOW CE1, a HIGH CE2 and a LOW WE,
A write begins at the latest transition among CE1 going LOW, CE2 going HIGH
and WE going LOW. A write ends at the earliest transition among CE1 going
HIGH. CE2 going LOW and WE going HIGH. tWP is measured from the beginning
of write to the end of write.
2. tCW is measured from the latter of CE1 going LOW or CE2 going HIGH to the
end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR1 applies
in case a write ends at CE1 or WE going HIGH. tWR2 applies in case a write
ends at CE2 going LOW.
5. During this period, I/O pins are in the output state, therefore the input signals
of opposite phase to the outputs must not be applied.
6. If CE1 goes LOW simultaneously with WE going LOW or after WE going LOW,
the outputs remain in high impedance state.
7. If CE1 goes HIGH simulaneously with WE going HIGH or before WE going HIGH,
the outputs remain in high impedance state.
51BV1000-5
Figure 5. Write Cycle (OE Low Fixed)
8
CMOS 1M (128K × 8) Static RAM
LH51BV1000J
CE1 CONTROL (NOTE)
DATA RETENTION MODE
VCC
2.7 V
tCDR
tR
2.2 V
VCCDR
CE1 ≥ VCCDR - 0.2 V
CE1
0V
CE2 CONTROL
DATA RETENTION MODE
VCC
2.7 V
tR
tCDR
CE2
VCCDR
0.4 V
0V
CE2 ≤ 0.2 V
NOTE: To control the data retention mode at CE1, fix the input level of CE2
between VCCDR and VCCDR - 0.2 V or 0 V and 0.2 V during the data retention mode.
51BV1000-6
Figure 6. Data Retention Chart
(CE1 Controlled)
9
CMOS 1M (128K × 8) Static RAM
LH51BV1000J
PACKAGE DIAGRAM
32CSP (FBGA032-P-0610)
B
INDEX
TOP
VIEW
6.20 [0.244]
6.00 [0.236]
A
SIDE
VIEW
S
DETAIL
0.30 [0.012]
TYP. (NOTE)
1.20 [0.047]
MAX.
0.10 [0.004] S
0.67 [0.026]
TYP.
10.20 [0.402]
10.00 [0.394]
(See Detail)
0.10 [0.004] S
C
0.20 [0.008]
MIN.
0.80 [0.031]
TYP.
1.20 [0.047]
TYP.
BOTTOM
VIEW
0.80 [0.031]
TYP.
D
0.40 [0.016]
TYP.
φ0.35 [0.014]
0.30 [0.012] M
S
AB
0.15 [0.006] M
S
CD
NOTE: Land hole diameter for ball mounting.
DIMENSIONS IN MM [INCHES]
10
MAXIMUM LIMIT
MINIMUM LIMIT
32CSP
CMOS 1M (128K × 8) Static RAM
LH51BV1000J
ORDERING INFORMATION
LH51BV1000J
Device Type
Y
Package
- ##
Speed
LL
Power
Low-Low power standby
70 ns Access Time (ns)
32-pin, 6 x 10 mm CSP (FBGA032-P-0610)
CMOS 1M (124K x 8) Static RAM
Example: LH51BV1000JY-70LL (CMOS 1M (124K x 8) Static RAM, 70 ns, Low-Low power standby, 32-pin CSP)
51BV1000-7
11