LH5116/H CMOS 16K (2K × 8) Static RAM FEATURES DESCRIPTION • 2,048 × 8 bit organization The LH5116/H are static RAMs organized as 2,048 × 8 bits. It is fabricated using silicon-gate CMOS process technology. It features high speed access in read mode using output enable (tOE). • Access time: 100 ns (MAX.) • Power consumption: Operating: 220 mW (MAX.) Standby: 5.5 µW (MAX.) • Single +5 V power supply • Fully-static operation • TTL compatible I/O • Three-state outputs • Wide temperature range available LH5116H: -40 to +85°C • Packages: 24-pin, 600-mil DIP 24-pin, 300-mil SK-DIP 24-pin, 450-mil SOP PIN CONNECTIONS TOP VIEW 24-PIN DIP 24-PIN SK-DIP 24-PIN SOP A7 1 24 A6 2 23 A8 22 A9 Vcc A5 3 A4 4 21 WE A3 5 20 OE A2 6 19 A10 A1 7 18 CE A0 8 17 I/O8 I/O1 9 16 I/O7 I/O2 10 15 I/O6 I/O3 11 14 I/O5 GND 12 13 I/O4 5116-1 Figure 1. Pin Connections for DIP, SK-DIP, and SOP Packages 1 CMOS 16K (2K × 8) Static RAM ROW ADDRESS BUFFERS A0 8 A5 3 A6 2 ROW DECODERS LH5116/H A7 1 A8 23 A9 22 A10 19 24 VCC MEMORY CELL ARRAY (128 x128) 12 GND CE DATA CONTROL I/O1 9 I/O2 10 I/O3 11 I/O4 13 I/O5 14 I/O6 15 I/O7 16 I/O8 17 COLUMN I/O CIRCUIT COLUMN DECODERS COLUMN ADDRESS BUFFERS CE CE 18 WE 21 OE 20 4 A4 5 A3 6 A2 7 A1 5116-2 Figure 2. LH5116/H Block Diagram PIN DESCRIPTION SIGNAL PIN NAME A0 - A10 SIGNAL Address input I/O1 - I/O8 PIN NAME Data input/output CE Chip Enable input VCC Power supply OE Output Enable input GND Ground WE Write Enable input TRUTH TABLE CE OE MODE I/O1 - I/O8 SUPPLY CURRENT NOTE 1 L X L Write DIN Operating (ICC) L L H Read DOUT Operating (ICC) H X X Deselect High-Z Standby (ISB ) 1 L H X Outputs disable High-Z Operating (ICC) 1 NOTE: 1. X = H or L 2 WE CMOS 16K (2K × 8) Static RAM LH5116/H ABSOLUTE MAXIMUM RATINGS SYMBOL RATING UNIT NOTE Supply voltage Input voltage PARAMETER VCC VIN V V Operating temperature Topr 1 1 2 3 Storage temperature Tstg -0.3 to +7.0 -0.3 to VCC + 0.3 0 to +70 -40 to +85 -55 to +150 °C °C NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. Applied to the LH5116/D/NA 3. Applied to the LH5116H/HD/HN RECOMMENDED OPERATING CONDITIONS 1 PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC VIH VIL 4.5 2.2 -0.3 5.0 5.5 VCC + 0.3 0.8 V V V Supply voltage Input voltage NOTE: 1. TA = 0 to 70°C (LH5116/D/NA), TA = -40 to +85°C (LH5116H/HD/HN) DC CHARACTERISTICS 1 (VCC = 5 V ±10%) PARAMETER SYMBOL CONDITIONS MIN. Output ‘LOW’ voltage Output ‘HIGH’ voltage Input leakage current Output leakage current VOL VOH ILI ILO Operating current ICC1 ICC2 IOL = 2.1 mA IOH = -1.0 mA VIN = 0 V to VCC CE = VIH, VI/O = 0 V to VCC Outputs open (OE = VCC) Outputs open (OE = VIH) Standby current ISB TYP. 2.4 -1.0 -1.0 MAX. UNIT 0.4 V V µA 1.0 1.0 30 40 1.0 0.2 25 30 CE ≥ VCC - 0.2 V All other input pins = 0 V to VCC µA mA mA µA NOTE 2 3 4 NOTES: 1. TA = 0 to 70°C (LH5116/D/NA), TA = -40 to +85°C (LH5116H/HD/HN) 2. CE = 0 V; all other input pins = 0 V to VCC 3. CE = VIL; all other input pins = VIL to VIH 4. TA = 25°C AC CHARACTERISTICS 1 (1) READ CYCLE (VCC = 5 V ±10%) PARAMETER SYMBOL MIN. Read cycle time Address access time Chip enable access time Chip enable Low to output in Low-Z Output enable access time Output enable Low to output in Low-Z Chip disable to output in High-Z Output disable to output in High-Z Output hold time tRC tAA tACE tCLZ tOE tOLZ tCHZ tOHZ tOH 100 TYP. MAX. 100 100 10 40 10 0 0 10 40 40 UNIT NOTE ns ns ns ns ns ns ns ns ns 2 2 2 2 NOTES: 1. TA = 0 to 70°C (LH5116/NA/D). TA = -40 to 85°C (LH5116H/HD/HN). 2. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. 3 CMOS 16K (2K × 8) Static RAM LH5116/H (2) WRITE CYCLE 1 (VCC = 5 V ±10%) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Write cycle time tWC 100 ns Chip enable to end of write tCW 80 ns Address valid time tAW 80 ns Address setup time tAS 0 ns Write pulse width tWP 60 ns Write recovery time tWR 10 ns Output active from end of write tOW 10 WE Low to output in High-Z tWHZ 0 Data valid to end of write tDW 30 Data hold time tDH 10 Output enable to output in High-Z tOHZ 0 Output active from end of write tOW 10 30 NOTE ns 2 ns 2 ns ns 40 ns 2 ns 2 NOTES: 1. TA = 0 to +70°C (LH5116/D/NA), TA = -40 to +85°C (LH5116H/HD/HN) 2. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. AC TEST CONDITIONS PARAMETER MODE Input voltage amplitude NOTE 0.8 V to 2.2 V Input rise/fall time 10 ns Timing reference level 1.5 V Output load condition 1TTL + CL (100 pF) 1 NOTE: 1. Includes scope and jig capacitance. DATA RETENTION CHARACTERISTICS 1 PARAMETER SYMBOL CONDITIONS MIN. Data retention voltage VCCDR CE ≥ VCCRC - 0.2 V 2.0 Data retention current ICCDR CE ≥ VCCDR - 0.2 V, VCCDR = 2.0 V Chip disable to data retention Recovery time TYP. MAX. UNIT 5.5 V 1.0 µA 0.2 tCDR 0 ns tR tRC ns NOTES: 1. TA = 0 to +70°C (LH5116/D/NA), TA = -40 to +85°C (LH5116H/HD/HN) 2. TA = 25°C 3. t RC = Read cycle time CAPACITANCE 1 (f = 1 MHz, TA = 25°C) PARAMETER SYMBOL CONDITIONS Input capacitance CIN MAX. UNIT VIN = 0 V 7 pF Input/output capacitance CI/O VI/O = 0 V 10 pF NOTE: 1. This parameter is sampled and not production tested. 4 MIN. TYP. NOTE 2 3 CMOS 16K (2K × 8) Static RAM LH5116/H tCDR tR DATA RETENTION MODE VCC 4.5 V 2.2 V VCCDR CE ≥ VCCDR -0.2 V CE 0V 5116-6 Figure 3. Low Voltage Data Retention tRC A0 - A10 tAA tOH tACE CE tOE tCHZ OE tOLZ tOHZ tCLZ DOUT DATA VALID NOTE: WE = "HIGH" 5116-3 Figure 4. Read Cycle 5 CMOS 16K (2K × 8) Static RAM LH5116/H tWC A0 - A10 tWR (NOTE 3) tAW tCW CE tAS tWP (NOTE 2) WE tWHZ tOW (NOTE 4) (NOTE 5) DOUT tDW tDH (NOTE 6) DIN OE = 'LOW' NOTES: 1. WE must be HIGH when there is a change in A0 - A10. 2. When CE and WE are both LOW at the same time, write occurs during the period tWP. 3. tWR is the time from the rise of CE or WE, whichever is first, to the end of the write cycle. 4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 5. DOUT outputs data with the same logic level as the input data of this write cycle. 6. If CE is LOW during this period, the input/output pin is in the output state. During this state, input signals of opposite logic level must not be applied. 5116-4 Figure 5. Write Cycle 1 tWC A0 - A10 (NOTE 3) tWR tAW OE tCW CE tAS tWP (NOTE 2) WE tOLZ tOHZ tOW (NOTE 5) DOUT tDW tDH (NOTE 4) (NOTE 6) DIN NOTES: 1. WE must be HIGH when there is a change in A0 - A10. 2. When CE and WE are both LOW at the same time, write occurs during the period tWP. 3. tWR is the time from the rise of CE or WE, whichever is first, to the end of the write cycle. 4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 5. DOUT outputs data with the same logic level as the input data of this write cycle. 6. If CE is LOW during this period, the input/output pins are in the output state. During this state, input signals of opposite logic level must not be applied. Figure 6. Write Cycle 2 6 5116-5 CMOS 16K (2K × 8) Static RAM LH5116/H ACCESS TIME tAA, tACE (RELATIVE VALUE) ACCESS TIME tAA, tACE (RELATIVE VALUE) ACCESS TIME VS. SUPPLY VOLTAGE 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 1.1 1.0 0.9 0.8 6.0 0 75 100 AVERAGE SUPPLY CURRENT VS. SUPPLY VOLTAGE AVERAGE SUPPLY CURRENT VS. AMBIENT TEMPERATURE AVERAGE SUPPLY CURRENT ICC (mA) 25 15 10 5 4.0 20 15 10 5 4.5 5.0 5.5 6.0 0 SUPPLY VOLTAGE VCC (V) INPUT VOLTAGE VS. SUPPLY VOLTAGE 2.0 VIH 1.5 VIL 1.0 0.5 4.0 25 50 75 100 AMBIENT TEMPERATURE TA (°C) INPUT VOLTAGE VS. AMBIENT TEMPERATURE 2.5 INPUT VOLTAGE VIH, VIL (V) INPUT VOLTAGE VIH, VIL (V) 50 AMBIENT TEMPERATURE TA (°C) 20 2.5 25 SUPPLY VOLTAGE VCC (V) 25 AVERAGE SUPPLY CURRENT ICC (mA) ACCESS TIME VS. AMBIENT TEMPERATURE 1.2 2.0 1.5 VIH VIL 1.0 0.5 4.5 5.0 5.5 SUPPLY VOLTAGE VCC (V) 6.0 0 25 50 75 100 AMBIENT TEMPERATURE TA (°C) 5116-7 Figure 7. Electrical Characteristic Curves (VCC = 5 V, TA = 25°C unless otherwise specified) 7 CMOS 16K (2K × 8) Static RAM LH5116/H PACKAGE DIAGRAMS 24DIP (DIP024-P-0600) DETAIL 24 13 13.45 [0.530] 12.95 [0.510] 0° TO 15° 0.30 [0.012] 0.20 [0.008] 1 12 31.30 [1.232] 30.70 [1.209] 4.45 [0.175] 4.05 [0.159] 15.24 [0.600] TYP. 5.30 [0.209] 4.90 [0.193] 3.45 [0.136] 3.05 [0.120] 0.51 [0.020] MIN 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 24DIP-2 24-pin, 600-mil DIP 24SDIP (SDIP024-P-0300) DETAIL 24 13 6.55 [0.258] 6.15 [0.242] 1 0° TO 15° 12 0.30 [0.012] 0.20 [0.008] 22.25 [0.876] 21.75 [0.856] 3.65 [0.144] 3.25 [0.128] 7.62 [0.300] TYP. 4.40 [0.173] 4.00 [0.157] 3.45 [0.136] 3.05 [0.120] 1.778 [0.070] TYP. 0.51 [0.020] MIN 0.56 [0.022] 0.36 [0.014] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 24SDIP 24-pin, 300-mil SK-DIP 8 CMOS 16K (2K × 8) Static RAM LH5116/H 24SOP (SOP024-P-0450B) 0.50 [0.120] 0.30 [0.012] 1.27 [0.050] TYP. 1.70 [0.067] 24 13 8.80 [0.346] 12.40 [0.488] 8.40 [0.331] 11.60 [0.457] 1 10.60 [0.417] 12 1.70 [0.067] 15.60 [0.614] 15.20 [0.598] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 24SOP 24-pin, 450-mil SOP 9 CMOS 16K (2K × 8) Static RAM LH5116/H ORDERING INFORMATION (TA = 0°C to 70°C) LH5116 Device Type X Package - ## Speed 10 100 Access Time (ns) Blank 24-pin, 600-mil DIP (DIP024-P-0600) D 24-pin, 300-mil SK-DIP (DIP024-P-0300) N 24-pin, 450-mil SOP (SOP024-P-0450B) CMOS 16K (2K x 8) Static RAM Example: LH5116N-10 (CMOS 16K (2K x 8) Static RAM, 100 ns, 24-pin, 450-mil SOP) 5116-8 ORDERING INFORMATION (TA = -40°C to +85°C) LH5116H Device Type X Package - ## Speed 10 100 Access Time (ns) Blank 24-pin, 600-mil DIP (DIP024-P-0600) D 24-pin, 300-mil SK-DIP (DIP024-P-0300) N 24-pin, 450-mil SOP (SOP024-P-0450B) CMOS 16K (2K x 8) Static RAM Example: LH5116HN-10 (CMOS 16K (2K x 8) Static RAM, 100 ns, 24-pin, 450-mil SOP) 5116-9 10