LMH6678 Low Power 2-Channel Central-Office xDSL Driver General Description Features The LMH6678 is a low power 2-channel differential output driver utilizing dual current feedback op amps with a fixed gain of AV = +5.4. AVCC1 = AVCC2 = +12V, AVDD = DVDD = +3.3V, TA = 25˚C, 2/3 Power Mode, Typical values unless specified. n Low power consumption — Line power PLINE = 100 mW 580 mW/Ch — No signal 185 mW/Ch — Listen mode 100 mW/Ch — Shutdown mode 3 mW/Ch n Power Supply +12V — Analog (AVCC1, AVCC2) +3.3V — Digital (DVDD, AVDD) n Output voltage swing @ RL = 31Ω — Single ended 11.5 VPP — Differential 23 VPP n Multi tone power ratio, f = 500 kHz 72 dB n Output current 580 mA n Thermal shutdown protection n 5mm x 4mm LLP package n Low thermal resistance 36˚C/W (θJA) n Small PCB footprint The LMH6678 utilizes high integration with low power consumption to provide 580 mW at 19.8 dBm line output. The LMH6678 can also be put into a listen mode to maintain the termination for receive signals with 100 mW/Ch power dissipation. The LMH6678 has two separate 2-bit power control inputs compatible with 3.3V CMOS for each channel that enable independent control of line status. When the drivers for both channels are shut off, power consumption drops to only 6 mW. Thermal Shutdown function protects the IC from a shorted line fault or system over temperature. The LMH6678 is available in a 5mm x 4mm 24-lead LLP package. Application n Full rate ADSL, ADSL+, ADSL++ or G. Lite linecard n Remote DSLAMs Block Diagram 20084037 © 2003 National Semiconductor Corporation DS200840 www.national.com LMH6678 Low Power 2-Channel Central-Office xDSL Driver December 2003 LMH6678 Absolute Maximum Ratings (Note 1) Digital Control Input If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Soldering Information ESD Tolerance Storage Temperature Range Human Body Model Infrared or Convection (20 sec.) 2KV (Note 2) Machine Model DVDD +0.8V, DGND −0.8V 235˚C −65˚C to +150˚C Junction Temperature (Note 4) +150˚C 200V (Note 8) ± 3V VIN Differential Operating Ratings (Note 1) Supply Voltages Supply Voltage AVCC1 – AGND or AVCC2– AGND +12V ± 10% +13.2V AVCC1 to AGND +3.6V AVCC2 to AGND +12V ± 10% AVDD – AGND +3.6V DVDD to DGND +3.3V ± 10% DGND − AGND ± 0.2V ± 0.2V ± 0.2V AVDD to AGND +3.3V ± 10% DVDD – DGND AVCC1 – AVCC2 AVDD – DVDD Operating Temperature Range (Note 3), (Note 4) Package Thermal Resistance (θJA) (Note 4) Voltage at Input Pin Analog Input −40˚C to +85˚C AVCC1 (AVCC2) +0.8V, AGND −0.8V 36˚C/W Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C, AVCC1 = AVCC2 = +12V, DVDD = AVDD = +3.3V. DGND = AGND = 0V, 2/3 Power Mode. See (Note 9). Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units Dynamic Performance fCL −3 dB BW RL = 100Ω 50 MHZ SR Slew Rate (Note 7) VIN_DIFF = ± 2.4V, RL = 100Ω 700 V/µs fc = 1 MHz, VO = 2 VPP, RL = 31Ω −91 fc = 200 kHz, VO = 2 VPP, RL = 31Ω −98 Distortion and Noise Response HD2 HD3 2nd Harmonic Distortion 3rd Harmonic Distortion fc = 1 MHz, VO = 2 VPP, RL = 31Ω −57 fc = 200 kHz, VO = 2 VPP, RL = 31Ω −71 MTPR Multi-Tone Power Ratio f = 500 kHz 72 VIN Differential Output Noise 100 kHz to 10 MHz 57 dBc dBc dBc nV/ Input Characteristics VIN Input DC Voltage Common Mode 6.04 6.1 6.16 V RIN Input Resistance Differential IDIFF = 10 µA from +IN to −IN 14.4 20 28.4 kΩ VIN_DIFF = −1 to 1V, No Load +5.37 +5.40 +5.48 V/V Transfer Characteristics AV Voltage Gain PSRR Power Supply Rejection Ratio Xt Cross Talk f = 1 MHz, RL = 100Ω VO Output Voltage Swing High VIN_DIFF = ± 2.4V, No Load −108 VIN_DIFF = ± 2.4V, RL = 31Ω VIN_DIFF = Output Voltage Swing Low VIN_DIFF = VIN_DIFF = VIN_DIFF = ISC Output Short Circuit Current www.national.com ± 2.4V, IOUT = 580 mA ± 2.4V, No Load ± 2.4V, RL = 31Ω ± 2.4V, IOUT = 580 mA −95 11.85 11.68 11.75 11.64 11.74 V 0.15 0.25 0.36 0.31 0.39 Sourcing to Ground +800 Sinking to Ground −800 2 dB V mA Symbol Parameter Conditions Min (Note 6) VIN_DIFF = ± 2.4V Sourcing, RL = 20Ω Sinking, RL = 20Ω Typ (Note 5) Max (Note 6) Units ± 580 IOUT Output Current mA VOC Output Common Mode Voltage 5.89 6 6.05 V VOS Output Offset Voltage −40 0 +40 mV Power Supply (Note 10), (Note 11) ICC B01 B11 B02 B12 Full Power AVCC Quiescent Supply Current L L L L 28.6 33 36.9 2/3 Power H L H L 18.6 22 25.4 1/3 Power L H L H 9.2 12 14.3 0.2 .95 19 Shutdown IDV H H H H B01 B11 B02 B12 Full Power L L L L 11 16 2/3 Power H L H L 7 12 15 1/3 Power L H L H 3 7 10.3 H H H H DVDD Quiescent Supply Current Shutdown IAV AVDD Quiescent Supply Current All Power Modes 0.05 .14 .8 1.1 1.4 2.7 3.3 mA mA mA Logic Inputs VIH Input High Voltage VIL Input Low Voltage 0 0.5 V IIH Input High Current @ VIH = 3.3V −0.5 0.02 +0.5 µA IIL Input Low Current @ VIH = 0V −0.5 0.02 +0.5 µA 2.43 V Charge Pump fCP Charge Pump Frequency Measure at DRIVE at Full Power 2.75 MHz VHIGH Charge Pump High Average Voltage Measure at CstoreH at Full Power +14.6 V VLOW Charge Pump Low Average Voltage Measure at CstoreL at Full Power −2.7V V Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. Note 2: Human body model, 1.5kΩ in series with 100pF. Note 3: Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚ C. Note 4: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC board. Die attach pad is electrically connected to AGND. Note 5: Typical Values represent the most likely parametric norm. Note 6: All limits are guaranteed by testing or statistical analysis. Note 7: Slew rate is the slowest of the rising and falling slew rates. Note 8: Machine Model, 0Ω in series with 200 pF. Note 9: Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Absolute maximum ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Note 10: Quiescent supply current specification apply for the condition of no input signal. See application section for information on power consumption as a function of output power, power control bit settings and external resistor RADJ. Note 11: “L” is VIL and “H” is VIH. 3 www.national.com LMH6678 Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C, AVCC1 = AVCC2 = +12V, DVDD = AVDD = +3.3V. DGND = AGND = 0V, 2/3 Power Mode. See (Note 9). (Continued) LMH6678 Connection Diagram 20084038 Note: Die attach pad is electrically connected to AGND Ordering Information Package LLP www.national.com Part Number LMH6678LQ LMH6678LQX Package Marking L6678LQ 4 Transport Media 1k Units Tape and Reel 4.5k Units Tape and Reel NSC Drawing LQA24A Single-Ended Small Signal Frequency Response @ RL = 36Ω Single-Ended Small Signal Frequency Response @ RL = 100Ω 20084010 20084011 Medium Signal Pulse Response @ RL = 36Ω, 1 MHz Medium Signal Pulse Response @ RL = 100Ω, 1 MHz 20084005 20084006 Large Signal Pulse Response @ RL = 36Ω, 1 MHz Large Signal Pulse Response @ RL = 100Ω, 1 MHz 20084008 20084007 5 www.national.com LMH6678 Typical Performance Characteristics LMH6678 Typical Performance Characteristics (Continued) Single-Ended Small Signal Frequency Response @ ZL = 100Ω||100 pF Single-Ended Small Signal Frequency Response @ ZL = 36Ω||100 pF 20084014 20084013 Output Swing @ ZL = 100Ω||100 pF, 1 MHz Output Swing @ ZL = 36Ω||100 pF, 1 MHz 20084003 20084001 Output Swing @ ZL = 100Ω||100 pF, 5 MHz Output Swing @ ZL = 36Ω||100 pF, 5 MHz 20084002 20084004 www.national.com 6 (Continued) Differential PSRR @ Analog VCC Differential Output Referred Cross Talk 20084015 20084012 Charge Pump @ Drive Pin Charge Pump Leakage (Differential) 20084009 20084016 Output Voltage Noise @ RS = 50Ω Output Voltage Swing 20084039 20084026 7 www.national.com LMH6678 Typical Performance Characteristics LMH6678 Typical Performance Characteristics (Continued) MTPR @ Full Power, 500 kHz MTPR @ Full Power, 1 MHz 20084030 20084027 MTPR @ 2/3 Power, 500 kHz MTPR @ 2/3 Power, 1 MHz 20084032 20084029 MTPR @ 1/3 Power, 500 kHz MTPR @ 1/3 Power, 1 MHz 20084031 www.national.com 20084028 8 (Continued) Detail View of Total ICC vs. RADJ @ VADJ = +12V Detail View of Total ICC vs. RADJ @ VADJ = +3.3V 20084033 20084035 Harmonic Distortion vs. Frequency Harmonic Distortion vs. Load 20084017 20084040 Harmonic Distortion @ ICC = 33mA, 200 kHz Harmonic Distortion @ ICC = 33 mA, 1 MHz 20084019 20084018 9 www.national.com LMH6678 Typical Performance Characteristics LMH6678 Typical Performance Characteristics (Continued) Harmonic Distortion @ ICC = 21 mA, 200 kHz Harmonic Distortion @ ICC = 21 mA, 1 MHz 20084020 20084021 Harmonic Distortion @ ICC = 16 mA, 200 kHz Harmonic Distortion @ ICC = 16 mA, 1 MHz 20084023 20084022 Harmonic Distortion @ ICC = 11.4 mA, 200 kHz Harmonic Distortion @ ICC = 11.4 mA, 1 MHz 20084024 www.national.com 20084025 10 FUNCTIONAL DESCRIPTION The LMH6678 contains two pairs of high speed/high output current operational amplifiers configured as two amplifiers differential inputs and outputs, as shown in Figure 1. Quies- 20084041 FIGURE 1. Functional Block Diagram All supply voltage pins need a 0.1 µF ceramic capacitor in parallel with a 4.7 µF capacitor as bypass capacitors. The 0.1 µF capacitor should be as close as possible to the supply voltage pin and the larger capacitor placed next to it. The LMH6678 delivers very low power consumption at a single +12V analog supply voltage by a combination of its circuit architecture and the on-chip dual charge pump. The output stage is an emitter-follower type, which can provide low distortion, low quiescent current and high peak output currents. The charge pumps generate two internal dc voltages, VHIGH = +15V and VLOW = −3V. As shown in Figure 2, VHIGH and VLOW supply base currents for the output stages. This enables the drivers to swing within a VCE(sat) of VCC and ground, giving the LMH6678 its high swing of +11.5 VPP into a 31Ω load. TABLE 1. Power Mode Logic Control Channel A (B) Power Mode B01 (B02) B11 (B12) Full Power L L 2/3 Power H L 1/3 Power L H Shutdown H H Channel A and B are set independently. Two supply voltages are required, +12V ± 10% and +3.3V ± 10%. Current for the driver amplifiers, including their output current, flows from the 12V analog VCC (AVCC) supply and Analog Ground (AGND.) For proper output swing and distortion performance, both AVCC pins must be connected to +12V and the exposed metal pad must be soldered to ground potential as described in the layout section. Both AVDD and DVDD pins must be connected to +3.3V. The internal bias circuitry is powered from AVDD and AGND while the digital circuitry and charge pump are powered from DVDD and DGND. This allows separate bypassing and decoupling for AVDD and DVDD. 11 www.national.com LMH6678 cent current can be set independently for each channel via two control bits as depicted in table 1. Also, quiescent current can be continuously varied by selection of an external resistor between the ADJ pin and a supply voltage of either +12V or +3.3V. Application Notes LMH6678 Application Notes rents are small compared to the dc bias currents. Typical and maximum quiescent VDD supply currents are given in the electrical characteristics. Thus, for the charge pump capacitors C1-C4, the suggested values are 0.022 µF 20% X7R type. With theses values, the ripple on VHIGH and VLOW will be approximately 40 mVPP. This results in a small spurious output on the line of typically −120 dBm/Hz at 2.75 MHz. Spurs produced at harmonics of the clock frequency are at least 20 dB lower and further attenuated by the transformer. This is shown in the typical performance characteristics section. Ripple and spurious outputs can be further attenuated by increasing the size of the reservoir capacitors C2 and C4. (Continued) 20084042 FIGURE 2. Internal Connections of Integrated Charge Pumps CHARGE PUMPS Figure 3 is a simplified schematic of the internal charge pumps. Each pump consists of a transfer capacitor and a reservoir capacitor and switches. The states of switches are driven by an internal 2.75 MHz clock oscillator. The transfer capacitor of the high charge pump, C1, is connected across DVDD and DGND during one phase of the clock and between VHIGH and AVCC during the opposite phase. This causes its reservoir capacitor, C2, to charge up to DVDD (3.3Volts) potential less a small drop due to finite switch resistance. VHIGH therefore is pumped to nearly VCC + VDD potential or approximately +15V. Similarly, the transfer capacitor of the low charge pump, C3, is connected across DVDD and DGND during one phase of the clock and between AGND and VLOW during the opposite phase. This causes its reservoir capacitor, C4, to charge up to VDD potential less a small drop due to finite switch resistance. VLOW therefore is pumped to nearly −VDD potential or approximately −3V. The charge pumps outputs provide both dc bias currents and the base current of the output transistors. These base cur- www.national.com 20084043 FIGURE 3. Charge Pump Functional Schematic MULTI-TONE POWER RATIO AND NOISE The Multi-Tone Power Ratio of the LMH6678 is shown in the typical performance characteristics section. MTPR is the best representation of non-linearity for ADSL modems. The measurement is accomplished with all ADSL bins transmitting full power except one. The delta between the peak amplitude of the transmitting carriers and energy left in the single bin defines the maximum available SNR for that bin. The test circuit is described in Figure 4. Here R2, C3, R4 and C4 were added for increase gain. 12 LMH6678 Application Notes (Continued) 20084044 FIGURE 4. MTPR Measurement Test Circuit R-C TERMINATION CIRCUIT AND TRANSFORMER TURNS RATIO The LMH6678 was designed to operate in the circuit of Figure 5. In this circuit, resistor R1 and R2 provide a line termination in the upstream band. At higher frequencies in the downstream band, capacitors C1 and C2 bypass R1 and R2 for higher efficiency. To calculate the transformer turns ratio required, we assume a peak-to-rms ratio of 5.8 must be supported and the VCC supply tolerance is 5%. At a 30Ω load, the driver outputs can swing to 350 mV of each rail with low distortion. This gives a peak swing of 12(.95) −0.7 = 10.7V. A typical selection for C1, C2, R1 and R2 results in approximately 0.1 dB loss and the transformer loss is typically 0.25 dB, so total voltage loss is about 0.35 dB. For 19.8 dBm output, line rms voltage is 3.09 and peak voltage is 17.9. The optimum turns ratio is calculated at 1.035 x 17.9/10.7 = 1.73. This gives a reflected line impedance of 100Ω/(1.73)2 = 33.4 at the primary side. R1 and R2 are usually chosen to be 33.4/2 = 16.7 to terminate the line at lower frequencies. 20084045 FIGURE 5. Typical R-C Termination INPUT POWER LEVEL AND GAIN With losses included, output power from the LMH6678 should be 19.8 dBm + 0.35 dB = 20.15 dBm or 103.5 mW. At 33.4Ω, the rms differential output voltage is √(PxR) = 1.86 Vrms. The driver amplifiers have a voltage gain of 5.4V/V, so the input level should be 1.86/5.4 = 344 mVRMS to deliver 19.8 dBm to the line. The driver input equivalent circuit is shown in Figure 1. The inputs should be capacitively coupled to maintain the input and output common-mode voltage at VCC/2. 13 www.national.com LMH6678 Application Notes 3. Calculate transformer turns ratio based on AZ, line driver voltage swing, and transformer insertion loss (TIL). RL is the line impedance, 100Ω for ADSL. N = [(VLINEPP /(2 * 11.2)]* [(1 + ROUT/( RL * AZ)] * 10(TIL/20) 4. Calculate R4 from ROUT, AZ, and N (Continued) If additional gain is required, the gain can be increased with positive feedback using the circuit of Figure 6. In this case the voltage gain AV will be AV =5.4*(1-K)/(1-5.4*K) R4 = ROUT / (2 * AZ * N2) Where K = (R1||10K)/(R1||10K + R2) = 10K*R1(10K*R1 + R1R2 + 10K*R2) and R1 = R3, R2 = R4 5. Calculate the resistance looking into the transformer secondary (chip side). RSEC = RL / N2 6. Calculate K1. K1 = (AZ - 1)/(5.4 * AZ) 7. Calculate K2. K2 = RSEC/( RSEC + 2 * R4) 8. Pick a value for R2. Typically 3kΩ is a good value. 9. Calculate REQ. It is suggested to choose R1 < 3K so that the 15% tolerance of the input resistance will not greatly affect the gain. Furthermore, this circuit will have a differential input resistance of RIN_DIFF = 2*R1 −2 *R2/(4.4) which may be negative in band. Usually no stability problems are seen if this |RIN| is chosen larger than 500Ω. To minimize distortion caused by loading on the Codec outputs, |RIN| is usually chosen to be 1kΩ or more. Additional blocking capacitors C3 and C4 must be inserted in series with R2 and R4 to prevent the circuit from latching. C3 and C4 should be chosen to be less than 1/5 of C1 to avoid large signal oscillation. REQ = R2/(1-5.4* K2) (Note REQ is usually negative.) 10. Calculate RIN RIN = [(K1*R2)/(1-K1)*10k]/[10k-(K1*R2)/(1-K1)] 11. Calculate the gain without the input voltage divider. AV1 = N*5.4*K2 * [(REQ//10k)/(RIN + REQ//10k)] /(10TIL/20) 12. . Calculate AVTOTAL the final required gain from input to the line. AVTOTAL = VLINERMS/VINRMS 13. . Calculate the voltage divider network of R1 and R3 using AV1, transformer insertion loss (TIL), R1 = RIN * [AV1/(AVTOTAL*10TIL/20)] R3 = (2 * RIN)/[1 - (AVTOTAL*10TIL/20)/ AV1] The example shown in Figure 7 is designed to the following parameters: (19.8 dBm output power) VLINERMS = 3.13V AZ = 4.5 ROUT = 65Ω (13.5dB return loss) Crest Factor = 5.8 @ nominal 12V supply Transformer Insertion Loss = 0.4dB (AFE output level) VINRMS = 350mV 20084046 FIGURE 6. Increasing Gain ACTIVE TERMINATION CIRCUIT The LMH6678 can be used to synthesize the output impedance by using positive feedback to increase the output resistance. In ADSL this technique is often used to lower the total power consumption of the line driver by reducing the voltage across the series termination resistors. This approach gives slightly higher power consumption but better return loss in the downstream band compared to the R-C termination of Figure 5. The equations that follow and Figure 7 describe how to implement this technique with the LMH6678. 1. Pick positive feedback factor (also called the resistance gain), AZ. 2. Pick desired output resistance, ROUT, seen by the line. www.national.com 20084047 FIGURE 7. Active Termination Application 14 the PCB, using the PCB as a heatsink. In addition, platedthrough holes (vias) on the PCB provide a low thermal resistance heat flow path to the backside of the circuit board. (Continued) POWER CONSUMPTION Power consumption is a function of line power and dynamic bias current of the line driver. After the transformer turns ratio has been selected as described above, power consumption per channel for the typical R-C termination application can be estimated as follows: ICC = IdB + ILOAD LAND PATTERN AND ASSEMBLY GUIDELINE FOR LMH6678 1. The thermal pad must be connected to analog ground AGND in LMH6678. 2. Prepare the PCB with a top-side land pattern, as shown in figure 8. 3. Place the recommended number of plated-through holes in the area of the thermal pad. These holes should be 8 mils max. in diameter. They are kept small so that solder wicking through the holes is not a problem during reflow. The minimum recommended number of holes for the 24-pin LLP is six, as shown in Figure 8. IdB = 0.25 * Iq This is because 25% of the total dc current flows in the output transistors. This term effectively vanishes when the class AB stage is drives a heavy load. Where ILOAD = average load current driven by output transistors IdB = dynamic VCC bias current while driving full load power ICC = average VCC current 4. Connect all holes to the internal and bottom analog ground plane. 5. When laying out these holes to the ground plane, do not use the typical web or spoke via connection methodology, as shown in Figure 9. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes soldering the vias that have ground plane connections easier. However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the thermal pad should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. Use plated via with solid connection to plane as shown in Figure 10. 6. The top-side solder mask should leave the terminals of the pad connections and the thermal pad area exposed. The thermal pad area should leave the 8 mils holes exposed. When losses included, 103.5 mW is delivered by the driver, therefore IRMS = TR* √(.1035/100) = 32.2 mA Since the ADSL signal is DMT and is effectively guassian, the average value of the supply current due to driving the load is given by ILOAD = average|IRMS| = √(2/π)*IRMS = 0.8 * IRMS = 44.6 mA for TR = 1.73 Assuming 2/3 power mode, Ifixed = 0.25 * 11 mA = 2.75 mA ICC = 2.75 mA + 44.6 mA = 47.4 mA PCC = ICC x VCC = 569 mW To get the IDD full current, simply add 0.75 mA to the quiescent current per channel: IDD = 0.75 + 5.5 + 0.6 = 6.8 mA PDD = VDD * IDD = 23 mW For the total power consumption per channel, PCON = PDD + PCC = 592 mW 7. Apply solder paste to the exposed thermal pad area and all of the package terminals. 8. With these preparatory steps in place, the LLP is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For power dissipation of the LMH6678, subtract the power into the load plus external losses: PDISS = 592-103 = 489 mW per channel PDISS total = 2 x 489 = 978 mW for both channels Proper selection of the external resistor between the ADJ pin can optimize the trade-off between power consumption and distortion. This external resistor will reduce the supply current for the 1/3, 2/3 and full bias settings for both channels. The approximately equation is IS = IS * (1- (VCC-0.8)/(30µA*RADJ)) Curves of VCC and VDD supply currents per channel vs. RADJ for the various power settings are shown in typical performance characteristics section. PACKAGE AND LAYOUT CONSIDERATION The LMH6678 uses the 24-pin Leadless Leadframe Package, a thermally enhanced, standard size IC package designed to eliminate the use of bulky heatsinks traditionally used in thermal packages. This package can be easily mounted using standard PCB surface mount assembly techniques. The LLP is designed so that the thermal pad is exposed on the bottom of the IC, as shown in the package drawing. This provides an extremely low thermal resistance (θJC) path between the die and the exterior of the package. The thermal pad on the bottom of the IC can then be soldered directly to 20084050 FIGURE 8. Recommended Land Pattern 15 www.national.com LMH6678 Application Notes LMH6678 Application Notes (Continued) HIGH SPEED DRIVER LAYOUT GUIDELINES The LMH6678 is a high performance differential line amplifier that requires proper layout for best performance. • Keep power-supply leads as short as possible. This will keep inductance low and resistive losses at a minimum. • Proper power-supply bypassing with low ESR capacitors is essential to achieve good performance. A parallel combination of small (around 0.1 µF) ceramic and bigger (6.8 µF) tantalum bypass capacitors will provide low and impedance over a wide frequency rage. • Bypass capacitor should be placed as close as possible, limited by pick and place machine requirement, to the power-supply pins of the LMH6678 (ceramic cap first and then tantalum cap). • PCB traces conducting high currents, such as from output to load or from power-supply connector to the powersupply pins of the LMH6678 should be kept as wide and short as possible to minimize inductance and resistive loss. • The six holes in the landing pattern for the LMH6678 are for the thermal vias that connect the thermal pad of LLP package to the internal/external ground plane on the PCB. For detail information on the LLP package including thermal modeling considerations and prepared procedures, please see National Semiconductor. "Applications Note 1187: Leadless Leadframe Package (LLP)" located at www.national.com. 20084048 FIGURE 9. Via Connection Not Recommended Under the Thermal Pad 20084049 FIGURE 10. Via Connection Recommended For Use in Thermal Pad www.national.com 16 LMH6678 Low Power 2-Channel Central-Office xDSL Driver Physical Dimensions inches (millimeters) unless otherwise noted 24-Pin LLP NS Package Number LQA24A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.