LMH6734 Single Supply, Ultra High-Speed, Triple Selectable Gain Buffer General Description Features The LMH6734 is a high speed monolithic selectable gain buffer designed specifically for ultra high resolution video systems as well as wide dynamic range systems requiring exceptional signal fidelity. Benefiting from National's current feedback architecture, the LMH6734 offers gains of −1, +1 and +2. At a gain of +2 the LMH6734 supports ultra high resolution video systems with a 560 MHz 2 VPP 3 dB bandwidth. With this large signal bandwidth and 2.1 nV/ of input referred noise, the LMH6734 is ideal for driving component video over CAT5 cable up to 200 ft without frequency and gain equalization. The LMH6734 is offered in a space saving 16-Pin SSOP package. (Typical values unless otherwise specified.) ■ Supply range 3V to 12V single supply ■ Supply range ±1.5V to ±6V split supply ■ 925 MHz −3 dB small signal bandwidth (AV = +1, VS = ±5V) ■ 650 MHz −3 dB small signal bandwidth (AV = +2, VS = 5V) ■ Low supply current (5.5 mA per op amp, VS = 5V) ■ 2.1 nV/√Hz input noise voltage ■ 3750 V/μs slew rate (VS = ±5V) ■ 70 mA linear output current (AV = +2, VS = ±5V) ■ Input range and output swing to 1V from each supply rail Applications ■ ■ ■ ■ ■ ■ ■ HDTV component video driver CAT5 component video driver High resolution projectors Wide dynamic range IF amp DDS post-amps Wideband inverting summer Line driver Connection Diagram 16-Pin SSOP 30003610 Top View RF = RG = 327Ω VIP10™ is a trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 300036 www.national.com LMH6734 Single Supply, Ultra High Speed, Triple Selectable Gain Buffer September 2007 LMH6734 Soldering Information Infrared or Convection (20 sec.) Wave Soldering (10 sec.) Storage Temperature Range Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 5) Human Body Model Machine Model Supply Voltage (V+ - V–) IOUT Common Mode Input Voltage Maximum Junction Temperature Storage Temperature Range Operating Ratings 2000V 200V 13.2V (Note 4) ±VCC +150°C −65°C to +150°C 5V Electrical Characteristics 235°C 260°C −65°C to +150°C (Note 1) Temperature Range (Note 3) Supply Voltage (V+ - V–) Thermal Resistance Package −40°C to +85°C 3V to 12V (θJC) 36°C/W 16-Pin SSOP (θJA) 120°C/W (Note 2) Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = +5V, AV = +2, RL = 100Ω. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 8) Typ (Note 7) Max (Note 8) Units Frequency Domain Performance UGBW −3 dB Bandwidth Unity Gain, VOUT = 200 mVPP 870 SSBW −3 dB Bandwidth VOUT = 200 mVPP, RL = 100Ω 650 SSBW VOUT = 200 mVPP, RL = 150Ω 685 LSBW VOUT = 2 VPP 480 0.1 dB BW 0.1 dB Gain Flatness VOUT = 200 mVPP 130 MHz MHz MHz Time Domain Response TRS Rise and Fall Time (10% to 90%) 2V Step 0.7 ns SR Slew Rate 2V Step 1900 V/µs ts Settling Time to 0.1% 2V Step 10 ns te Enable Time From Disable = Rising Edge 10 ns td Disable Time From Disable = Falling Edge 15 ns HD2L 2nd Harmonic Distortion 2 VPP, 10 MHz −63 dBc HD3L 3rd Harmonic Distortion 2 VPP, 10 MHz −73 dBc Distortion Equivalent Input Noise VN Non-Inverting Voltage >10 MHz 2.1 nV/ ICN Inverting Current >10 MHz 18.6 pA/ NCN Non-Inverting Current >10 MHz 26.9 pA/ Video Performance DG Differential Gain 4.43 MHz, RL = 150Ω 0.03 % DP Differential Phase 4.43 MHz, RL = 150Ω 0.025 deg Static, DC Performance VIO Input Offset Voltage IBN Input Bias Current Non-Inverting PSRR Power Supply Rejection Ratio CMRR 0.4 2.0 2.5 mV 2 16.7 28 32 µA +PSRR 59 59 61 −PSRR 58 56 61 52 52 54.5 Common Mode Rejection Ratio www.national.com 2 dB dB Parameter Conditions XTLK Crosstalk Input Referred, f = 10 MHz, Drive Channels A, C and Measure Channel B ICC Supply Current All three amps Enabled, No Load Min (Note 8) Typ (Note 7) Max (Note 8) −80 15 15 Units dB 16.7 18 19 mA Supply Current Disabled V+ RL = ∞ 1.54 1.8 mA V− RL = ∞ 0.75 1.8 mA % Supply Current Disabled Gain Error RL = ∞ Gain AV = +2 0.2 1.25 1.975 1.996 2.025 −0.9875 −0.998 AV = +1 0.998 AV = −1 V/V −1.0125 Miscellaneous Performance RIN+ Non-Inverting Input Resistance 200 CIN+ Non-Inverting Input Capacitance kΩ 1 RO Output Impedance DC pF 0.05 VO Output Voltage Range RL = 100Ω 1.25-3.75 1.3-3.7 1.12-3.88 Ω RL = ∞ 1.11-3.89 1.15-3.85 1.03-3.97 V CMIR Input Range Driving input +INA, CMRR > 40 dB 1.1-3.9 1.2-3.8 1.0-4.0 IO Linear Output Current VIN = 0V, VOUT < ±42 mV (Note 4) ±50 ±60 mA ISC Short Circuit Current VIN = 2V Output Shorted to Ground (Note 6) 170 mA IIH Disable Pin Bias Current High Disable Pin = V+ −72 μA IIL Disable Pin Bias Current Low Disable Pin = 0V −360 μA VDMAX Voltage for Disable Disable Pin ≤ VDMAX 3.2 V VDMIM Voltage for Enable Disable Pin ≥ VDMIN 3.6 V ±5V Electrical Characteristics V (Note 2) Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = +5V, V− = −5V, AV = +2, RL = 100Ω. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 8) Typ (Note 7) Max (Note 8) Units Frequency Domain Performance UGBW −3 dB Bandwidth Unity Gain, VOUT = 200 mVPP 925 SSBW −3 dB Bandwidth VOUT = 200 mVPP, RL = 100Ω 730 SSBW VOUT = 200 mVPP, RL = 150Ω 760 LSBW VOUT = 2 VPP 560 0.1 dB BW 0.1 dB Gain Flatness VOUT = 200 mVPP 270 MHz MHz MHz Time Domain Response TRS Rise and Fall Time (10% to 90%) 2V Step 0.7 TRL 5V Step 0.8 SR Slew Rate 2V Step 3750 V/µs ts Settling Time to 0.1% 2V Step 10 ns te Enable Time From Disable = Rising Edge 10 ns td Disable Time From Disable = Falling Edge 15 ns 3 ns www.national.com LMH6734 Symbol LMH6734 Symbol Parameter Conditions Min (Note 8) Typ (Note 7) Max (Note 8) Units Distortion HD2L 2nd Harmonic Distortion 2 VPP, 10 MHz −72 dBc HD3L 3rd Harmonic Distortion 2 VPP, 10 MHz −63 dBc Equivalent Input Noise VN Non-Inverting Voltage >10 MHz 2.1 nV/ ICN Inverting Current >10 MHz 18.6 pA/ NCN Non-Inverting Current >10 MHz 26.9 pA/ Video Performance DG Differential Gain 4.43 MHz, RL = 150Ω 0.03 % DP Differential Phase 4.43 MHz, RL = 150Ω 0.03 deg Static, DC Performance VIO Input Offset Voltage 0.6 2.4 3.4 mV IBN Input Bias Current Non-Inverting −14 −19 3.5 19 24 µA PSRR Power Supply Rejection Ratio +PSRR 59 59 61.5 −PSRR 58 58 61 53 53 55 CMRR Common Mode Rejection Ratio XTLK Crosstalk Input Referred, f = 10 MHz, Drive Channels A, C and Measure Channel B ICC Supply Current All three amps Enabled, No Load Supply Current Disabled V+ dB dB −80 18 18 dB 19.5 20.8 22 mA RL = ∞ 1.54 1.8 mA Supply Current Disabled V− RL = ∞ 0.75 1.8 mA Gain Error RL = ∞ 0.2 1.25 % Gain AV = +2 1.996 2.025 1.975 AV = +1 0.998 AV = −1 −0.9875 −0.998 V/V −1.0125 Miscellaneous Performance RIN+ Non-Inverting Input Resistance CIN+ Non-Inverting Input Capacitance 200 kΩ 1 pF RO Output Impedance DC VO Output Voltage Range RL = 100Ω ±3.55 ±3.5 ±3.7 0.05 Ω ±4.0 V RL = ∞ ±3.85 CMIR Input Range Driving input +INA, CMRR > 40 dB ±3.9 ±3.8 ±4.0 IO Linear Output Current VIN = 0V, VOUT < ±43 mV (Note 4) 70 ±80 mA ISC Short Circuit Current VIN = 2V Output Shorted to Ground (Note 6) 237 mA IIH Disable Pin Bias Current High Disable Pin = V+ −72 μA IIL Disable Pin Bias Current Low Disable Pin = 0V −360 μA VDMAX Voltage for Disable Disable Pin ≤ VDMAX 3.2 V VDMIM Voltage for Enable Disable Pin ≥ VDMIN 3.6 V www.national.com 4 V Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ> TA. See Applications Information for information on temperature de-rating of this device. Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / θJA. All numbers apply for packages soldered directly onto a PC Board. Note 4: The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the Application Information for more details. Note 5: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 6: Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of the Application Information for more details. Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 8: Limits are 100% production tested at 25C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Ordering Information Package 16-Pin SSOP Part Number LMH6734MQ LMH6734MQX Package Marking LH6734MQ 5 Transport Media 95 Units/Rail 2.5k Units Tape and Reel NSC Drawing MQA16 www.national.com LMH6734 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. LMH6734 Typical Performance Characteristics V+ = +5V (TA = 25°C, AV = +2, RL = 100Ω, unless otherwise specified.) Large Signal Frequency Response Small Signal Frequency Response 30003631 30003632 Small Signal Frequency Response Frequency Response vs. VOUT 30003664 30003601 Frequency Response vs. Supply Voltage Gain Flatness 30003662 www.national.com 30003647 6 LMH6734 Gain Flatness, Dual Input Buffer Pulse Response 30003648 30003622 Crosstalk vs. Frequency Distortion vs. Frequency 30003635 30003633 Distortion vs. Output Voltage Small Signal Frequency Response vs. Resistive Load 30003634 30003661 7 www.national.com LMH6734 Frequency Response vs. Capacitive Load Series Output Resistance vs. Capacitive Load 30003614 30003619 PSRR vs. Frequency Open Loop Gain and Phase 30003621 30003626 Closed Loop Output Impedance |Z| Disable Timing 30003624 30003604 www.national.com 8 Channel to Channel Crosstalk vs. Frequency 30003649 30003660 Disabled Channel Isolation vs. Frequency 30003663 Typical Performance Characteristics V+ = +5V, V− = −5V (TA = 25°C, AV = +2, RL = 100Ω, unless otherwise specified.) Large Signal Frequency Response Small Signal Frequency Response 30003651 30003652 9 www.national.com LMH6734 DC Errors vs. Temperature LMH6734 Frequency Response vs. VOUT Frequency Response vs. Supply Voltage 30003653 30003616 Gain Flatness Gain Flatness, Dual Input Buffer 30003655 30003654 Pulse Response Pulse Response 30003657 www.national.com 30003658 10 LMH6734 Distortion vs. Frequency Distortion vs. Output Voltage 30003646 30003645 DC Errors vs. Temperature Crosstalk vs. Frequency 30003656 30003659 11 www.national.com LMH6734 Application Information GENERAL INFORMATION The LMH6734 is a high speed current feedback selectable gain buffer (SGB), optimized for very high speed applications. With its internal feedback and gain-setting resistors, RF = RG = 327Ω, the LMH6734 offers excellent AC performance while simplifying board layout and minimizing the effects of layout related parasitic components. The LMH6734 has no internal ground reference so single or split supply configurations are both equally useful. SETTING THE CLOSED LOOP GAIN The LMH6734 can be configured with gain settings of AV = +2, +1, or −1. Table 1, shows the non-inverting and inverting pin connections to achieve the desired closed loop gain. Table 1. Setting the Closed Loop Gain GAIN AV 30003608 INPUT CONNECTIONS Non-Inverting Inverting −1 V/V Ground Input Signal +1 V/V Input Signal NC (Open) +2 V/V Input Signal Ground FIGURE 2. Recommended Split Supply Non-Inverting Gain Circuit, Gain +1 V/V SPLIT SUPPLY APPLICATION The recommended split supply circuit applications are shown in Figure 1, Figure 2 , and Figure 3. In all three configurations the input signal is DC coupled with a termination resister input RIN = 50Ω. In Figure 1 the inverting input is connected to ground completing the internal feedback loop to set the gain to +2 V/V. In Figure 2 the inverting input is open (no-connect), thus providing a buffer configuration of +1 V/V. Figure 3 shows a buffer configuration with a gain of −1 V/V. In this configuration an input resistor of 59Ω was used to balance the internal RG resistor of 327Ω and to provide a 50Ω termination. 30003603 FIGURE 3. Recommended Split Supply Inverting Gain Circuit, Gain = –1 V/V SINGLE SUPPLY APPLICATION The LMH6734 can also be configured for single supply applications as shown in Figure 4, Figure 5, and Figure 6. In Figure 4, the 220 μF capacitor was chosen to satisfy low frequency input signals and to provide an open for the internal feedback network path, thus setting the gain to +1 V/V. With an AC signal present, this 220 μF capacitor is shunted to ground and completes the feedback resistor network to set the AC coupled gain of +2 V/V. The input is AC coupled with the 22 μF capacitor and the two 4.7 kΩ resistors to set the input DC bias voltage. Figure 5 shows the single supply buffer configuration with the inverting input open (no-connect) creating an open to the internal feedback network giving a gain of +1 V/V. The input voltage is AC coupled with the 22 μF capacitor along with two 4.7 kΩ resistors to set the input DC bias voltage. Figure 6 shows the single supply buffer configuration for a gain of −1 V/V. In this circuit, the input signal is DC coupled into the inverting input closing the internal feedback network and creating a gain of −1 V/V while an AC gain of +2 V/V is present at the non-inverting input. Thus, the 6.8 kΩ and the 30003605 FIGURE 1. Recommended Split Supply Non-Inverting Gain Circuit, Gain = +2 V/V www.national.com 12 UNITY GAIN COMPENSATION With a current feedback Selectable Gain Buffer like the LMH6734, the feedback resistor is a compromise between the value needed for stability at unity gain and the optimized value used at a gain of two. The result of this compromise is substantial peaking at unity gain. If this peaking is undesirable a simple RC filter at the input of the buffer will smooth the frequency response as shown in Figure 7. Figure 8 shows the results of a simple filter placed on the non-inverting input. See Figure 9 and Figure 10 for another method of reducing unity gain peaking. 30003642 30003630 FIGURE 4. Recommended Single Supply Non-Inverting Gain Circuit, Gain = +2 V/V FIGURE 7. Correction for Unity Gain Peaking 30003644 FIGURE 5. Recommended Single Supply Non-Inverting Gain Circuit, Gain = +1 V/V 30003629 FIGURE 8. Frequency Response for Circuit in Figure 7 30003643 FIGURE 6. Recommended Single Supply Inverting Gain Circuit, Gain = −1 V/V 30003607 The gain of the LMH6734 is accurate to ±1% and stable over temperature. The internal gain setting resistors, RF and RG, match very well. However, over process and temperature their absolute value will change. Using external resistors in series with RG to change the gain will result in poor gain accuracy over temperature and from part to part. FIGURE 9. Alternate Unity Gain Compensation 13 www.national.com LMH6734 2.2 kΩ resistors were chosen to set the input DC bias voltage to 1/4 the supply voltage such that at high frequencies the output voltage is gained up by +2 V/V. LMH6734 30003637 FIGURE 10. Frequency Response for Circuit in Figure 9 (Standard Circuit Figure 5) COMPONENT DRIVER The LMH6734 is capable of transmitting and receiving component video over short to moderate unshielded twisted-pair (UTP) CAT5 cables, as shown in Figure 11. The component signals Y, Pb, and Pr are connected to the LMH6734 transmit side inputs with a 75Ω termination. The LMH6734 transmit amplifiers are configured for a gain of +2 V/V before driving the CAT5 cable. Only three out of the four pairs in the standard CAT5 are utilized, the fourth pair is available for audio. The output of the LMH6734 transmit amplifier drives a 50Ω transmission system with one side of the twisted pair terminated 50Ω to ground. Note this system, without signal equalization, will satisfy transmission up to 200 ft. For longer cable lengths, frequency and gain equalization to compensate for signal degradation is recommended. The LMH6734 receive side is configured for a unity gain buffer for the component signals received through the CAT5 cable. The inputs of the receiver channels are 100Ω differentially terminated. The two 327Ω external resisters were chosen to match the internal RF and RG value of 327Ω. Figure 12, shows the LMH6734 transceiver frequency response over various lengths of CAT5 cable with a 1 VPP input signal at ±5 supply voltage. The CMRR of the LMH6734 receive side at low frequencies is 55 dB at best with a split power supply of ±5V. 30003665 FIGURE 11. Component Video Transmission Over UTP (CAT5) www.national.com 14 LMH6734 30003666 FIGURE 12. Frequency Response vs. Normalized Gain and CAT5 Cable Length grade second order harmonic performance, especially if the supply traces are thin and /or long. In Figure 1, Figure 2, and Figure 3 it is recommended an optional capacitor, CSS= 0.01 μF, be connected between the split supplies for best second harmonic distortion. Another option to using CSS is to use pairs of 0.01 μF and 0.1 μF ceramic capacitors for each supply bypass. DRIVING CAPACITIVE LOADS Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Figure 13 shows the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. The charts “Suggested ROUT vs. Cap Load” give a recommended value for selecting a series output resistor for mitigating capacitive loads. The values suggested in the charts are selected for 0.5 dB or less of peaking in the frequency response. This gives a good compromise between settling time and bandwidth. For applications where maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the recommended values. VIDEO PERFORMANCE The LMH6734 has been designed to provide excellent performance with production quality video signals in a wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless. Best performance will be obtained with back terminated loads. The back termination reduces reflections from the transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier output stage. Figure 7 shows a typical configuration for driving a 75Ω cable. The amplifier is configured for a gain of two to make up for the 6 dB of loss in ROUT. POWER DISSIPATION The LMH6734 is optimized for maximum speed and performance in the small form factor of the standard 16-Pin SSOP package. To achieve its high level of performance, the LMH6734 consumes an appreciable amount of quiescent current which cannot be neglected when considering the total package power dissipation limit. The quiescent current contributes to about 40° C rise in junction temperature when no additional heat sink is used (VS = ±5V, all three channels on). Therefore, it is easy to see the need for proper precautions in order to make sure the junction temperature’s absolute maximum rating of 150°C is not violated. To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAX is never exceeded due to the overall power dissipation (all three channels). With the LMH6734 used in a back-terminated 75Ω RGB analog video system (with 2 VPP output voltage), the total power dissipation is around 305 mW of which 220 mW is due to the quiescent device dissipation (output black level at 0V). With no additional heat sink used, the junction temperature rises to about 120°C when operated at 85°C ambient. To reduce the junction temperature many options are available. Forced air cooling is the easiest option. An external add- 30003638 FIGURE 13. Decoupling Capacitive Loads LAYOUT CONSIDERATIONS Whenever questions about layout arise, use the evaluation board as a guide. The LMH730275 is the evaluation board supplied with samples of the LMH6734. To reduce parasitic capacitances, ground and power planes should be removed near the input and output pins. For long signal paths controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the smaller ceramic capacitors should be placed as close to the device as possible. The LMH6734 has multiple power and ground pins for enhanced supply bypassing. Every pin should ideally have a separate bypass capacitor. Sharing bypass capacitors may slightly de15 www.national.com LMH6734 on heat-sink can be added to the 16-Pin SSOP package, or alternatively, additional board metal (copper) area can be utilized as heat-sink. An effective way to reduce the junction temperature for the 16-Pin SSOP package (and other plastic packages) is to use the copper board area to conduct heat. With no enhancement the major heat flow path in this package is from the die through the metal lead frame (inside the package) and onto the surrounding copper through the interconnecting leads. Since high frequency performance requires limited metal near the device pins the best way to use board copper to remove heat is through the bottom of the package. A gap filler with high thermal conductivity can be used to conduct heat from the bottom of the package to copper on the circuit board. Vias to a ground or power plane on the back side of the circuit board will provide additional heat dissipation. A combination of front side copper and vias to the back side can be combined as well. Follow these steps to determine the maximum power dissipation for the LMH6734: 1. Calculate the quiescent (no-load) power: PAMP = ICC X (VS) VS = V+-V− 2. Calculate the RMS power dissipated in the output stage: PD (rms) = rms ((VS - VOUT) X IOUT) where VOUT and IOUT are the voltage and current across the external load and VS is the total supply current 3. Calculate the total RMS power: PT = PAMP+PD The maximum power that the LMH6734 package can dissipate at a given temperature (See Figure 14) can be derived with the following equation: PMAX = (150° C/W – TAMB)/ θJA, where TAMB = Ambient temperature (°C) and θJA = Thermal resistance, from junction to ambient, for a given package (°C/W). For the SSOP package θJA is 120°C/W. ESD PROTECTION The LMH6734 is protected against electrostatic discharge (ESD) on all pins. The LMH6734 will survive 2000V Human Body Model and 200V Machine Model events. Under closed loop operation the ESD diodes have no affect on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6734 is driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is possible to power up a chip with a large signal applied to the input pins. Shorting the power pins to each other will prevent the chip from being powered up through the input. EVALUATION BOARDS National Semiconductor provides the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization. Many of the datasheet plots were measured with these boards. Device Package Evaluation Board Part Number LMH6734MQ SSOP LMH730275 A bare evaluation board can be ordered when a sample request is placed with National Semiconductor. 30003602 FIGURE 14. Maximum Power Dissipation www.national.com 16 LMH6734 Physical Dimensions inches (millimeters) unless otherwise noted 16-Pin SSOP NS Package Number MQA16 17 www.national.com LMH6734 Single Supply, Ultra High Speed, Triple Selectable Gain Buffer Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. 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As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. 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