NSC CLC411AJE

N
CLC411
High-Speed Video Op Amp with Disable
General Description
Features
The CLC411 combines a state-of-the-art complementary bipolar
process with National’s patented current-feedback architecture to
provide a very high-speed op amp operating from ±15V supplies.
Drawing only 11mA quiescent current, the CLC411 provides a
200MHz small signal bandwidth and a 2300V/µs slew rate while
delivering a continuous 70mA current output with ±4.5V output swing.
The CLC411’s high-speed performance includes a 15ns settling time
to 0.1% (2V step) and a 2.3ns rise and fall time (6V step).
■
The CLC411 is designed to meet the requirements of professional
broadcast video systems including composite video and high definition
television. The CLC411 exceeds the HDTV standard for gain flatness
to 30MHz with it's ±0.05dB flat frequency response and exceeds
composite video standards with its very low differential gain and
phase errors of 0.02%, 0.03°. The CLC411 is the op amp of choice
for all video systems requiring upward compatibility from NTSC and
PAL to HDTV.
Applications
■
■
■
■
■
■
■
HDTV amplifier
Video line driver
■ High-speed analog bus driver
■ Video signal multiplexer
■ DAC output buffer
■
■
Gain Flatness (A v=+2)
Magnitude (0.5dB/div)
The CLC411 features a very fast disable/enable (10ns/55ns) allowing
the multiplexing of high-speed signals onto an analog bus through the
common output connections of multiple CLC411’s. Using the same
signal source to drive disable/enable pins is easy since “breakbefore-make” is guaranteed.
The CLC411 is available in several versions:
CLC411AJP
CLC411AJE
CLC411A8B
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
8-pin plastic DIP
8-pin plastic SOIC
8-pin hermetic CERDIP,
MIL-STD-883
dice, MIL-STD-883, Level B
CLC411AMC
-55°C to +125°C
DESC SMD number: 5962-94566
200MHz small signal bandwidth (1Vpp)
±0.05dB gain flatness to 30MHz
0.02%, 0.03° differential gain, phase
2300V/µs slew rate
10ns disable to high-impedance output
70mA continuous output current
±4.5V output swing into 100Ω load
±4.0V input voltage range
CLC411
High-Speed Video Op Amp with Disable
June 1999
0
Frequency (5MHz/div)
50
+Vcc
6.8µF
Recommended
Inverting Gain
Configuration
Pinout
DIS
0.1µF
DIP & SOIC
7
3
25Ω
+
8
+Vr
CLC411
2
0.01µF
1
_
5
4
6
Vout
0.01µF
-Vr
Vin
Rg
RT
Rf
0.1µF
Select RT to yield
Rin = RT||Rg
6.8µF
+Vr
1
Vinv
2
Vnon-inv
3
-Vcc
4
8
DIS
-
7
+Vcc
+
6
Vout
5
-Vr
-Vcc
 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
CLC411 Electrical Characteristics (A
V
PARAMETERS
Ambient Temperature
CONDITIONS
CLC411 AJ
= +2; VCC = ±15V; RL = 100
Ω; Rf = 301
Ω , unless noted)
100Ω
301Ω
TYP
+25°C
MIN/MAX RATINGS
-40°C
+25°C
+85°C
UNITS
SYMBOL
200
75
150
50
150
50
110
40
MHz
MHz
SSBW
LSBW
0.05
0.05
0.1
0.2
0.3
0.02
0.03
0.2
0.2
0.6
0.7
1.0
0.2
0.2
0.5
0.4
1.0
0.3
0.4
0.6
0.7
1.0
dB
dB
dB
dB
°
%
°
GFPL
GFRL
GFPH
GFRH
LPD
DG
DP
2.3
15
5
2300
23
15
18
10
23
15
ns
ns
%
V/µs
TR
TS
OS
SR
-48
-52
-35
-42
-35
-42
-35
-35
dBc
dBc
HD2
HD3
nV/√Hz
pA/√Hz
pA/√Hz
dBm1Hz
µV
VN
ICI
ICN
SNF
INV
50
46
12
3.5
±14
±50
±20
±250
±30
±150
48
44
12
4.5
mV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
mA
mA
VIO
DVIO
IBN
DIBN
IBI
DIBI
PSRR
CMRR
ICC
ICCD
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vout < 1Vpp
Vout < 6Vpp
gain flatness
Vout < 1Vpp
peaking
DC to 30MHz
rolloff
DC to 30MHz
peaking
DC to 200MHz
rolloff
DC to 60MHz
linear phase deviation
DC to 60MHz
differential gain
4.43MHz, RL=150W
differential phase
4.43MHz, RL=150W
TIME DOMAIN RESPONSE
rise and fall time
6V step
settling time to 0.1%
2V step
overshoot
2V step
slew rate
6V step
DISTORTION AND NOISE RESPONSE (note 1)
2Vpp, 20MHz
2ND harmonic distortion
2Vpp, 20MHz
3RD harmonic distortion
equivalent noise input
voltage
>1MHz
inverting current
>1MHz
non-inverting current
>1MHz
noise floor
>1MHz
integrated noise
1MHz to 200MHz
2.5
12.9
6.3
-157
45
STATIC DC PERFORMANCE
*input offset voltage
average temperature coefficient
*input bias current
non-inverting
average temperature coefficient
*input bias current
inverting
average temperature coefficient
power supply rejection ratio
common mode rejection ratio
*supply current
no load
supply current
disabled
±2
+30
12
±200
±12
±50
56
52
11
2.5
±13
±50
65
±400
±40
±200
48
44
14
4.5
10
55
30
30
60
ns
ns
TOFF
TON
4.5
5.5
59
<3.0
>7.0
55
<3.0
>6.5
55
<3.0
>6.5
55
V
V
dB
VDIS
VEN
OSD
1000
2.0
±6.0
±4.5
±4.0
70
250
3.0
750
3.0
±4.5
±4.0
±3.5
50
1000
3.0
kΩ
pF
V
V
V
mA
RIN
CIN
VO
VOL
CMIR
IO
DISABLE/ENABLE PERFORMANCE (note 2)
disable time
to >50dB attenuation @10MHz
enable time
DIS voltage
pin 8
to disable
to enable
off isolation
at 10MHz
MISCELLANEOUS PERFORMANCE
non-inverting input resistance
non-inverting input capacitance
output voltage range
no load
output voltage range
RL=100Ω
common mode input range
output current
30
±9.0
____
30
____
±30
____
40
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels
are determined from tested parameters.
Miscellaneous Ratings
Absolute Maximum Ratings
Vcc
Iout
common-mode input voltage
differential input voltage
maximum junction temperature
operating temperature range: AJ
storage temperature range
lead temperature (soldering 10 sec)
ESD (human body model)
±18V
125mA
±Vcc
±15V
+150°C
-40°C to +85°C
-65°C to +150°C
+300°C
1000V
Recommended gain range
Notes: * AJ : 100% tested at +25°C.
note 1
note 2
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: Specifications guaranteed using 0.01mF bypass capacitors
on pins 1 & 5.
: Break before make is guaranteed.
Package Thermal Resistance
Reliability Information
Transistor count
±1 to ±10V/V
70
2
Package
θ JC
θ JA
AJP
AJE
A8B
65°C/W
55°C/W
25°C/W
120°C/W
135°C/W
115°C/W
o
Non-Inverting Frequency Response
-90
Av = 10
Rf = 200Ω
-180
-270
Av = 5
Rf = 200Ω
Magnitude (1dB/div)
0
Av = -1
Rf = 301Ω
Vout = 1Vpp
Av = -2
Rf = 301Ω
-180
-270
Av = -10
Rf = 200Ω
-360
-360
-450
Av = -5
Rf = 249Ω
-540
-450
1
10
100
Frequency (MHz)
Frequency (MHz)
Phase (deg)
Magnitude (1dB/div)
Inverting Frequency Response
Phase (deg)
Av = 2
Rf = 301Ω
Av = 1
Rf = 402Ω
Vout = 1Vpp
-630
1
10
Frequency (MHz)
Frequency (MHz)
3
100
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+Vcc
+Vcc
6.8µF
DIS
0.1µF
7
Vin
3
+
8
+Vr
2
_
7
0.01µF
6
Vout
8
+
3
25Ω
+Vr
0.01µF
1
6
CLC411
2
0.01µF
5
4
DIS
0.1µF
1
CLC411
Rin
6.8µF
Figure 3: Recommended
Inverting Gain Circuit
_
0.01µF
5
4
-Vr
Vout
-Vr
Vin
Rg
Rf
Rg
0.1µF
6.8µF
-Vcc
RT
Figure 1: Recommended
Non-inverting Gain Circuit
-Vcc
low-inductance ground plane. Bypassing the Vr pins will
reduce high frequency noise (>10MHz) in the amplifier.
If this noise is not a concern these capacitors may be
eliminated.
Differential Gain and Phase
The differential gain and phase errors of the CLC411
driving one doubly-terminated video load (RL=150Ω) are
specified and guaranteed in the “Electrical
Characteristics” table. The “Typical Performance” plot,
“Differential Gain and Phase (4.43MHz)” shows the
differential gain and phase performance of the CLC411
when driving from one to four video loads. Application
note OA-08, “Differential Gain and Phase for Composite
Video Systems,” describes in detail the techniques
used to measure differential gain and phase.
A block diagram of the amplifier and regulator topology
is shown in Figure 2, “CLC411 Equivalent Circuit.” The
regulators derive their reference voltage from an internal
floating zener voltage source. External control of the
zener reference pins can be used to level-shift amplifier
operation which is discussed in detail in the section
entitled “Extending Input/Output Range with Vr.”
+Vcc
1
+Vr
Feedback Resistor
The loop gain and frequency response for a currentfeedback operational amplifier is determined largely by
the feedback resistor, Rf. The electrical characteristics
and typical performance plots contained within the
datasheet, unless otherwise stated, specify an Rf of
301Ω, a gain of +2V/V and operation with ±15V power
supplies. The frequency response at different gain
settings and supply voltages can be optimized by
selecting a different value of Rf. Generally, lowering R f
will peak the frequency response and extend the
bandwidth while increasing its value will roll off the
response. For unity-gain voltage follower circuits, a
17kΩ
+
reg
3
+
2
-
+
-
6
_
reg
Vz
5
-Vr
4
-Vcc
Select RT to yield
Rin = RT||Rg
6.8µF
Description
The CLC411 is a high-speed current-feedback operational
amplifier which operates from ±15V power supplies.
The external supplies (±VCC) are regulated to lower
voltages internally. The amplifier itself sees
approximately ±6.5V rails. Thus the device yields
performance comparable to Comlinear’s ±5V devices,
but with higher supply voltages. There is no degradation
in rated specifications when the CLC411 is operated
from ±12V. A slight reduction in bandwidth will be
observed with ±10V supplies. Operation at less than
±10V is not recommended.
7
Rf
0.1µF
17kΩ
500
Figure 2: CLC411 Equivalent Circuit
400
Inverting
http://www.national.com
Rf (Ω)
Power Supply Decoupling
There are four pins associated with the power supplies.
The VCC pins (4,7) are the external supply voltages. The
Vr pins (5,1) are connected to internal reference nodes.
Figures 1 and 3 , “Recommended Non-inverting Gain
Circuit” and "Recommended Inverting Gain Circuit"
show the recommended supply decoupling scheme
with four ceramic and two electrolytic capacitors. The
ceramic capacitors must be placed immediately adjacent
to the device pins and connected directly to a good
300
Non-Inverting
200
100
0
0
1
2
3
4
5
6
7
8
9
Gain (V/V)
Figure 4: Recommended Rf vs. Gain
4
10
non-zero Rf must be used with current-feedback
operational amplifiers such as the CLC411. Application
note OA-13, “Current-Feedback Loop-Gain Analysis
and Performance Enhancements,” explains the
ramifications of Rf and how to use it to tailor the desired
frequency response with respect to gain. The equations
found in the application note should be considered as a
starting point for the selection of Rf. The equations do
not factor in the effects of parasitic capacitance found
on the inverting input, the output nor across the feedback
resistor. Equations in OA-13 require values for Rf
(301Ω), Av (+2) and Ri (inverting input resistance, 50Ω).
Combining these values yields a Zt* (optimum feedback
transimpedance) of 400Ω. Figure 4 entitled
"Recommended Rf vs. Gain" will enable the selection of
the feedback resistor that provides a maximally flat
frequency response for the CLC411 over its gain range.
+15V
The linear portion of the two curves (i.e. AV>4) results
from the limitation on Rg (i.e. Rg ≥50Ω).
Enable/Disable Operation
The disable feature allows the outputs of several CLC411
devices to be connected onto a common analog bus
forming a high-speed analog multiplexer. When disabled,
the output and inverting inputs of the CLC411 become
high impedances. The disable pin has an internal pullup resistor which is pulled-up to an internal voltage, not
to the external supply. The CLC411 is enabled when pin
8 is left open or pulled-up to ≥+7V and disabled when
grounded or pulled below +3V. CMOS logic devices are
necessary to drive the disable pin. For example, CMOS
logic with VDD ≥ +7V will guarantee proper operation over
temperature. TTL voltage levels are inadequate for
controlling the disable feature.
For faster enable/disable operation than 15V CMOS
logic devices will allow, the circuit of Figure 5 is
recommended. A fast four-transistor comparator, Figure
5A, interfaces between the CLC411 DISABLE pin and
several standard logic families. This circuit has a
differential input between the bases of Q1 and Q2. As
such it may be driven directly from differential ECL
logic, as in shown in Figure 5B. Single-ended logic
families may also be used by establishing an appropriate
threshold voltage on the Vth input, the base of Q2.
0.1µF
Q3
Q4
CLC411 pin 8, DISABLE
Disable
Q1
Q2
Vth
3.57kΩ
0.1µF
Q1,Q2 MPSH10
Q3,Q4 MPSH81
-15V
Buffers
Q1
A
B
C
Q2
330Ω
330Ω
-5.2V
ECL
Gate
-5.2V
0
1
2
3
4
5
6
7
DIS (pin 8)
+
A
-
CLC411
Figure 5B: Differential ECL Interface
DIS (pin 8)
931Ω
Q1
Q2
+
50Ω
B
0.1µF
ECL
Gate
10kΩ
330Ω
Analog Bus
Figure 5A: Disable Interface
-
CLC411
-15V
-5.2V
Figure 5C: ECL Interface
Figure 6: General Multiplexing Circuit
50Ω
Q2
Q1
50Ω
Figures 5C and 5D illustrate a single-ended ECL and
TTL interface respectively. The Disable input, the base
of Q1, is driven above and below the threshold, Vth.
0.1µF
332Ω
TTL
Gate
1N914
Fastest switching speeds result when the differential
voltage between the bases of Q1 and Q2 is kept to less
Figure 5D: TTL Interface
5
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than one volt. Single-ended ECL, Figure 5C, maintains
this desired maximum differential input voltage. TTL
and CMOS have higher Vhigh to Vlow excursions. The
circuit of figure 5D will ensure the voltage applied
between the bases of Q1 and Q2 does not cause
excessive switching delays in the CLC411. Under the
above proscribed four-transistor interface, all variations
were evaluated with approximately 1ns rise and fall
times which produced switching speeds equivalent to
the rated disable/enable switching times found in the
"CLC411 Electrical Characteristics" table.
implicitly have 0V as their midpoint, i.e. the VO range
is ±6V, centered at 0V.
An external voltage source can be applied to +Vr to shift
the range of the input/output voltages. For example, if
it were desired to move the positive VO range from +6V
to a +9V maximum in unipolar operation, Figure 7, “DC
Parameters as a Function of +Vr”, is used to determine
the required supply and +Vr voltages. Referring to
Figure 7, locate the point on the +VOMAX line where the
ordinate is +9V. Draw a vertical line from this point
intersecting the other lines in the graph. The circuit
voltages are the ordinates of these intersections. For
this example these points are shown in the graph as
solid dots. The required voltage sources are +Vr=+12V,
+ V CC = + 12V, -V CC=-12V. When these supply and
reference voltages are applied, the range for VO is -3V
to +9V, and CMIR ranges from -1V to +7V. The difference
between the minimum and maximum voltages is
constant, i.e. 12V for VO, only the midpoint has been
shifted, i.e. from 0V to +3V for VO.
A general multiplexer configuration using several
CLC411s is illustrated in figure 6, where a typical 8-to1 digital mux is used to control the switching operation
of the paralleled CLC411s. Since "break-before-make"
is a guaranteed specification of the CLC411 this
configuration works nicely. Notice the buffers used in
driving the disable pins of the CLC411s. These buffers
may be 15V CMOS logic devices mentioned previously
or any variation of the four-transistor comparator
illustrated above.
Note that in this example the -Vr pin has been left open
(or bypassed to reduce high-frequency noise). The
difference between +Vr and -Vr is fixed by V z. A levelshifting voltage can be applied to only one of the
reference pins, not both. If extended operation were
needed in the negative direction, Figure 4 may be used
by changing the signs, and applying the resultant
negative voltage to the -Vr pin. It is recommended that
+Vr be used for positive shifts, and -Vr for negative
shifts of input/output voltage range.
Extending Input/Output Range with Vr
As can be seen in Figure 3, the magnitude of the internal
regulated supply voltages is fixed by V z. In normal
operation, with ±15V external supplies, +Vr is nominally
+9V when left floating. CMIR (common mode input
range) and VO (output voltage range, no load) are
specified under these conditions. These parameters
20
Printed Circuit Layout & Evaluation Board
Refer to application note OA-15, “Frequent Faux Pas in
Applying Wideband Current Feedback Amplifiers,” for
board layout guidelines and construction techniques. Two
very important points to consider before creating a layout
which are found in the above application note are worth
reiteration. First the input and output pins are sensitive to
parasitic capacitances. These parasitic capacitances
can cause frequency-response peaking or sustained
oscillation. To minimize the adverse effect of parasitic
capacitances, the ground plane should be removed from
those pins to a distance of at least 0.25" Second, leads
should be kept as short as possible in the finished layout.
In particular, the feedback resistor should have its shortest
lead on the inverting input side of the CLC411. The output
is less sensitive to parasitic capacitance and therefore
can drive the longer of the two feedback resistor
connections. The evaluation board available for the CLC411
(part #730013 for through-hole packages, 730027 for SO8) may be used as a reference for proper board layout.
Application schematics for this evaluation board are in the
product accessories section of the Comlinear databook.
+VCCmax
+Vr
15
10
+VOmax
5
-5
5
-5
10
15
Vcm+
Vcm_
-10
-15
R
e
-V com
cc m
ra en
n g de
e d
R
e
+V com
cc m
ra end
ng e
e d
-10
-VOmin
-VCCmax
Figure 7: DC Parameters as a Function of +Vr
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CLC411
High-Speed Video Op Amp with Disable
Customer Design Applications Support
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National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
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of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
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National Semiconductor
Japan Ltd.
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circuitry and specifications.
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8