LP3950 Color LED Driver with Audio Synchronizer General Description Features The LP3950 is a color LED driver with a built-in audio synchronization feature for any analog audio input such as polyphonic ring tones and MP3 music. LEDs can be synchronized to an audio signal with two methods - amplitude and frequency. Also several fine tuning options are available for differentiation purposes. The chip also has an unique AGC (Automatic Gain Control) feature which tracks the input signal level and automatically adjusts the gain to an optimal value. The LP3950 has a high efficiency magnetic DC/DC converter with programmable output voltage and switching frequency. The converter has high output current capability so it is also able to drive flash LEDs in camera phone applications. n Audio synchronization for color LEDs with two modes: Amplitude and Frequency n Programmable frequency and amplitude response with tracking speed control n Automatic gain control or selectable gain for input signal optimization n RGB pattern generator similar to LP3933/LP3936 n Magnetic DC-DC boost converter with programmable boost output voltage n Selectable SPI or I2C compatible interface n One pin default enable for non-serial interface users. One pin selector for synchronization mode n Space efficient 32-pin thin CSP laminate package The LP3950 is similar to LP3933 and LP3936 in that the color LEDs (or RGB LEDs) can also be programmed to generate light patterns (programmable color, intensity, on/off timing, slope and blinking cycle). All functions are software controllable through a SPI or I2C compatible interface but the device also supports one pin control for enabling predefined (default) audio synchronization mode. Applications n Cellular phones n MP3/CD/minidisc players n Toys Typical Application 20129301 © 2005 National Semiconductor Corporation DS201293 www.national.com LP3950 Color LED Driver with Audio Synchronizer February 2005 LP3950 Connection Diagrams and Package Mark Information 32-Lead Thin CSP Package, 4.5 x 5.5 x 0.8 mm, 0.5 mm Pitch See NS Package Number SLD32A 20129303 20129302 Bottom View Top View 20129304 Note: The actual physical placement of the package marking will vary from part to part. The package marking “XY” designates the date code. “UZ” and “TT” are NSC internal codes for die manufacturing and assembly traceability. Both will vary considerably. Package Mark — Top View Ordering Information Order Number www.national.com Package Marking Supplied As LP3950SL LP3950SL 1000 units, Tape-and-Reel LP3950SLX LP3950SL 2500 units, Tape-and-Reel 2 LP3950 Pin Description Pin # Name Type 1 FB Input Description 2 GND_BOOST Ground Power switch ground. 3 SW Output Open drain, boost converter power switch. Boost converter feedback. 4 VDD2 Power Supply voltage for internal digital circuits. 5 GND2 Ground Ground return for VDD2 (internal digital). 6 DME Logic Input Default mode enable (internal pull down 1 MΩ). Audio mode selection (internal pull down 1 MΩ). 7 AMODE Logic Input 8 VDDA Power 9 ASE Input Analog audio input, single-ended. 10 AD1 Input Analog audio input, differential. Supply voltage for audio circuits. 11 AD2 Input Analog audio input, differential. 12 GNDA Ground Ground for analog audio inputs. 13 RT Input Oscillator resistor. 14 VDD1 Power Supply voltage for internal analog circuits. 15 GND1 Ground Ground. 16 VREF Output Internal reference bypass capacitor. 17 GND3 Ground Ground. 18 NRST Logic Input 19 SS/SDA Logic I/O 20 SO Logic Output Low active reset input. SPI slave select/ I2C data line. SPI serial data output. 21 SI Logic Input SPI serial data input. 22 SCK/SCL Logic Input SPI/ I2C clock. 23 PWM_LED Logic Input Direct PWM control for LEDs. 24 VDDIO Power 25 IF_SEL Logic Input 26 B2 Output Open drain output, blue LED2. 27 G2 Output Open drain output, green LED2. Supply voltage for logic IO signals. SPI/I2C select (IF_SEL = 1 in SPI mode). 28 R2 Output Open drain output, red LED2. 29 GND_RGB Ground RGB driver ground. 30 R1 Output Open drain output, red LED1. 31 G1 Output Open drain output, green LED1. 32 B1 Output Open drain output, blue LED1. 3 www.national.com LP3950 Absolute Maximum Ratings Maximum Lead Temperature (Notes 1, 260˚C 2) (Reflow soldering, 3 times) (Note 7) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Rating (Note 8) V (SW, FB, R1–2, G1–2, B1–2) (Notes 3, 4) −0.3V to +7.2V VDD1, VDD2, VDDIO, VDDA −0.3V to +6.0V Voltage on ASE, AD1, AD2 VDD1 Voltage on Logic Pins 2.7V to 2.9V VDDIO 1.65V to VDD1,2 V Voltage on ASE, AD1, AD2 150 mA Internally Limited Junction Temperature (TJ-MAX) Storage Temperature Range 0V to 6.0V VDD1, VDD2, VDDA (Note 4) 10 µA Continuous Power Dissipation (Note 6) 200V V (SW, FB, R1–2, G1–2, B1–2) −0.3V to VDD_IO +0.3V with 6.0V max I (VREF) 2 kV Machine Model: Operating Ratings (Notes 1, 2) −0.3V to +0.3V with 6.0V max I (R1, G1, B1, R2, G2, B2) (Note 5) Human Body Model: 0.1V to VDD1 - 0.1V Recommended Load Current 0 mA to 300 mA Junction Temperature (TJ) Range −40˚C to +125˚C Ambient Temperature (TA) Range (Note 9) −40˚C to +85˚C Thermal Properties 125˚C −65˚C to +150˚C Junction-to-Ambient Thermal Resistance 72˚C/W (θJA), SLD32A Package (Note 10) Electrical Characteristics (Notes 2, 11) Limits in standard typeface are for TJ = +25˚C. Limits in boldface type apply over the operating ambient temperature range (−40˚C ≤ TA ≤ +85˚C). Unless otherwise noted, specifications apply to Figure 1 with: VDD1 = VDD2 = VDDA = 2.8V, CVDD1 = CVDD2 = CVDDA = CVDDIO = 100 nF, COUT = CIN = 10 µF, CVREF = 100 nF, L1 = 4.7 µH and fBOOST = 2.0 MHz (Note 12). Symbol Typ Max Units Standby Supply Current (VDD1 + VDD2 + VDDA current) NSTBY = L (register) SCK, SS, SI, NRST = H 1 5 µA No-Load Supply Current (VDD1 + VDD2 + VDDA current, boost off) NSTBY = H (reg.) EN_BOOST = L (reg.) SCK, SS, SI, NRST = H 300 400 µA Full Load Supply Current (VDD1 + VDD2 + VDDA current, boost on) (Note 13) NSTBY = H (reg.) EN_BOOST = H (reg.) SCK, SS, SI, NRST = H All Outputs Active 850 µA IVDDIO VDDIO Supply Current 1.0 MHz SCK Frequency CL = 50 pF at SO Pin 20 µA IVDDA Audio Circuitry Supply Current (Note 14) INPUT_SEL = [10] (register) 550 µA VREF Reference Voltage(Note 15) IREF ≤ 1.0 nA Only for Test Purpose 1.230 V IVDD Parameter Condition Min Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins (GND1–3, GND_BOOST, GND_RGB, GNDA). Note 3: Battery/Charger voltage should be above 6.0V no more than 10% of the operational lifetime. Note 4: Voltage tolerance of LP3950 above 6.0V relies on fact that VDD1, VDD2 and VDDA (2.8V) are available (ON) at all conditions. If VDD1, VDD2 and VDDA are not available (ON) at all conditions, National Semiconductor does not guarantee any parameters or reliability for this device. Also, VDD1, VDD2 and VDDA must be at the same electric potential. Note 5: The total load current of the boost converter should be limited to 300 mA. Note 6: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160˚C (typ.) and disengages at TJ = 140˚C (typ.). Note 7: For detailed package and soldering specifications and information, please refer to National Semiconductor Application Note 1125: Laminate CSP/FBGA. Note 8: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 www.national.com 4 (Continued) Note 9: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (θJA x PD-MAX). Note 10: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 11: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 12: Low-ESR Surface-Mount Ceramic Capacitors are used in setting electrical characteristics. Note 13: Audio block inactive. Note 14: In single-ended and in differential mode one audio buffer only is active and IVDDA will be reduced by 90 µA (typ). Note 15: VREF pin (Bandgap reference output) is for internal use only. A capacitor should always be placed between VREF and GND1. 5 www.national.com LP3950 Electrical Characteristics (Notes 2, 11) LP3950 Block Diagram 20129305 FIGURE 1. LP3950 Block Diagram Modes of Operation RESET: In the RESET mode all the internal registers are reset to the default values. RESET is entered always if input NRST is LOW or internal Power On Reset is active. STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW and RESET is not active. This is the low power consumption mode, when all the circuit functions are disabled. Registers can be written in this mode and the control bits are effective immediately after start up. STARTUP: INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (VREF, oscillator, etc.). To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine. Thermal shutdown (THSD) disables the chip operation and Startup mode is entered until no thermal shutdown event is present. BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. In this mode the boost output is raised in PFM mode during the 10 ms delay generated by the state-machine. All RGB outputs are off during the 10 ms delay to ensure smooth startup. The Boost startup is entered from Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH. NORMAL: During the NORMAL mode the user controls the chip using the control registers. Registers can be written in any sequence and any number of bits can be altered in a register within one write cycle . If the default mode is selected, default control register values are used. www.national.com 6 LP3950 Modes of Operation (Continued) 20129306 Logic Interface Characteristics (1.80V ≤ VDDIO ≤ VDD1,2V). Limits in standard typeface are for TJ = +25˚C. Limits in boldface type apply over the operating ambient temperature range (−40˚C ≤ TA ≤ +85˚C). Symbol Parameter Conditions Min Typ Max Units LOGIC INPUTS SS, SI, SCK/SCL, PWM_LED, IF_SEL VIL Input Low Level VIH Input High Level II Logic Input Current fSCL Clock Frequency 0.5 VDDIO − 0.5 V V −1.0 1.0 2 µA I C Mode 400 kHz SPI Mode 8 MHz LOGIC OUTPUT SO VOL Output Low Level ISO = 3.0 mA VOH Output High Level ISO = −3.0 mA IL Output Leakage Current VSO = 2.8V 0.3 VDDIO − 0.5 0.5 VDDIO − 0.3 V V 1.0 µA 0.5 V 0.5 V LOGIC I/O SDA VOL Output Low Level ISDA = 3.0 mA 0.3 LOGIC INPUTS DME, AMODE (Internal pull down 1 MΩ) VIL Input Low Level VIH Input High Level VDDIO − 0.5 7 V www.national.com LP3950 Logic Interface Characteristics (Continued) (1.80V ≤ VDDIO ≤ VDD1,2V). Limits in standard typeface are for TJ = +25˚C. Limits in boldface type apply over the operating ambient temperature range (−40˚C ≤ TA ≤ +85˚C). Symbol Parameter Conditions Min Typ Max Units 6.0 µA Max Units 0.35 V 1.0 µA 200 kHz 0.5 V 0.35 V 6.0 µA Max Units 0.5 V 1.0 µA LOGIC INPUTS DME, AMODE (Internal pull down 1 MΩ) II Logic Input Current −1.0 Logic Interface Characteristics, Low I/O Voltage (1.65V ≤ VDDIO < 1.80V) . I2C compatible interface only. Symbol Parameter Conditions Min Typ LOGIC INPUTS SCL, PWM_LED, IF_SEL VIL Input Low Level VIH Input High Level II Logic Input Current fSCL Clock Frequency VDDIO − 0.35 V −1.0 I2C Mode LOGIC I/O SDA VOL Output Low Level ISDA = 3.0 mA 0.3 LOGIC INPUTS DME, AMODE (Internal pull down 1 MΩ) VIL Input Low Level VIH Input High Level II Logic Input Current VDDIO − 0.35 V −1.0 Logic Input NRST Characteristics (1.65V ≤ VDDIO ≤ VDD1,2V). Symbol Parameter VIL Input Low Level Conditions Min VIH Input High Level 1.3 II Logic Input Current −1.0 tNRST Reset Pulse Width Note: Guaranteed by design Typ V 10 µs Control Interface The LP3950 supports three different interface modes: 1) SPI interface (4 wire, serial) 2) I2C compatible interface (2 wire, serial) User can define the serial interface by the IF_SEL pin. The following table shows the pin configuration for both interface modes. Note that the pin configurations will be based on the status of the IF_SEL pin. 3) Direct enable (2 wire, enable lines) IF_SEL Interface Pin Configuration HIGH SPI SCK SI SO SS (clock) (data in) (data out) (chip select) LOW I2C Compatible SCL SDA SI SO (clock) (data in/out) (I2 address) (NC) Comment Use pull up resistor for SCL. Use pull up resistor for SDA. SI HIGH → address is 51’h; SI LOW → address is 50’h; Unused pin SO can be left unconnected. when data is sent out during a read cycle. A pull-up or pull-down resistor may be needed for SO line if a floating logic signal can cause unintended current consumption in the circuitry. The address and data are transmitted Most Significant Byte (MSB) first. The Slave Select signal (SS) must be low during the cycle transmission. SS resets the interface when high SPI Interface The transmission consists of 16-bit write and read cycles. One cycle consists of seven address bits, one read/write (R/W) bit and eight data bits. R/W bit high state defines a write cycle and low defines a read cycle. SO output is normally in high-impedance state and it is active only during www.national.com 8 is clocked in on the rising edge of the SCK clock signal, while data is clocked out on the falling edge of SCK. (Continued) and it has to be taken high between successive cycles. Data 20129307 FIGURE 2. SPI Write Cycle 20129308 FIGURE 3. SPI Read Cycle 20129309 FIGURE 4. SPI Timing Diagram 9 www.national.com LP3950 SPI Interface LP3950 SPI Timing Parameters VDD1 = VDD2 = VDDA = 2.70V to 2.90V, VDDIO = 1.80V to VDD1,2 V Symbol Limit Parameter Min Max Units 1 Cycle Time 80 ns 2 Enable Lead Time 40 ns 3 Enable Lag Time 40 ns 4 Clock Low Time 40 ns 5 Clock High Time 40 ns 6 Data Setup Time 0 ns 7 Data Hold Time 20 ns 8 Data Access Time 27 ns 9 Output Disable Time 27 ns 10 Output Data Valid 37 ns 11 Output Data Hold Time 0 ns 12 SS Inactive Time 15 ns Note: Data guaranteed by design. I2C Compatible Interface connected to VDDIO or GND (address selector). Maximum bit rate is 400 kbit/s (VDDIO 1.80V to VDD1,2V). I2C compatible interface can be used down to 1.65 VDDIO with maximum bit rate of 200 kbit/s. I2C SIGNALS In I2C compatible mode, the LP3950 pin SCL is used for the I2C clock and the SDA pin is used for the I2C data. Both these signals need a pull-up resistor according to I2C specification. The values of the pull-up resistors are determined by the capacitance of the bus (typ. A1.8k). Signal timing specifications are shown in Table I2C Timing Parameters . Unused pin SO can be left unconnected and pin SI must be I2C DATA VALIDITY The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW. 20129310 FIGURE 5. I2C Signals: Data Validity I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transition from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transition from LOW to HIGH while SCL is HIGH. The I2C master always generates www.national.com START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, the I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 10 LP3950 I2C Compatible Interface (Continued) 20129311 FIGURE 6. Start and Stop Conditions After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LP3950 address is 50’h or 51’h. The selection of the address is done by connecting SI pin to VDDIO (51 hex) or GND (50 hex). For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. 20129312 FIGURE 7. I2C Chip Address 20129313 w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = chip address, 50’h or 51’h for LP3950. FIGURE 8. I2C Write Cycle When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in Figure 9 . 11 www.national.com LP3950 I2C Compatible Interface (Continued) 20129314 FIGURE 9. I2C Read Cycle 20129341 FIGURE 10. I2C Timing Diagram I2C Timing Parameters (VDD1 = VDD2 = VDDA = 2.70V to 2.90V, VDDIO = 1.65V to VDD1,2 V) Symbol Parameter Limit Min Units Max 1 Hold Time (repeated) START Condition 0.6 µs 3.2 µs 2 Clock Low Time (1.65V ≤ VDDIO 2 Clock Low Time (1.80V ≤ VDDIO ≤ VDD1,2V) 1.3 µs 3 Clock High Time (1.65V ≤ VDDIO < 1.80V) 1200 ns 3 Clock High Time (1.80V ≤ VDDIO ≤ VDD1,2V) 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time (data output, delay generated by LP3950) 300 900 ns 5 Data Hold Time (data input) 0 900 ns 6 Data Setup Time 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns < 1.80V) 100 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.3 µs Cb Capacitive Load Parameter for Each Bus Line. Load of One Picofarad Corresponds to One Nanosecond. 10 NOTE: Data guaranteed by design www.national.com 12 200 ns The boost DC/DC converter generates a 4.1V–5.3V output voltage to drive LEDs from a single Li-Ion battery (3.0V to 4.5V). The output voltage is controlled with an eight-bit register in nine steps. The converter is a magnetic switching PWM mode DC/DC converter with a current limit. The converter has three options for switching frequency, 1.0 MHz, 1.67 MHz and 2.0 MHz (default), when the timing resistor RT is 82 kΩ. The LP3950 boost converter uses an unique pulse-skipping elimination method to stabilize the noise spectrum. Even with light load or no load a minimum length current pulse is fed to the inductor. An internal active load is used to remove the excess charge from the output capacitor when needed (Note 16). The boost converter should be disabled when there is no load to avoid idle current consumption. The topology of the magnetic boost converter is called CPM control, current programmed mode, where the inductor current is measured and controlled with the feedback. The output voltage control changes the resistor divider in the feedback loop. Figure 11 shows the boost topology with the protection circuitry. Four different protection schemes are implemented: 1. Over voltage protection, limits the maximum output voltage — Keeps the output below breakdown voltage — Prevents boost operation if the battery voltage is much higher than desired output 2. Over current protection, limits the maximum inductor current 3. — Voltage over switching NMOS is monitored; too high voltages turn the switch off Feedback (FB) protection for no connection 4. Duty cycle limit function, done with digital control Note 16: When the battery voltage is close to the output voltage, the output voltage may rise slightly over programmed value if the load on output is small and pulse-skipping elimination is active. 20129315 FIGURE 11. Boost Converter Functional Block Diagram Magnetic Boost DC/DC Converter Electrical Characteristics Limits in standard typeface are for TJ = +25˚C. Limits in boldface type apply over the operating ambient temperature range (−40˚C ≤ TA ≤ +85˚C). Unless otherwise noted, specifications apply to Figure 1 with: VDD1 = VDD2 = VDDA = 2.8V, CVDD1 = CVDD2 = CVDDA = CVDDIO = 100 nF, COUT = CIN = 10 µF, CVREF = 100 nF, L1 = 4.7 µH and fBOOST = 2.0 MHz (Note 12). Symbol Parameter Conditions ILOAD Load Current 3.0V ≤ VIN ≤ 4.5V VOUT = 5.0V VOUT Output Voltage Accuracy (FB Pin) 1.0 mA ≤ ILOAD ≤ 300 mA 3.0V ≤ VIN ≤ 4.5V VOUT = 5.0V (target value), autoload OFF Output Voltage (FB Pin) 1.0 mA ≤ ILOAD ≤ 300 mA 3.0V < VIN < 5.0V + V(SCHOTTKY), autoload OFF 1.0 mA ≤ ILOAD ≤ 300 mA VIN > 5V + V(SCHOTTKY) 13 Min Typ Max Units 0 300 mA −5 +5 % 5.0 V VIN–V(SCHOTTKY) V www.national.com LP3950 Magnetic Boost DC/DC Converter LP3950 Magnetic Boost DC/DC Converter Electrical Characteristics (Continued) Limits in standard typeface are for TJ = +25˚C. Limits in boldface type apply over the operating ambient temperature range (−40˚C ≤ TA ≤ +85˚C). Unless otherwise noted, specifications apply to Figure 1 with: VDD1 = VDD2 = VDDA = 2.8V, CVDD1 = CVDD2 = CVDDA = CVDDIO = 100 nF, COUT = CIN = 10 µF, CVREF = 100 nF, L1 = 4.7 µH and fBOOST = 2.0 MHz (Note 12). Typ Max Units RDSON Symbol Switch ON Resistance VDD1,2 = 2.8V, ISW = 0.5A 0.4 0.7 Ω fPWF PWM Mode Switching Frequency RT = 82 kΩ freq_sel[2:0] = 1XX 2.0 Frequency Accuracy 2.7 ≤ VDD1,2 ≤ 2.9 −6 RT = 82 kΩ −9 tPULSE Parameter Conditions Switch Pulse Minimum Width Min ±3 No Load SW Pin Current Limit +6 +9 tSTARTUP Startup Time ICL_OUT MHz 700 % 25 ns 15 ms 800 900 500 1000 mA Boost Standby Mode User can set the boost converter to STANDBY mode by writing the register bit EN_BOOST low when there is no load to avoid idle current consumption. When EN_BOOST is written high, the converter starts in PFM (Pulse Frequency Modulation) mode for 10 ms and then goes to PWM (Pulse Width Modulation ) mode. All RGB outputs are off during the 10 ms delay. Boost Output Voltage Control User can control the boost output voltage by eight-bit boost output voltage register according to the following table. BOOST[7:0] Register 0D’h Binary Hex BOOST Output Voltage (typical) BOOST[7:0] Register 0D’h Binary Hex BOOST Output Voltage (typical) 0000 0000 00 4.10 0001 1111 1F 4.85 0000 0001 01 4.25 0011 1111 3F 5.00 Default 0000 0011 03 4.40 0111 1111 7F 5.15 0000 0111 07 4.55 1111 1111 FF 5.30 0000 1111 0F 4.70 Boost Frequency Control The register ‘boost frequency’ has address 0C’h. The default value after reset is 07’h. ‘x’ means don’t care. FREQ_SEL[2:0] Frequency FREQ_SEL[2:0] Frequency 1xx 2.00 MHz 001 1.00 MHz 01x 1.67 MHz www.national.com 14 VIN = 3.6V, VOUT = 5.0V if not Boost Converter Efficiency Boost Frequency vs RT Resistor 20129316 20129320 Battery Current vs Voltage Battery Current vs Voltage 20129317 20129321 Boost Typical Waveforms at 100 mA Load Boost Startup with No Load 20129318 20129322 15 www.national.com LP3950 Boost Converter Typical Performance Characteristics otherwise stated. LP3950 Boost Converter Typical Performance Characteristics VIN = 3.6V, VOUT = 5.0V if not otherwise stated. (Continued) Boost Line Regulation Boost Load Transient Response, 50 mA to 100 mA 20129319 20129323 In the normal PWM mode the R, G and B switches are controlled in 3 phases (one phase per driver). During each phase the peak current set by an external ballast resistor is driven through the LED for the time defined by DUTY setting (0 µs to 50 µs). As a time averaged current this means 0% to 33% of the peak current. The PWM period is 150 µs and the pulse frequency is 6.67 kHz in normal mode. RGB LED Pattern Generator The LP3950 RGB outputs can be controlled either with audio synchronization or with RGB pattern generator. The pattern generator of LP3950 drives three independently controlled LED outputs (for example, R1, G1 and B1). The functionality is similar compared to RGB functionality of LP3936 and LP3933. The output of RGB pattern generator can be selected to drive RGB1 (R1-G1-B1), RGB2 (R2-G2-B2) or RGB1 and RGB2 (R1&R2 – G1&G2 – B1&B2) outputs. Programmable Pattern Mode User has control over the following parameters separately for each LED: • ON and OFF (start and stop time in blinking cycle) (PWM brightness control) • DUTY (dimming slope) • SLOPE (output enable control) • ENABLE The main blinking cycle is controlled with three-bit CYCLE control (0.25 / 0.5 / 1.0 / 2.0 / 4.0s). 20129325 FIGURE 13. Normal Mode PWM Waveforms at Different Duty Settings In the FLASH mode all the outputs are controlled in one phase and the PWM period is 50 µs. The time averaged FLASH mode current is three times the normal mode current at the same DUTY value. 20129324 FIGURE 12. RGB PWM Operating Principle RGB_START is the master control for the whole RGB function. The internal PWM and blinking control can be disabled by setting the RGB_PWM control LOW. In this case the individual enable controls can be used to switch outputs on and off. PWM_EN input can be used for external hardware PWM control. www.national.com 16 LP3950 Programmable Pattern Mode (Continued) 20129326 FIGURE 14. Example Blinking Waveforms RGB Driver Characteristics (R1, G1, B1, R2, G2, B2 outputs). Limits in standard typeface are for TJ = +25˚C. Limits in boldface type apply over the operating ambient temperature range (−40˚C ≤ TA ≤ +85˚C). Symbol Parameter Conditions Typ Max 3.5 6.0 Ω VFB = 5.0V, LED driver off 0.03 1.0 µA Maximum Slope Period At Maximum Duty Setting 0.93 s Minimum Slope Period At Maximum Duty Setting 31 ms tSRES Slope Resolution At Maximum Duty Setting 62 ms tSTART/STOP Start/Stop Resolution Cycle 1.0s 1/16 s Duty Duty Step Size RDS-ON ON Resistance ILEAKAGE Off State Leakage Current tSMAX tSMIN Min Units 1/16 ±3 tBLINK Blinking Cycle Accuracy DCYCF Duty Cycle Range EN_FLASH = 1 0 DCYC Duty Cycle Range EN_FLASH = 0 0 DRESF Duty Resolution EN_FLASH = 1 (4-bit) 6.64 % DRES Duty Resolution EN_FLASH = 0 (4-bit) 2.21 % fPWMF PWM Frequency EN_FLASH = 1 20 kHz fPWM PWM Frequency EN_FLASH = 0 6.67 kHz RGB LED PWM Control −6 +6 % 99.6 % 33.2 % (Note 17) RDUTY[3:0] GDUTY[3:0] BDUTY[3:0] DUTY sets the brightness of the LED by adjusting the duty cycle of the PWM driver. The minimum DUTY cycle is 0% [0000] and the maximum in the flash mode is A 100% [1111]. The peak pulse current is determined by the external resistor, LED forward voltage drop and the boost voltage. In the normal mode the maximum duty cycle is 33%. RSLOPE[3:0] GSLOPE[3:0] BSLOPE[3:0] SLOPE sets the turn-on and turn-off slopes. Fastest slope is set by [0000] and slowest by [1111]. SLOPE changes the duty cycle at constant, programmable rate. For each slope setting the maximum slope time appears at maximum DUTY setting. When DUTY is reduced, the slope time decreases proportionally. For example, in case of maximum DUTY, the sloping time can be adjusted from 31 ms [0000] to 930 ms [1111]. For DUTY [0111] the sloping time is 14 ms [0000] to 434 ms [1111]. The blinking cycle has no effect on SLOPE. RON[3:0] GON[3:0] BON[3:0] ON sets the beginning time of the turn-on slope. The on-time is relative to the selected blinking cycle length. On-setting N (N = 0–15) sets the on-time to N/16 * cycle length. 17 www.national.com LP3950 RGB LED PWM Control ROFF[3:0] GOFF[3:0] BOFF[3:0] ROFF[3:0] GOFF[3:0] BOFF[3:0] (Note 17) (Continued) OFF sets the beginning time of the turn-off slope. Off-time is relative to blinking cycle length in the same way as on-time. If ON = 0, OFF = 0 and RGB_PWM = 1, then RGB outputs are continuously on (no blinking), the DUTY setting controls the brightness and the SLOPE control is ignored. If ON and OFF are the same, but not 0, RGB outputs are turned off. CYCLE[2:0] CYCLE sets the blinking cycle: [000] for 0.25s, [001] for 0.5s, [010] for 1.0s, [011] for 2.0s. and [1XX] for 4.0s CYCLE effects to all RGB LEDs. RSW1 GSW1 BSW1 RSW2 GSW2 BSW2 Enable Enable Enable Enable Enable Enable RGB_START Master Switch for both RGB drivers: RGB_START = 0 → RGB OFF RGB_START = 1 → RGB ON, starts the new cycle from t = 0 RGB_PWM = 0 → RSW, GWS and BSW control directly the RGB outputs (on/off control only) RGB_PWM = 1 → Normal PWM RGB functionality (duty, slope, on/off times, cycle) RGB_PWM EN_FLASH R1_PWM G1_PWM B1_PWM R2_PWM G2_PWM B2_PWM for for for for for for R1 switch G1 switch B1 switch R2 switch G2 switch B2 switch Flash mode enable control for RGB1 and RGB2. In the flash mode (EN_FLASH = 1) RGB outputs are PWM controlled simultaneously, not in 3-phase system as in the normal mode. xx_PWM = 0 → External PWM control from PWM_LED pin is disabled xx_PWM = 1 → External PWM control from PWM_LED pin is enabled Internal PWM control (DUTY) can be used independently of external PWM control. External PWM has the same effect on all enabled outputs. Note 17: The LP3933 shares the same pattern generator. Application Note AN-1291, “Driving RGB LEDs Using LP3933 Lighting Management System” contains a thorough description of the RGB driver functionality including programming examples. PWM_LED input can be used as a direct on/off or PWM brightness control for selected RGB outputs. For example it can trigger the flash using a flash signal from the camera. If PWM_LED input is not used, it must be tied to VDDIO. www.national.com 18 The LEDs connected to the RGB outputs can be synchronized to incoming audio signal with Audio Synchronization feature. Audio Synchronization has two modes. Amplitude mode synchronizes LEDs based on the peak amplitude of the input signal. In the amplitude mode the user can select one of three amplitude mapping options. The frequency mode synchronizes the LEDs based on bass, middle and treble amplitudes (= low pass, band pass and high pass filters). The user can select between two different responses of frequency for best audio-visual user experience. Both of the modes provide a control for speed of the mapping with four different speed configurations. Programmable gain and AGC (Automatic Gain Control) function are also available for adjustment of the optimum audio signal mapping. The Audio Synchronization functionality is described more closely below. If the input signal is a PWM signal, use a first or second order low pass filter to convert the digital PWM audio signal into an analog waveform. There are two parameters that need to be known to get the filter to work successfully: frequency of the PWM signal and the voltage level of the PWM signal. Suggested cut-off frequency (-3dB) should be around 2 kHz to 4 kHz and the stop-band attenuation at sampling frequency should be around -48dB or better. Use a resistor divider to reduce the digital signal amplitude to meet the specification of the analog audio input. Because a loworder low-pass filter attenuates the high-frequency components from audio signal, MODE_CONTROL=[01] selection is recommended when frequency synchronization mode is enabled. Figure 23 shows an example of a second order RC-filter for 29 kHz PWM signal with 3.3V amplitude. Active filters, such as a Sallen-Key filter, may also be applied. An active filter gives better stop-band attenuation and cut-off frequency can be higher than for a RC-filter. INPUT SIGNAL TYPE The LP3950 support four types of analog audio input signals for audio synchronization 1. Single ended audio To make sure that the filter rolls off sufficiently quickly, connect your filter circuit to the audio input(s), turn on the audio synchronization feature, set manual gain to maximum, apply the PWM signal to the filter input and keep an eye on LEDs. If they are blinking without an audio signal (modulation), a sharper roll-off after the cut-off frequency, more stop-band attenuation, or smaller amplitude of the PWM signal is required. 2. Differential audio 3. Stereo 4. Single ended and differential audio. Figure 15 shows how to wire the LP3950 audio inputs case by case (NC = Not Connected). Schematic Diagram 20129327 FIGURE 15. Wiring Diagram for LP3950 Audio Inputs 19 www.national.com LP3950 USING A DIGITAL PWM AUDIO SIGNAL AS AN AUDIO SYNCHRONIZATION SOURCE Audio Synchronization LP3950 Audio Synchronization (Continued) AUDIO SYNCHRONIZATION SIGNAL PATH LP3950 audio synchronization is mainly done digitally and it consists of following signal path blocks (see Figure 17) • Input buffers • Multiplexer • AD converter • DC remover INPUT BUFFERING Figure 16 describes the LP3950 audio input buffering structure in high level. The electric parameters of the buffers are described in Table Audio Synchronization Characteristics. Operational amplifiers for both buffers are rail-to-rail input opamps. The single ended buffer is simply a voltage follower. DC level of the input signal is generated by a resistor divider. The differential amplifier is a basic differential-to-singleended converter. • • • • • • • Schematic Diagram Automatic gain control (AGC) / programmable gain 3 band digital filter Peak detector Look-up tables (LUT) Mode selector Integrators PWM generator 20129331 FIGURE 16. Audio Input Buffer Structure Functional Block Diagram 20129332 FIGURE 17. Signal Path Block Diagram synchronization the three-way crossover FILTER separates high pass, low pass and band pass signals. For both modes, a predefined lookup table (LUT) is used to match the audio visual effect. The MODE SELECTOR selects the synchronization mode. Reaction speed can be selected using INTEGRATOR speed variables. Finally PWM GENERATOR sets the driver FETs duty cycles. The digitized input signal has a DC component that is removed by the digital DC REMOVER (-3 dB @ A400 Hz). The automatic GAIN CONTROL adjusts the input signal to suitable range automatically. User can disable AGC and the gain can be set manually with PROGRAMMABLE GAIN. The LP3950 has two audio synchronization modes: amplitude and frequency. For amplitude based synchronization the PEAK DETECTION method is used. For frequency based www.national.com 20 LP3950 Audio Synchronization (Continued) Audio Synchronization Characteristics Min Typ Zin Symbol Input Impedance of AD1, AD2, ASE pins 200 500 AIN_SINGLE Audio Input Level Range (peak-to-peak), Single Ended Audio 0.1 VDDA −0.1 V Audio Input Level Range (peak-to-peak), Differential Audio 0.1 VDDA −0.1 V AIN_DIFF Parameter Conditions Max Units kΩ Crossover Frequencies (−3 dB) f3 dB Narrow Frequency Response Low Pass Band Pass High Pass 0.5 1.0 and 1.5 2.0 Wide Frequency Response Low Pass Band Pass High Pass 1.0 2.0 and 3.0 4.0 kHz CONTROL OF AUDIO SYNCHRONIZATION The following table describes the controls required for audio synchronization. Note that these controls are functional when using serial interface (I2C or SPI) for device control. Also LP3950 audio synchronization functionality is illustrated in Figure 18. Audio Synchronization Control EN_SYNC Audio synchronization enabled. Set EN_SYNC = 1 to enable audio synchronization or 0 to disable. SYNC_MODE Synchronization mode selector. Set SYNC_MODE = 0 for amplitude synchronization. Set SYNC_MODE = 1 for frequency synchronization. MODE_CTRL[1:0] See below: Mode control EN_AGC Automatic gain control. Set EN_AGC = 1 to enable automatic control or 0 to disable. When EN_AGC is disabled, the audio input signal gain value is defined by GAIN_SEL. GAIN_SEL[2:0] Input signal gain control. Gain has a range from 0 dB to 21 dB with 3 dB steps: [000] ... 0 dB [011] ... 9 dB [110] ... 18 dB [001] ... 3 dB [100] ... 12 dB [111] ... 21 dB [010] ... 6 dB [101] ... 15 dB INPUT_SEL[1:0] [00] ... Single ended input signal, ASE. [01] ... Differential input signal, AD1 and AD2. [10] ... Stereo input or single ended and differential input signal. Note: Sum of input signals divided by 2. [11] ... No input Please see Figure 15 for wiring. SPEED_CTRL[1:0] Control for speed of the mapping. Sets the reaction speed (or "sampling rate") for the audio input signal: [00] ... FASTEST [01] ... FAST [10] ... MEDIUM [11] ... SLOW In the amplitude mode fMAX = 3.8 Hz, in the frequency mode fMAX = 7.6 Hz. 21 www.national.com LP3950 Audio Synchronization (Continued) 20129328 FIGURE 18. LP3950 Audio Synchronization Functionality MODE CONTROL IN THE FREQUENCY MODE signal passed through the bandpass filter is used to control green LEDs (G1 and/or G2 PWM outputs) and high pass signal controls blue LEDs (B1 and/or B2 PWM outputs). Finally, the user can select the desired mapping speed by SPEED_CTRL[1:0]. Of course, the user can connect any color LED to any output in his/her own application (i.e. the red output does not need to drive a red LED). Maximum duty cycle is A100% as in the Flash mode (not 33% as in the normal mode of the pattern generator, which is described in Table RGB LED PWM Control ). During the frequency mode (SYNC_MODE = 1) the user can select between two filter options by MODE_CTRL[1:0] as shown below (Figure 19). User can select the filters based on the music type and light effect requirements. Filter options: Left figure, wide frequency response; MODE_CTRL[1:0] is set to [00], [10] or [11]. Right figure, narrow frequency response: MODE_CTRL[1:0] set to [01]. Signal passed through the lowpass filter is used to control the duty cycle of red LEDs (R1 and/or R2 PWM outputs), the 20129333 20129334 FIGURE 19. Cross-over Frequencies. Left: Wide Frequency Response. Right: Narrow Frequency Response www.national.com 22 mapping options give different light responses as shown in Figure 20. Again, the user can select the desired mapping speed by SPEED_CTRL[1:0]. Maximum duty cycle is A100%. If MODE_CTRL[1:0] = 11 and SYNC_MODE = 0, audio synchronization is inactive. (Continued) MODE CONTROL IN THE AMPLITUDE MODE During the amplitude synchronization mode (SYNC_MODE = 0) the user can select between three different amplitude mappings by using MODE_CTRL[1:0] select. These three 20129340 20129338 MODE_CTRL[1:0] = [10] = MODE2 MODE_CTRL[1:0] = [00] = MODE0 Note 18: This figure is for illustrating purpose only and does not necessarily represent the accurate function of the circuit. 20129339 MODE_CTRL[1:0] = [01] = MODE1 FIGURE 20. Amplitude Synchronization Mapping Options synchronization mode. In the default mode default control register values are used, see Table LP3950 Control Register Names and Default Values. Please refer to Figure 22 on Typical Applications section at the end of this document for wiring. MODE CONTROL IN THE DEFAULT MODE One of the main benefits of LP3950 is the default mode, which enables user to build applications without I2C or SPI control. The LP3950 is set to the default mode when DME pin is high. DME pin high –state forces registers NSTBY and EN_SYNC to the high [1] state so that the start-up sequence get started (see start-up sequence on Section Modes of Operation ). Function of LP3950 in the default mode of operation is controlled by AMODE pin. If AMODE is pulled low the LP3950 is in the amplitude synchronization mode. If the AMODE pin is pulled high the LP3950 is in the frequency RGB OUTPUT SELECTOR The usage of RGB outputs (RGB1 and RGB2) can be selected with RGB_SEL[1:0] control bits. Audio synchronization and RGB pattern generator output can be connected to RGB ports as shown in the following table. 23 www.national.com LP3950 Audio Synchronization LP3950 Audio Synchronization (Continued) RGB Output Control RGB_SEL[0] RGB_SEL[1] RGB1 Output Control RGB2 Output Control 0 0 Pattern Generator Pattern Generator 1 0 Audio Sync Pattern Generator 0 1 Pattern Generator Audio Sync 1 1 Audio Sync Audio Sync www.national.com 24 OUTPUT CAPACITOR, COUT The output capacitor COUT directly affects the magnitude of the output ripple voltage. In general, the higher the value of COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR (Equivalent Series Resistance) are the best choice. At the lighter loads, the low ESR ceramics offer a much lower VOUT ripple than the higher ESR tantalums of the same value. At the higher loads, the ceramics offer a slightly lower VOUT ripple magnitude than the tantalums of the same value. However, the dv/dt of the VOUT ripple with the ceramics is much lower that the tantalums under all load conditions. Capacitor voltage rating must be sufficient, 10V is recommended. INDUCTOR, L1 LP3950’s high switching frequency enables the use of a small surface mount inductor. A 4.7 µH shielded inductor is suggested for 2.0 MHz switching frequency. Values below 2.2 µH should not be used at 2.0 MHz. At lower switching frequencies 4.7 µH inductors should always be used. The inductor should have a saturation current rating higher than the peak current it will experience during circuit operation (A1.0A). Less than 300 mΩ ESR is suggested for high efficiency. Open core inductors cause flux linkage with circuit components and, thus, may interfere with the normal operation of the circuit. This should be avoided. For high efficiency, choose an inductor with a high frequency core material such as ferrite to reduce the core losses. To minimize radiated noise, use a toroid, pot core or shielded core inductor. The inductor should be connected to the SW pin as close to the IC as possible. Examples of suitable inductors are TDK type VLF4012AT- 4R7M1R1 and Coilcraft type MSS4020472MLD. Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction with the increased applied voltage. The capacitance value can fall to below half of the nominal capacitance. Too low output capacitance can make the boost converter unstable. INPUT CAPACITOR, CIN The input capacitor CIN directly affects the magnitude of the input ripple voltage and to a lesser degree the VOUT ripple. A higher value CIN will give a lower VIN ripple. Capacitor voltage rating must be sufficient, 10V is recommended. OUTPUT DIODE, D1 A Schottky diode should be used for the output diode. To maintain high efficiency the average current rating of the schottky diode should be larger than the peak inductor cur- List of Recommended External Components Symbol Symbol Explanation Value Unit Type CVDD1 VDD1 Bypass Capacitor 100 nF Ceramic, X5R CVDD2 VDD2 Bypass Capacitor 100 nF Ceramic, X5R COUT Output Capacitor from FB to GND 10 ± 10% µF Ceramic, X5R CIN Input Capacitor from Battery Voltage to GND 10 ± 10% µF Ceramic, X5R CVDDIO VDD_IO Bypass Capacitor 100 nF Ceramic, X5R CVDDA VDDA Bypass Capacitor 100 nF Ceramic, X5R C1,2,3 Audio Input Capacitors 10 nF Ceramic, X5R 1% (Note 19) RT Oscillator Frequency Bias Resistor 82 kΩ RSO SO Output Pull-up Resistor 100 kΩ CVREF Reference Voltage Capacitor, between VREF and GND 100 nF L1 Boost Converter Inductor 4.7 µH Rectifying Diode, VF @ Maxload 0.3 V D1 Ceramic, X5R Shielded, Low ESR, ISAT A1.0A Schottky Diode RGB LED Red, Green, Blue or White LEDs RRX, RGX, RBX User Defined Current Limit Resistors Note 19: Resistor RT tolerance change will change the timing accuracy of RGB block. Also the boost converter switching frequency will be affected. the inductor and the schottky diode very close to the integrated circuit and use wide routings for those components. Sensitive components should be placed far from those components with high pulsating current. A ground plane is recommended. The power switch loop (the switch is on) has the greatest affect on noise generation. The loop is formed by the input PCB Design Guidelines Printed circuit board layout is critical to low noise operation and good performance of the LP3950. Bypass capacitors should be close to the VDD pins of the integrated circuit. Special attention must be given to the routing of the switching loops. Lengths of these loops should be minimized. It is essential to place the input capacitor, the output capacitor, 25 www.national.com LP3950 rent (A1.0A). Schottky diodes with a low forward drop and fast switching speeds are ideal for increasing efficiency in portable applications. Choose a reverse breakdown of the schottky diode larger than the output voltage. Do not use ordinary rectifier diodes, since slow switching speeds and long recovery times cause the efficiency and the load regulation to suffer. Recommended External Components LP3950 PCB Design Guidelines (Continued) capacitor, the inductor, the SW pin, the GND_BOOST pin and the ground plane, as shown by the dashed line in Figure 21. The other switching loop, the rectifier loop, is formed by the input capacitor, the inductor, the diode, the output capacitor and the ground plane, as shown by the dotted line. Arrange the components so that the switching current loops curl in the same direction (see arrows in Figure 21). See also Application Note AN 1149, Layout Guidelines for Switching Mode Power Supplies. 20129342 FIGURE 21. The Current Loops www.national.com 26 LP3950 Typical Applications 20129335 FIGURE 22. The LP3950 Set to the Default Mode 27 www.national.com LP3950 Typical Applications (Continued) 20129336 NC = Not Connected Here, a second order RC-filter is used on the ASE input to convert a PWM signal to an analog waveform. FIGURE 23. Typical Application of LP3950 When the SPI Interface Is Used www.national.com 28 LP3950 Typical Applications (Continued) 20129343 There may be cases where the audio input signal going into the LP3950 is too weak for audio synchronization. This figure presents a single-supply inverting amplifier connected to the ASE input for audio signal amplification. The amplification is +20 dB, which is well enough for 20 mVp-p audio signal. Because the amplifier (LMV321) is operating in single supply voltage, a voltage divider using R3 and R4 is implemented to bias the amplifier so the input signal is within the input common-mode voltage range of the amplifier. The capacitor C4 is placed between the inverting input and resistor R1 to block the DC signal going into the audio signal source. The values of R1 and C4 affect the cutoff frequency, fc = 1/(2*Pi*R1*C4), in this case it is around 160 Hz. As a result, the LMV321 output signal is centered around mid-supply, that is VDD/2. The output can swing to both rails, maximizing the signal-to-noise ratio in a low voltage system FIGURE 24. Backlight and Keypad LEDs Controlled by the Pattern Generator - Funlight LEDs Controlled by Audio Synchronization 29 www.national.com www.national.com 30 AUDIO SYNC CONTROL 2 2B CYCLE PWM 07 AUDIO SYNC CONTROL 1 BLUE SLOPE & DUTY CYCLE 06 2A GREEN SLOPE & DUTY CYCLE 05 BOOST OUTPUT VOLTAGE RED SLOPE & DUTY CYCLE 04 0D BLUE ON/OFF 03 BOOST FREQUENCY GREEN ON/OFF 02 0C RED ON/OFF 01 ENABLES RGB CONTROL 00 0B SETUP ADDR (HEX) GAIN_SEL[2] 1 BOOST[7] 0 CYCLE[2] 0 CYCLE[1] 0 BSLOPE[3] 0 GSLOPE[3] 0 RSLOPE[3] 0 BON[3] 0 GON[3] 0 RON[3] 0 RGB PWM 0 D7 GAIN_SEL[1] 0 BOOST[6] 0 NSTBY 0 CYCLE[0] 0 BSLOPE[2] 0 GSLOPE[2] 0 RSLOPE[2] 0 BON[2] 0 GON[2] 0 RON[2] 0 RGB START 0 D6 GAIN_SEL[0] 1 BOOST[5] 1 EN_BOOST 0 R1_PWM 0 BSLOPE[1] 0 GSLOPE[1] 0 RSLOPE[1] 0 BON[1] 0 GON[1] 0 RON[1] 0 RSW1 0 D5 SYNC_MODE 0 BOOST[4] 1 EN_FLASH 0 G1_PWM 0 BSLOPE[0] 0 GSLOPE[0] 0 RSLOPE[0] 0 BON[0] 0 GON[0] 0 RON[0] 0 GSW1 0 D4 MODE_CTRL[1] 0 EN_AGC 1 BOOST[3] 1 B1_PWM 0 BDUTY[3] 0 GDUTY[3] 0 RDUTY[3] 0 BOFF[3] 0 GOFF[3] 0 ROFF[3] 0 BSW1 0 D3 LP3950 Control Register Names and Default Values MODE_CTRL[0] 1 EN_SYNC 0 BOOST[2] 1 FREQ_SEL[2] 1 AUTOLOAD_EN 1 R2_PWM 0 BDUTY[2] 0 GDUTY[2] 0 RDUTY[2] 0 BOFF[2] 0 GOFF[2] 0 ROFF[2] 0 RSW2 0 D2 SPEED_CTRL[1] 0 INPUT_SEL[0] 1 BOOST[1] 1 FREQ_SEL[1] 1 RGB_SEL[1] 1 G2_PWM 0 BDUTY[1] 0 GDUTY[1] 0 RDUTY[1] 0 BOFF[1] 0 GOFF[1] 0 ROFF[1] 0 GSW2 0 D1 SPEED_CTRL[0] 1 INPUT_SEL[0] 0 BOOST[0] 1 FREQ_SEL[0] 1 RGB_SEL[0] 1 B2_PWM 0 BDUTY[0] 0 GDUTY[0] 0 RDUTY[0] 0 BOFF[0] 0 GOFF[0] 0 ROFF[0] 0 BSW2 0 D0 LP3950 LP3950 Color LED Driver with Audio Synchronizer Physical Dimensions inches (millimeters) unless otherwise noted 32-Lead Thin CSP Package, 4.5 x 5.5 x 0.8 mm, 0.5 mm Pitch NS Package Number SLD32A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 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