NSC LP39542TL

LP39542
Advanced Lighting Management Unit
General Description
Features
LP39542 is an advanced lighting management unit for handheld devices. It drives any phone lights including display
backlights, RGB, keypad and camera flash LEDs. The boost
DC-DC converter drives high current loads with high efficiency. White LED backlight drivers are high efficiency low voltage
structures with excellent matching and automatic fade in/ fade
out function. The stand-alone command based RGB controller is feature rich and easy to configure. Built-in audio
synchronization feature allows user to synchronize the color
LEDs to audio input. Integrated high current driver can drive
camera flash LED or motor/vibra. Internal ADC can be used
for ambient light or temperature sensing. The flexible I2C interface allows easy control of LP39542. Small micro SMD
package together with minimum number of external components is a best fit for handheld devices.
■
■
■
■
■
■
■
■
■
■
■
Audio synchronization for color/RGB LEDs
Command based PWM controlled RGB LED drivers
Programmable ON/OFF blinking sequences for RGB LED
High current driver for flash LED with built-in timing and
safety feature.
4+2 or 6 low voltage constant current white LED drivers
with programmable 8-bit adjustment (0...25 mA/LED)
High efficiency Boost DC-DC converter
I2C compatible interface
Possibility for external PWM dimming control
Possibility for clock synchronization for RGB timing
Ambient light and temperature sensing possibility
Small package – microSMD-36, 3.0 x 3.0 x 0.6 mm
Applications
■ Cellular Phones
■ PDAs, MP3 players
Typical Applications
30008560
© 2007 National Semiconductor Corporation
300085
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LP39542 Advanced Lighting Management Unit
August 2007
LP39542
Connection Diagrams and Package Mark Information
CONNECTION DIAGRAMS
MicroSMD-36 Package, 3.0 x 3.0 x 0.6 mm, 0.5 mm pitch NS Package Number TLA36AAA or
MicroSMDxt-36 Package, 3.0 x 3.0 x 0.65 mm, 0.5 mm pitch NS Package Number RLA36AAA
30008503
30008504
PACKAGE MARK
30008505
Ordering Information
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Order Number
Package Marking
Supplied As
Spec/Flow
LP39542TL
D58B
TNR 250
NoPb
LP39542TLX
D58B
TNR 1000
NoPb
LP39542RL
D58B
TNR 250
NoPb
LP39542RLX
D58B
TNR 1000
NoPb
2
LP39542
Pin Descriptions
Pin #
Name
Type
6F
SW
Output
Description
6E
FB
Input
Boost Converter Feedback
6D
FLASH
Output
High Current Flash Output
6C
R1
Output
Red LED 1 Output
6B
G1
Output
Green LED 1 Output
6A
B1
Output
Blue LED 1 Output
Boost Converter Power Switch
5F
GND_SW
Ground
Power Switch Ground
5E
GND
Ground
Ground
5D
VDDIO
Power
Supply Voltage for Logic Input/Output Buffers and Drivers
5C
SDA
Logic Input/Output
5B
IRGB
Input
5A
GND_RGB
Ground
Ground for RGB Currents
4F
GND_WLED
Ground
Ground for WLED Currents
4E
IFLASH
Input
4D
SYNC_PWM
Logic Input
External PWM Control for LEDs or External Clock for RGB Sync
4C
ADDR_SEL
Logic Input
Address Select (I2C)
4B
NRST
Logic Input
Reset Pin
4A
R2
Output
Red LED 2 Output
3F
WLED5
Output
White LED 5 Output
3E
WLED6
Output
White LED 6 Output
Supply Voltage
Serial Data In/Out (I2C)
Bias Current Set Resistor for RGB Drivers
High Current Flash Current Set Resistor
3D
VDD1
Power
3C
FLASH_EN
Logic Input
Enable for High Current Flash
3B
SCL
Logic Input
Clock (I2C)
3A
G2
Output
Green LED 2 Output
2F
WLED3
Output
White LED 3 Output
White LED 4 Output
2E
WLED4
Output
2D
ASE
Input
Audio Synchronization Input
2C
IRT
Input
Oscillator Frequency Resistor
2B
GNDT
Ground
Ground
2A
B2
Output
Blue LED 2 Output
1F
WLED1
Output
White LED 1 Output
1E
WLED2
Output
White LED 2 Output
1D
GNDA
Ground
Ground for Analog Circuitry
1C
VREF
Output
Reference Voltage
1B
VDDA
Power
Internal LDO Output
1A
VDD2
Power
Supply Voltage
3
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LP39542
Operating Ratings
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V (SW, FB, R1-2, G1-2, B1-2,
FLASH, WLED1-6)(Notes 3, 4)
VDD1, VDD2, VDDIO, VDDA
Voltage on ASE, IRT, IFLASH,
IRGB, VREF
Voltage on Logic Pins
V(all other pins): Voltage to GND
I (VREF)
I(R1, G1, B1, R2, G2, B2)
I(FLASH)(Note 5)
Continuous Power Dissipation
(Note 6)
Junction Temperature (TJ-MAX)
Storage Temperature Range
Maximum Lead Temperature
(Soldering) (Note 7)
ESD Rating (Note 8)
Human Body Model:
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(Notes 1, 2)
V (SW, FB, WLED1-6, R1-2, G1-2,
B1-2, FLASH)
VDD1,2 with external LDO
VDD1,2 with internal LDO
VDDA
VDDIO
Voltage on ASE
Recommended Load Current
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
(Note 9)
-0.3V to +7.2V
-0.3V to +6.0V
-0.3V to VDD1+0.3V
with 6.0V max
-0.3V to VDDIO +0.3V
with 6.0V max
-0.3V to 6.0V
10 μA
100 mA
400 mA
Internally Limited
0 to 6.0V
2.7 to 5.5V
3.0 to 5.5V
2.7 to 2.9V
1.65V to VDD1
0.1V to VDDA –0.1V
0 mA to 400 mA
-30°C to +125°C
-30°C to +85°C
Thermal Properties
Junction-to-Ambient Thermal
Resistance(θJA), TLA36AAA or
RLA36AAA Package
(Note 10)
150°C
-65°C to +150°C
260°C
2 kV
4
60°C/W
(Notes 2, 11)
Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the operating ambient temperature range (-30°C
< TA < +85°C). Unless otherwise noted, specifications apply to the LP39542 Block Diagram with: VDD1 = VDD2 = 3.6V, VDDIO = 2.8V,
CVDD = CVDDIO = 100 nF, COUT = CIN = 10 μF, CVDDA = 1 μF, CREF = 100 nF, L1 = 4.7 μH, RFLASH = 910Ω, RRGB = 5.6 kΩ and RRT
= 82 kΩ (Note 12).
Symbol
IVDD
Parameter
Standby supply current
(VDD1 + VDD2)
Condition
Min
Typ
Max
Units
1
8
μA
450
μA
1
mA
NSTBY (bit) = L, NRST (pin) = H
SCL=H, SDA = H
No-boost supply current NSTBY (bit) = H,
(VDD1 + VDD2)
EN_BOOST(bit) = L
SCL = H, SDA = H
Audio sync and LEDs OFF
IVDDIO
IEXT_LDO
VDDA
No-load supply current
(VDD1 + VDD2)
NSTBY (bit) = H,
EN_BOOST (bit) = H
SCL = H, SDA = H
Audio sync and LEDs OFF
Autoload OFF
RGB drivers
(VDD1 + VDD2)
CC mode at R1, G1, B1 and R2, G2, B2 set to 15 mA
SW mode
150
150
μA
WLED drivers
(VDD1 + VDD2)
4+2 banks IOUT = 25.5 mA per LED
500
μA
Audio synchronization
(VDD1 + VDD2)
Audio sync ON
VDD1,2 = 2.8V
390
μA
VDD1,2 = 3.6V
700
Flash
(VDD1 + VDD2)
I(RFLASH) = 1 mA
Peak current during flash
2
VDDIO Standby Supply
current
NSTBY (bit)=L
SCL = H, SDA = H
External LDO output
current
(VDD1, VDD2, VDDA)
7V tolerant application only
IBOOST = 300 mA
Output voltage of internal (Note 13)
LDO for analog parts
2.72
-3
2.80
mA
1
μA
6.5
mA
2.88
+3
V
%
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pins.
Note 3: Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime.
Note 4: Voltage tolerance of LP39542 above 6.0V relies on fact that VDD1 and VDD2 (2.8V) are available (ON) at all conditions. If VDD1 and VDD2 are not available
(ON) at all conditions, National Semiconductor does not guarantee any parameters or reliability for this device.
Note 5: The total load current of the boost converter in worst-case conditions is limited to 300 mA (min. input and max. output voltage).
Note 6: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=160°C (typ.) and disengages at
TJ=140°C (typ.).
Note 7: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip
Scale Package or Application note AN1412: Micro SMDxt Wafer Lever Chip Scale Package
Note 8: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 9: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Note 10: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 11: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 12: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
Note 13: VDDA output is not recommended for external use.
5
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LP39542
Electrical Characteristics
LP39542
Block Diagram
30008506
www.national.com
6
RESET:
In the RESET mode all the internal registers are reset to the default values and the chip goes to STANDBY
mode after reset. NSTBY control bit is low after reset by default. Reset is active always if NRST input pin is
low or internal Power On Reset is active. LP39542 can be also reset by writing any data to Reset Register
in address 60H. Power On Reset (POR) will activate during the chip startup or when the supply voltage
VDD2 falls below 1.5V. Once VDD2 rises above 1.5V, POR will inactivate and the chip will continue to the
STANDBY mode.
STANDBY:
The STANDBY mode is entered if the register bit NSTBY is LOW. This is the low power consumption mode,
when all circuit functions are disabled. Registers can be written in this mode and the control bits are effective
immediately after power up.
STARTUP:
When NSTBY bit is written high, the INTERNAL STARTUP SEQUENCE powers up all the needed internal
blocks (Vref, Bias, Oscillator etc..). To ensure the correct oscillator initialization, a 10 ms delay is generated
by the internal state-machine. If the chip temperature rises too high, the Thermal Shutdown (TSD) disables
the chip operation and STARTUP mode is entered until no thermal shutdown event is present.
BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is raised in PFM
mode during the 10 ms delay generated by the state-machine. The Boost startup is entered from Internal
Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH. During
the 10 ms Boost Startup time all LED outputs are switched off to ensure smooth start-up.
NORMAL:
During NORMAL mode the user controls the chip using the Control Registers. The registers can be written
in any sequence and any number of bits can be altered in a register in one write
30008507
7
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LP39542
Modes of Operation
LP39542
Magnetic Boost DC/DC Converter
The LP39542 Boost DC/DC Converter generates a 4.0 – 5.3V
voltage for the LEDs from single Li-Ion battery (3V…4.5V).
The output voltage is controlled with an 8-bit register in 9
steps. The converter is a magnetic switching PWM mode DC/
DC converter with a current limit. The converter has three options for switching frequency, 1 MHz, 1.67 MHz and 2 MHz
(default), when timing resistor RT is 82 kΩ. Timing resistor
defines the internal oscillator frequency and thus directly affects boost frequency and all circuit's internally generated
timing (RGB, Flash, WLED fading).
The LP39542 Boost Converter uses pulse-skipping elimination to stabilize the noise spectrum. Even with light load or no
load a minimum length current pulse is fed to the inductor. An
active load is used to remove the excess charge from the
output capacitor at very light loads. At very light load and when
input and output voltages are very close to each other, the
pulse skipping is not completely eliminated. Output voltage
should be at least 0.5V higher than input voltage to avoid
pulse skipping. Reducing the switching frequency will also
reduce the required voltage difference.
Active load can be disabled with the en_autoload bit. Disabling will increase the efficiency at light loads, but the downside is that pulse skipping will occur. The Boost Converter
should be stopped when there is no load to minimise the current consumption.
The topology of the magnetic boost converter is called CPM
control, current programmed mode, where the inductor current is measured and controlled with the feedback. The user
can program the output voltage of the boost converter. The
output voltage control changes the resistor divider in the feedback loop.
The following figure shows the boost topology with the protection circuitry. Four different protection schemes are implemented:
1.
2.
3.
4.
Over voltage protection, limits the maximum output
voltage
— Keeps the output below breakdown voltage.
— Prevents boost operation if battery voltage is much
higher than desired output.
Over current protection, limits the maximum inductor
current
— Voltage over switching NMOS is monitored; too high
voltages turn the switch off.
Feedback break protection. Prevents uncontrolled
operation if FB pin gets disconnected.
Duty cycle limiting, done with digital control.
30008508
Boost Converter Topology
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8
Symbol
Parameter
Conditions
Min
Typ
Max
3.0V ≤ VIN
VOUT = 5V
0
3.0V ≤ VIN
VOUT = 4V
0
400
Output Voltage Accuracy
(FB Pin)
3.0V ≤ VIN ≤ VOUT - 0.5
VOUT = 5.0V
−5
+5
Output Voltage
(FB Pin)
1 mA ≤ ILOAD ≤ 300 mA
VIN > 5V + V(SCHOTTKY)
VIN–V(SCHOTTKY)
RDSON
Switch ON Resistance
VDD1,2 = 2.8V, ISW = 0.5A
0.4
fboost
PWM Mode Switching
Frequency
RT = 82 kΩ
freq_sel[2:0] = 1XX
Frequency Accuracy
2.7 ≤ VDDA ≤ 2.9
−6
RT = 82 kΩ
−9
ILOAD
Load Current
VOUT
Units
300
mA
V
0.8
2
tPULSE
Switch Pulse Minimum
Width
no load
tSTARTUP
Startup Time
Boost startup from STANDBY
ISW_MAX
SW Pin Current Limit
Ω
MHz
±3
+6
+9
25
%
ns
10
700
550
%
ms
800
900
950
mA
Boost Output Voltage Control
BOOST STANDBY MODE
User can stop the Boost Converter operation by writing the
Enables register bit EN_BOOST low. When EN_BOOST is
written high, the converter starts for 10 ms in PFM mode and
then goes to PWM mode.
BOOST OUTPUT VOLTAGE CONTROL
User can control the boost output voltage by boost output 8bit register.
Boost Output [7:0]
Register 0DH
Boost Output
Voltage (typical)
Bin
Hex
0000 0000
00
4.00
0000 0001
01
4.25
0000 0011
03
4.40
0000 0111
07
4.55
0000 1111
0F
4.70
0001 1111
1F
4.85
0011 1111
3F
5.00 Default
0111 1111
7F
5.15
1111 1111
FF
5.30
30008509
BOOST FREQUENCY CONTROL
freq_sel[2:0]
frequency
1XX
2.00 MHz
01X
1.67 MHz
001
1.00 MHz
Register ‘boost freq’ (address 0EH). Register default value
after reset is 07H.
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LP39542
Magnetic Boost DC/DC Converter Electrical Characteristics
LP39542
Boost Converter Typical Performance Characteristics
Vin = 3.6V, Vout = 5.0V if not otherwise stated
Boost Converter Efficiency
Boost Typical Waveforms at 100mA Load
30008511
30008510
Battery Current vs Voltage
Battery Current vs Voltage
30008512
30008513
Boost Line Regulation
Boost Startup with No Load
30008514
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30008515
10
LP39542
Boost Load Transient, 50 mA–100 mA
Boost Switching Frequency
30008516
30008517
Output Voltage vs Load Current
Efficiency at Low Load vs Autoload
30008562
30008561
11
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LP39542
Functionality of Color LED Outputs (R1, G1, B1; R2, G2, B2)
LP39542 has 2 sets of RGB/color LED outputs. Both sets
have 3 outputs and the sets can be controlled in 4 different
ways:
CURRENT CONTROL OF COLOR LED OUTPUTS (R1, R2,
G1, G2, B1, B2)
Both RGB output sets can be separately controlled as constant current sinks or as switches. This is done using
cc_rgb1/2 bits in the RGB control register. In constant current
mode one or both RGB output sets are controlled with constant current sinks (no external ballast resistors required).
The maximum output current for both drivers is set by one
external resistor RRGB. User can decrease the maximum current for an individual LED driver by programming as shown
later.
The maximum current for all RGB drivers is set with RRGB.
The equation for calculating the maximum current is
1.
Command based pattern generator control (internal
PWM)
2. Audio synchronization control
3. Programmable ON/OFF blinking sequences for RGB1
4. External PWM control
By using command based pattern generator user can program any kind of color effect patterns. LED intensity, blinking
cycles and slopes are independently controlled with 8 16-bit
commands. Also real time commands are possible as well as
loops and step by step control. If analog audio is available on
system, the user can use audio synchronization for synchronizing LED blinking to the music. The different modes
together with the various sub modes generate very colorful
and interesting lighting effects. Direct ON/OFF control is
mainly for switching on and off LEDs. External PWM control is for applications where external PWM signal is available
and required to control the color LEDs. PWM signal can be
connected to any color LED separately as shown later.
IMAX = 100 × 1.23V / (RRGB + 50Ω)
where
IMAX - maximum RGB current in any RGB output in constant
current mode
1.23V - reference voltage
100 - internal current mirror multiplier
RRGB- resistor value in Ohms
50Ω - internal resistor in the IRGB input
For example if 22mA is required for maximum RGB current
RRGB equals to
COLOR LED CONTROL MODE SELECTION
The RGB_SEL[1:0] bits in the Enables register (08H) control
the output modes for RGB1 (R1, G1, B1) and RGB2 (R2, G2,
B2) outputs as seen in the following table.
RGB_SEL
[1:0]
Audio sync
Pattern
generator
00
-
RGB1 & RGB2
-
01
-
RGB2
RGB1
10
RGB2
RGB1
-
11
RGB1 & RGB2
-
-
RRGB=100×1.23V / IMAX–50Ω=123V / 0.022A–50Ω=5.54kΩ
Each individual RGB output has a separate maximum current
programming. The control bits are in registers RGB1 max
current and RGB2 max current (12H and 13H) and programming is shown in table below. The default value after
reset is 00b.
Blinking
control
RGB Control register (00H) has control bits for direct on/off
control of all color LEDs. Note that the LEDs have to be turned
on in order to control them with audio synchronization or pattern generator.
The external PWM signal can control any LED depending on
the control register setup. External PWM signal is connected
to PWM/SYNC pin. The controls are in the Ext. PWM Control
register (address 07H) except the FLASH control in HC_Flash
(10H) register as follows:
bit 7 PWM controls WLED 1-4
wled5-6_pwm
bit 6 PWM controls WLED 5-6
r1_pwm
bit 5 PWM controls R1 output
g1_pwm
bit 4 PWM controls G1 output
b1_pwm
bit 3 PWM controls B1 output
r2_pwm
bit 2 PWM controls R2 output
g2_pwm
bit 1 PWM controls G2 output
b2_pwm
bit 0 PWM controls B2 output
hc_pwm
bit 5 PWM controls FLASH
HC_Flash (10H)
Note: If DISPL=1, wled1-4pwm controls WLED1-6
Note: Maximum external PWM frequency is 1kHz. If during the external
PWM control the internal PWM is on, the result will be product of both
functions.
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Maximum
current/output
00
0.25 × IMAX
01
0.50 × IMAX
10
0.75 × IMAX
11
1.00 × IMAX
SWITCH MODE
The switch mode is used if there is a need to connect parallel
LEDs to output or if the RGB output current needs to be increased.
Please note that the switch mode requires an external ballast resistors at each output to limit the LED current.
The switch/current mode and on/off controls for RGB are in
the RGB_ctrl register (00H).
Ext. PWM Control (07H)
wled1-4_pwm
IR1[1:0], IG1[1:0],
IB1[1:0], IR2[1:0],
IG2[1:0], IB2[1:0]
12
LP39542
RGB_ctrl register (00H)
CC_RGB1
bit7
CC_RGB2
bit6
r1sw
bit5
g1sw
bit4
b1sw
bit3
r2sw
bit2
g2sw
bit1
b2sw
bit0
1 R1, G1 and B1 are switches → limit current with ballast resistor
0 R1, G1 and B1 are constant current sinks, current limited internally
1 R2, G2 and B2 are switches → limit current with ballast resistor
0 R2, G2 and B2 are constant current sinks, current limited internally
1 R1 is on
0 R1 is off
1 G1 is on
0 G1 is off
1 B1 is on
0 B1 is off
1 R2 is on
0 R2 is off
1 G2 is on
0 G2 is off
1 B2 is on
0 B2 is off
30008518
13
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LP39542
Since registers are 8-bit long one command requires 2 write
cycles. Each command has intensity level for each LED, command execution time (CET) and transition time (TT) as seen
in the following figures.
Command Based Pattern Generator
for Color LEDs
The LP39542 has an unique stand-alone command based
pattern generator with 8 user controllable 16-bit commands.
30008519
COMMAND REGISTER WITH 8 COMMANDS
COMMAND 1
COMMAND 2
COMMAND 3
COMMAND 4
COMMAND 5
ADDRESS 50H
R2
R1
R0
G2
G1
G0
CET3
CET2
ADDRESS 51H
CET1
CET0
B2
B1
B0
TT2
TT1
TT0
CET2
ADDRESS 52H
R2
R1
R0
G2
G1
G0
CET3
ADDRESS 53H
CET1
CET0
B2
B1
B0
TT2
TT1
TT0
ADDRESS 54H
R2
R1
R0
G2
G1
G0
CET3
CET2
ADDRESS 55H
CET1
CET0
B2
B1
B0
TT2
TT1
TT0
ADDRESS 56H
R2
R1
R0
G2
G1
G0
CET3
CET2
ADDRESS 57H
CET1
CET0
B2
B1
B0
TT2
TT1
TT0
CET2
ADDRESS 58H
R2
R1
R0
G2
G1
G0
CET3
ADDRESS 59H
CET1
CET0
B2
B1
B0
TT2
TT1
TT0
COMMAND 6
ADDRESS 5AH
R2
R1
R0
G2
G1
G0
CET3
CET2
ADDRESS 5BH
CET1
CET0
B2
B1
B0
TT2
TT1
TT0
COMMAND 7
ADDRESS 5CH
R2
R1
R0
G2
G1
G0
CET3
CET2
ADDRESS 5DH
CET1
CET0
B2
B1
B0
TT2
TT1
TT0
ADDRESS 5EH
R2
R1
R0
G2
G1
G0
CET3
CET2
ADDRESS 5FH
CET1
CET0
B2
B1
B0
TT2
TT1
TT0
COMMAND 8
COLOR INTENSITY CONTROL
Each color has 3-bit intensity level. Level control is logarithmic, 2 curves are selectable. The LOG bit in register 11H
defines the curve used as seen in the following table.
R[2:0], G[2:0],
B[2:0]
LOG=0
LOG=1
0
0
001
7
1
010
14
2
011
21
4
100
32
10
101
46
21
110
71
46
111
100
100
000
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CURRENT
[% × IMAX(COLOR)]
30008520
14
CET [3:0]
CET duration, ms
0000
197
0001
393
0010
590
0011
786
0100
983
0101
1180
0110
1376
0111
1573
1000
1769
1001
1966
1010
2163
1011
2359
1100
2556
1101
2753
CET [3:0]
CET duration, ms
1110
2949
1111
3146
LP39542
COMMAND EXECUTION TIME (CET) AND TRANSITION TIME (TT)
The command execution CET time is the duration of one single command. Command execution times CET are defined as
follows, when RT=82kΩ:
Transition time TT is duration of transition from the previous
RGB value to programmed new value. Transition times TT
are defined as follows:
TT [2:0]
Transition time, ms
000
0
001
55
010
110
011
221
100
442
101
885
110
1770
111
3539
The figure below shows an example of RGB CET and TT
times.
30008521
The command execution time also may be less than the transition time – the figure below illuminates this case.
30008522
15
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LP39542
is 0000 0000 and 0000 0000 in one command register. The
loop will start from command 1 and continue until stopped by
writing rgb_start=0 or loop=0. The example of loop is shown
in following figure:
LOOP CONTROL
Pattern generator commands can be looped using the LOOP
bit (D1) in Pattern gen ctrl register (11H). If LOOP=1 the program will be looped from the command 8 register or if there
30008523
SINGLE PROGRAM
If control bit LOOP=0 the program will start from Command 1
and run to either last command or to empty “0000 0000 / 0000
0000” command.
30008524
The LEDs maintain the brightness of the last command when
the single program stops. Changes in command register will
not be effective in this phase. The RGB_START bit has to be
toggled off and on to make changes effective.
START BIT
Pattern_gen_ctrl register’s RGB_START bit will enable
command execution starting from Command 1.
Pattern gen ctrl register (11H)
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rgb_start
Bit 2
0 – Pattern generator disabled
1 – execution pattern starting from command 1
loop
Bit 1
0 – pattern generator loop disabled (single pattern)
1 – pattern generator loop enabled (execute until stopped)
log
Bit 0
0 – color intensity mode 0
1 – color intensity mode 1
16
The color LEDs connected to RGB outputs can be synchronized to incoming audio with Audio Synchronization feature.
Audio Sync has 2 modes. Amplitude mode synchronizes
color LEDs based on input signal’s peak amplitude. In the
amplitude mode the user can select between 3 different amplitude mapping modes and 4 different speed configurations.
The frequency mode synchronizes the color LEDs based on
bass, middle and treble amplitudes (= low pass, band pass
and high pass filters). User can select between 2 different
frequency responses and 4 different speed configurations for
best audio-visual user experience. Programmable gain and
AGC function are also available for adjustment of input signal
amplitude to light response. The Audio Sync functionality is
described more closely below.
PWM signal with 3.3V amplitude. Active filters, such as a
Sallen-Key filter, may also be applied. An active filter gives
better stop-band attenuation and cut-off frequency can be
higher than for a RC-filter.
To make sure that the filter rolls off sufficiently quickly, connect your filter circuit to the audio input(s), turn on the audio
synchronization feature, set manual gain to maximum, apply
the PWM signal to the filter input and keep an eye on LEDs.
If they are blinking without an audio signal (modulation), a
sharper roll-off after the cut-off frequency, more stop-band
attenuation, or smaller amplitude of the PWM signal is required.
AUDIO SYNCHRONIZATION SIGNAL PATH
LP39542 audio synchronization is mainly done digitally and it
consists of the following signal path blocks:
• Input Buffers
• AD Converter
• DC Remover
• Automatic Gain Control (AGC)
• Programmable Gain
• 3 Band Digital Filter
• Peak Detector
• Look-up Tables (LUT)
• Mode Selector
• Integrators
• PWM Generator
• Output Drivers
USING A DIGITAL PWM AUDIO SIGNAL AS AN AUDIO
SYNCHRONIZATION SOURCE
If the input signal is a PWM signal, use a first or second order
low pass filter to convert the digital PWM audio signal into an
analog waveform. There are two parameters that need to be
known to get the filter to work successfully: frequency of the
PWM signal and the voltage level of the PWM signal. Suggested cut-off frequency (-3 dB) should be around 2 kHz to 4
kHz and the stop-band attenuation at sampling frequency
should be around -48 dB or better. Use a resistor divider to
reduce the digital signal amplitude to meet the specification
of the analog audio input. Because a low-order low-pass filter
attenuates the high-frequency components from audio signal,
MODE_CTRL=01b selection is recommended when frequency synchronization mode is enabled. Application example 5
shows an example of a second order RC-filter for 29 kHz
30008525
The digitized input signal has DC component that is removed
by digital DC REMOVER (-3 dB @ 400 Hz). Since the light
response of input audio signal is very much amplitude dependent the AGC adjusts the input signal to suitable range
automatically. User can disable AGC and the gain can be set
manually with PROGRAMMABLE GAIN. LP39542 has 2 audio synchronization modes: amplitude and frequency. For
amplitude based synchronization the PEAK DETECTION
method is used. For frequency based synchronization 3
BAND FILTER separates high pass, low pass and band bass
signals. For both modes the predefined LUT is used to optimize the audio visual effect. MODE SELECTOR selects the
synchronization mode. Different response times to music
beat can be selected using INTEGRATOR speed variables.
Finally PWM GENERATOR sets the driver FET duty cycles.
scribed in the Audio Synch table. The buffer is rail-to-rail input
operational amplifier connected as a voltage follower. DC level of the input signal is set by a simple resistor divider
INPUT SIGNAL TYPE AND BUFFERING
LP39542 supports single ended audio input as shown in the
figure below. The electric parameters of the buffer are de-
30008526
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LP39542
Audio Synchronization
LP39542
AUDIO SYNCHRONIZATION ELECTRICAL PARAMETERS
Symbol
Parameter
Conditions
ZIN
Input Impedance of ASE
AIN
Audio Input Level Range
(peak-to-peak)
f3dB
Gain = 21 dB
Gain = 0 dB
Crossover Frequencies (-3 dB)
Narrow Frequency Response
Wide Frequency Response
Min
Typical
250
500
Max
kΩ
V
0.1
VDDA-0.1
Low Pass
Band Pass
High Pass
Low Pass
Band Pass
High Pass
0.5
1.0 and 1.5
2.0
1.0
2.0 and 3.0
4.0
CONTROL OF ADC AND AUDIO SYNCHRONIZATION
The following table describes the controls required for audio synchronization.
Audio_sync_CTRL1 (2AH)
Input signal gain control. Range 0...21 dB, step 3 dB:
GAIN_SEL[2:0]
Bits 7-5
[000] = 0 dB (default)
[001] = 3 dB
[010] = 6 dB
[011] = 9 dB
[100] = 12 dB
[101] = 15 dB
[110] = 18 dB
[111] = 21 dB
Synchronization mode selector.
SYNC_MODE
Bit 4
SYNCMODE = 0 → Amplitude Mode (default)
SYNCMODE = 1 → Frequency Mode
EN_AGC
EN_SYNC
INPUT_SEL[1:0]
Bit 3
Automatic Gain Control enable
1 = enabled
0 = disabled (Gain Select enabled) (default)
Bit 2
Audio synchronization enable
1 = Enabled
Note : If AGC is enabled, AGC gain starts from current GAIN_SEL gain value.
0 = Disabled (default)
[00] = Single ended input signal, ASE.
[01] = Temperature measurement
Bits 1-0
[10] = Ambient light measurement
[11] = No input (default)
Audio_sync_CTRL2 (2BH)
EN_AVG
Bit 4
0 – averaging disabled (not applicable in audio sync mode)
1 – averaging enabled (not applicable in audio sync mode)
MODE_CTRL[1:0]
Bits 3-2 See below: Mode control
SPEED_CTRL[1:0]
Sets the LEDs light response time to audio input.
[00] = FASTEST (default)
[01] = FAST
Bits 1-0 [10] = MEDIUM
[11] = SLOW
(For SLOW setting in amplitude mode fMAX= 3.8 Hz,
Frequency mode fMAX = 7.6 Hz)
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Units
18
kHz
Lower frequency mode
MODE_CTRL = 01 and SYNC_MODE = 1
Higher frequency mode
MODE_CTRL = 00 and SYNC_MODE = 1
30008527
30008528
MODE_CTRL select. These three mapping options give different light response. The modes are presented in the following graphs.
MODE CONTROL IN AMPLITUDE MODE
During the amplitude synchronization mode user can select between three different amplitude mappings by using
Non-overlapping mode
MODE_CTRL[1:0] = [01]
Partly overlapping mode
MODE_CTRL[1:0] = [00]
30008529
30008530
19
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LP39542
based on the music type and light effect requirements. In the
first mode the frequency range extends to 8 kHz in the secont
to 4 kHz.
The lowpass filter is used for the red, the bandpass filter for
the blue and the hipass filter for the green LED.
MODE CONTROL IN FREQUENCY MODE
Mode control has two setups based on audio synchronization
mode select: the frequency mode and the amplitude mode.
During the frequency mode user can select two filter options
by MODE_CTRL as shown below. User can select the filters
LP39542
Overlapping mode
MODE_CTRL[1:0] = [10]
Peak Input Signal Level
Range vs Gain Setting
30008532
30008531
2. Feed SYNC/PWM pin with 5 MHz clock
By this the internal 5 MHz clock is disabled from pattern generator and flash timing circuitry.
The external clock signal frequency will fully determine the
timings related to RGB and Flash.
Note: The boost converter will use internal 5 MHz clock even
if the external clock is available.
RGB Output Synchronization to
External Clock
The RGB pattern generator and high current flash driver timing can be synchronized to external clock with following configuration.
1.
Set PWM_SYNC bit in Enables register to 1
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20
LP39542 has a possibility to drive indicator LEDs with RGB1
outputs with programmable blinking time. Blinking function is
enabled with RGB_SEL[1:0] bits set as 01b in 0BH register.
R1_CYCLE_EN, G1_CYCLE_EN and B1_CYCLE_EN bits in
cycle registers (02H, 04H and 06H) enable/disable blinking
function for corresponding output. When EN_BLINK bit is
written high in register 11H, the blinking sequences for all
outputs (which has CYCLE_EN bit enabled) starts simultaneously. EN_BLINK bit should be written high after selecting
wanted blinking sequences and enabling CYCLE_EN bits, to
R1, G1 and B1 Blink Registers (01H, 03H and 05H):
Name
Bit
Description
R1_ON[3:0], R1_OFF[3:0]
G1_ON[3:0], G1_OFF[3:0]
B1_ON[3:0], B1_OFF[3:0]
7-4, 3-0
RGB1 ON and OFF time
Blinking ON/OFF cycle is defined so that there will be first
OFF-period then ON-period after which follows an off-period
for the remaining cycle time that can not be set. If OFF and
ON times are together more than 100% the first OFF time will
be as set and the ON time is cut to meet 100%. For example,
Bits
ON/OFF time
0000
0%
0001
1%
0010
2.5%
0011
5%
0100
7.5%
0101
10%
0110
15%
0111
20%
1000
30%
1001
40%
1010
50%
1011
60%
1100
70%
1101
80%
1110
90%
1111
100%
if 50% OFF time is set and ON time is set greater than 50%,
only 50% ON time is used, the exceeding ON time is ignored.
If OFF and ON times are together less than 100% the remaining cycle time output is OFF.
30008570
21
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LP39542
synchronize outputs to get desired lighting effect. R1SW,
G1SW and B1SW bits can be used to enable and disable
outputs when wanted.
RGB1 blinking sequence is set with R1, G1 and B1 blink registers (01H, 03H and 05H) by setting the appropriate OFF-ON
times. Blinking cycle times are set with R1_CYCLE[2:0],
G1_CYCLE[2:0] and B1_CYCLE[2:0] bits in R1, G1 and B1
CYCLE registers (02H, 04H and 06H). OFF/ON time is a percentage of the selected cycle time. Values for setting OFF/
ON time can be seen in following table.
RGB LED Blinking Control
LP39542
Values for setting the blinking cycle for RGB1 can be seen in
following table:
R1, G1 and B1 Cycle Registers (02H, 04H and 06H):
Name
Bit
Decription
R1_CYCLE_EN
G1_CYCLE_EN
B1_CYCLE_EN
3
Blinking enable
0 = disabled
1 = enabled, output state is defined with blinking
cycle
R1_CYCLE[2:0]
G1_CYCLE[2:0]
B1_CYCLE[2:0]
2-0
RGB1 cycle time
Bits
Blinking cycle
time
Blinking
frequency
000
0.1s
10 Hz
001
0.25s
4 Hz
010
0.5s
2 Hz
011
1s
1 Hz
100
2s
0.5 Hz
101
3s
0.33 Hz
110
4s
0.25 Hz
111
5s
0.2 Hz
PATTERN_GEN_CTRL Register (11H):
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Name
Bit
EN_BLINK
3
Description
Blinking sequence start bit
0 = disabled
1 = enabled
22
Symbol
Parameter
ILEAKAGE
R1, G1, B1, R2, G2, B2 pin leakage
current
Condition
IRGB
Maximum recommended sink current
Min
Typ
Max
Units
0.1
1
μA
CC mode
40
mA
SW mode
50
mA
Accuracy @ 37mA
RRGB=3.3 kΩ ±1%, CC mode
Current mirror ratio
CC mode
±5
%
1:100
RGB1 and RGB2 current mismatch
IRGB=37mA, CC mode
±5
RSW
Switch resistance
SW mode
2.5
5
Ω
fRGB
RGB switching frequency
Accuracy proportional to internal clock
freq.
20
21.8
kHz
If SYNC to external 5 MHz clock is in
use
18.2
%
20
kHz
Note: RGB current should be limited as follows:
constant current mode – limit by external RRGB resistor;
switch mode – limit by external ballast resistors
Output Current vs Pin Voltage (Current Sink Mode)
Pin Voltage vs Output Current (Switch Mode)
30008566
30008568
Output Current vs RRGB (Current Sink Mode)
30008567
23
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LP39542
RGB Driver Electrical Characteristics (R1, G1, B1, R2, G2, B2 Outputs)
LP39542
Single High Current Driver
LP39542 has internal constant current driver that is capable
of driving high current LED, mainly targeted for FLASH LED
in camera phone applications.
HC[1:0] bits in the HC_Flash register control the FLASH current as show in following table.
MAXIMUM CURRENT SETUP FOR FLASH
The user sets the maximum current of FLASH with RFLASH
resistor based on following equation:
IMAX = 300 × 1.23V / (RFLASH + 50Ω),
where
Imax = maximum flash current in Amps (ie. 0.3A)
1.23V = reference voltage
300 = internal current mirror multiplier
RFLASH = Resistor value in Ohms
HC[1:0]
I(FLASH)
00
0.25 × IMAX(FLASH)
01
0.50 × IMAX(FLASH)
10
0.75 × IMAX(FLASH)
11
1.00 × IMAX(FLASH)
The figure below shows the internal structure for the FLASH
driver.
50Ω = Internal resistor in the IFLASH input
For example if 400mA is required for the maximum flash current, RFLASH equals to
RFLASH = 300 × 1.23V / IMAX – 50Ω = 369V / 0.4A – 50Ω =
873Ω e.g. 910Ω resistor can be used
CURRENT CONTROL FOR FLASH
To minimize the internal current consumption, the flash function has an enable bit EN_HCFLASH in the HC_Flash register.
EN_
HCFLASH
MODE
0
FLASH disabled, no extra current
consumption through RFLASH
1
FLASH enabled, IFLASH set by
HC_SW[1:0] (see below)
30008533
FLASH TIMING
Flash output is turned on in lower current View finder mode
when the EN_HCFLASH bit is written high. The actual flash
at maximum current starts when the FLASH_EN digital input
pin goes high. The Flash length can be selected from 3 predefined values or the FLASH_EN pin pulse length can determine how long the flash pulse is. After flash pulse the flash is
shut down completely. To enable flash again, EN_HCFLASH
bit must be set to 0 and then 1.The pulse length is controlled
by the FT_T[1:0] bits in register 10H as show in the table below.
FL_T[1:0]
Flash duration typ
Current during view finder/
focusing
Current during FLASH
00
200ms
Set by HC[1:0]
HC[11] = IMAX(FLASH)
01
400ms
Set by HC[1:0]
HC[11] = IMAX(FLASH)
10
600ms
Set by HC[1:0]
HC[11] = IMAX(FLASH)
11
EN_FLASH on duration
Set by HC[1:0]
HC[11] = IMAX(FLASH)
After the flash pulse the EN_HCFLASH bit has to be written
low, the LP39542 does not clear this bit automatically. If 11b
is selected in the FL_T[1:0] register, then it is possible to use
safety bit EN_SAFETY in register 10H. When EN_SAFETY
is 1, then the flash is shut down automatically, if the
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FLASH_EN pulse duration is longer than 1.2 seconds (typ.).
This prevents any damage to the application circuitry, if the
FLASH_EN pin is stuck high because of user or program error.
24
LP39542
The following figure shows the functionality of the built-in flash
30008534
Flash LED can be controlled also with external PWM signal:
HC_FLASH Register (10H):
Name
Bit
HC_PWM
5
Description
Flash external PWM control
0 = Flash external PWM control disabled
1 = Flash external PWM control enabled
High Current Driver Electrical Characteristics
Symbol
Parameter
ILEAKAGE
FLASH pin leakage current
IMAX(FLASH)
Maximum Sink Current
Accuracy
Condition
Flash safety time
Typ
0.1
RFLASH = 910Ω
Current mirror ratio
tSAFETY
Min
-10
-5
Max
Units
2
μA
400
mA
10
5
%
1:300
EN_SAFETY = 1, FL_T = 11b
25
1.2
s
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LP39542
Backlight Drivers
LP39542 has 2 independent backlight drivers. Both drivers
are regulated constant current sinks. LED current for both
LED banks (WLED1…4 and WLED5…6) are controlled by 8bit current mode DACs with 0.1 mA step.
WLED1…4 and WLED5…6 can be also controlled with one
DAC for better matching allowing the use of larger displays
having up to 6 white LEDs in parallel.
Display configuration is controlled with DISPL bit as shown in
the following table.
DISPL
Configuration
Matching
0
Main display up
to 4 LEDs
Sub display up
to 2 LEDs
Good btw
WLED1…4
Good btw
WLED5…6
1
Large display
up to 6 LEDs
Good btw
WLED 1…6
30008535
30008536
Main display up to 4 LEDs (WLED1…4)
Sub display driver up to 2 LEDs (WLED5…6)
30008537
Main display up to 6 LEDs (WLED1…6) (DISPL=1)
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WLED dimming, SLOPE=0
WLED dimming, SLOPE=1
30008539
30008540
WLED Control Register (08H):
Name
Bit
Description
SLOPE_W5_6
6
Slope for WLED5-6
0 = Full range fade execution time 1.30s
1 = Full range fade execution time 0.65s
SLOPE_W1_4
5
Slope for WLED1-4
0 = Full range fade execution time 1.30s
1 = Full range fade execution time 0.65s
EN_FADE_W5_6
4
Enable fade for WLED5-6
0 = Fade disabled
1 = Fade enabled
EN_FADE_W1_4
3
Enable fade for WLED1-4
0 = Fade disabled
1 = Fade enabled
DISPL
2
Large display mode enable
0 = WLED1-4 and WLED5-6 are controlled
separately
1 = WLED1-4 and WLED5-6 are controlled with
WLED1-4 controls
EN_W1_4
1
Enable WLED1-4
0 = WLED1-4 disabled
1 = WLED1-4 enabled
EN_W5_6
0
Enable WLED5-6
0 = WLED5-6 disabled
1 = WLED5-6 enabled
27
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LP39542
slope of the fade curve. The fading times are shown in the
graphs, which corresponds the full range current change
(0-255). Note that when large display mode is selected (DISPL = 1), then EN_FADE_W5_6 and SLOPE_W5_6 bits do not
have any effect.
FADE IN / FADE OUT
LP39542 has an automatic fade in and out for main and sub
backlight. The fade function is enabled to main and sub backlights with EN_FADE_W1_4 and EN_FADE_W5_6 register
bits. Register bits SLOPE_W1_4 and SLOPE_W5_6 set the
LP39542
WLED Output Current vs. Voltage
ADJUSTMENT
WLED1-4[7:0]
WLED5-6[7:0]
Driver current,
mA (typical)
0000 0000
0
0000 0001
0.1
0000 0010
0.2
0000 0011
0.3
…
…
…
…
1111 1101
25.3
1111 1110
25.4
1111 1111
25.5
30008538
Backlight Driver Electrical Characteristics
Symbol
IMAX
Parameter
Conditions
Maximum Sink Current
Min
Typical
Max
Units
21.3
25.5
29.4
mA
0.03
1
μA
12.8
14.78
+16
mA
%
Ileakage
Leakage Current
IWLED1
WLED1 Current tolerance
IWLED1 set to 12.8 mA (80H)
Imatch1-4
Sink Current Matching
ISINK = 13 mA, Between WLED1…4
0.2
%
Imatch5-6
Sink Current Matching
ISINK = 13 mA, Between WLED5…6
0.2
%
Imatch1-6
Sink Current Matching
ISINK = 13 mA, Between WLED1…6
0.3
%
Note: Matching is the maximum difference from the average.
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10.52
-18
LP39542
Ambient Light and Temperature Measurement with LP39542
The Analog-to-Digital converter (ADC) in the Audio Syncronization block can be also used for ambient light measurement or temperature measurement.
The selection between these modes is controlled with input
selector bits INPUT_SEL[1:0] in register 2AH as seen on the
following table. Internal averaging function can be used to filter unwanted noise from the measured signal. Averaging
function can be enabled with EN_AVG bit in register 2BH.
INPUT_SEL[1:0]
Mode
00
Audio synchronization
01
Temperature measurement
(voltage input)
10
Ambient light measurement
(current input)
11
No input
EN_AVG = 0
Averaging disabled. fsample = 122 Hz,
data in register changes every 8.2 ms.
EN_AVG = 1
Averaging enabled. fsample = 244 Hz,
averaging of 64 samples, data in
register changes every 262 ms
(3.2Hz).
30008564
ADC Code vs Input Current
in Light Measurement Mode
TEMPERATURE MEASUREMENT
The temperature measurement requires two external components: resistor and thermistor (resistor that has known temperature vs resistance curve). The ADC reads the voltage
level at ASE pin and converts the result into a digital word.
User can read the ADC output from register. The known temperature allows for example to monitor the temperature inside
the display module and decrease the current level of the LEDs
if temperature raises too high. This function may increase
lifetime of LEDs in some applications.
AMBIENT LIGHT MEASUREMENT
The ambient light measurement requires only one external
component: Ambient light sensor (photo transistor or diode).
The ADC reads the current level at ASE pin and converts the
result into a digital word. User can read the ADC output from
the ADC output register. The known ambient light condition
allows user to set the backlight current to optimal level thus
saving power especially in low light and bright sunlight condition.
30008542
Temperature sensor connection example
30008541
ASE Input Configuration for Light Measurement
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LP39542
EXAMPLE TEMP SENSOR READING AT DIFFERENT
TEMPERATURES (R25°C = 1MΩ)
30008563
ADC Code vs Input Voltage
in temperature measurement mode
30008543
Example curve for thermistor
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30
T(°C)
R(MΩ)
Rt(MΩ)
V(ASE)
-40
1
60
2.7540984
2.24
0
1
4
25
1
1
1.4
60
1
0.2
0.4666667
100
1
0.04
0.1076923
To shield LP39542 from high input voltages 6…7.2V the use
of external 2.8V LDO is required. This 2.8V voltage protects
internally the device against high voltage condition. The rec-
30008544
In cases where high voltage is not an issue the connection is
as shown below
30008545
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LP39542
ommended connection is as shown in the picture below.
Internally both logic and analog circuitry works at 2.8V supply
voltage. Both supply voltage pins should have separate filtering capacitors.
7V Shielding
LP39542
Logic Interface Electrical Characteristics
(1.65V ≤ VDDIO ≤ VDD1,2V) (Unless otherwise noted).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.2×VDDIO
V
1.0
μA
400
kHz
0.5
V
1.0
μA
LOGIC INPUTS ADDR_SEL, NRST, SCL, SYNC_PWM, FLASH_EN, SDA
VIL
Input Low Level
VIH
Input High Level
IL
Logic Input Current
fSCL
Clock Frequency
0.8×VDDIO
V
−1.0
LOGIC OUTPUT SDA
VOL
Output Low Level
ISDA = 3 mA
IL
Output Leakage Current VSDA = 2.8V
0.3
Note: Any unused digital input pin has to be connected to GND to avoid floating and extra current consumption.
I2C Compatible Interface
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I2C master always generates
START and STOP bits. The I2C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, I2C master can generate repeated START
conditions. First START and repeated START conditions are
equivalent, function-wise.
INTERFACE BUS OVERVIEW
The I2C compatible synchronous serial interface provides access to the programmable functions and registers on the
device. This protocol uses a two-wire interface for bi-directional communications between the devices connected to the
bus. The two interface lines are the Serial Data Line (SDA),
and the Serial Clock Line (SCL). These lines should be connected to a positive supply, via a pull-up resistor and remain
HIGH even when the bus is idle. Every device on the bus is
assigned a unique address and acts as either a Master or a
Slave depending on whether it generates or receives the serial clock (SCL).
DATA TRANSACTIONS
One data bit is transferred during each clock pulse. Data is
sampled during the high state of the serial clock (SCL). Consequently, throughout the clock’s high period, the data should
remain stable. Any changes on the SDA line during the high
state of the SCL and in the middle of a transaction, aborts the
current transaction. New data should be sent during the low
SCL state. This protocol permits a single data line to transfer
both command/control information and data using the synchronous serial clock.
30008550
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying an acknowledge. A
receiver which has been addressed must generate an acknowledge after each byte has been received.
After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LP39542 address
is 54h or 55H as selected with ADDR_SEL pin. I2C address
for LP39542 is 54H when ADDR_SEL=0 and 55H when
ADDR_SEL=1. For the eighth bit, a “0” indicates a WRITE
and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when CLK is LOW.
30008549
I2C Signals: Data Validity
I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
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30008551
I2C Chip Address
32
LP39542
Register changes take an effect at the SCL rising edge during the last ACK from slave.
30008552
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 7-bit chip address, 54H (ADDR_SEL=0) or 55H (ADDR_SEL=1) for LP39542.
I2C Write Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle
waveform.
30008553
I2C Read Cycle
30008554
I2C Timing Diagram
33
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LP39542
I2C Timing Parameters
VDD1,2 = 3.0 to 4.5V, VDD_IO = 1.65V to VDD1,2
Symbol
Parameter
Limit
Min
Units
Max
μs
1
Hold Time (repeated) START Condition
0.6
2
Clock Low Time
1.3
μs
3
Clock High Time
600
ns
4
Setup Time for a Repeated START Condition
600
5
Data Hold Time (Output direction, delay generated by LP39542)
300
900
ns
5
Data Hold Time (Input direction, delay generated by the Master)
0
900
ns
6
Data Setup Time
7
Rise Time of SDA and SCL
20+0.1Cb
300
ns
8
Fall Time of SDA and SCL
15+0.1Cb
300
ns
ns
100
ns
9
Set-up Time for STOP condition
600
ns
10
Bus Free Time between a STOP and a START Condition
1.3
μs
Cb
Capacitive Load for Each Bus Line
10
200
pF
NOTE: Data guaranteed by design
Autoincrement mode is available, with this mode it is possible to read or write bytes with autoincreasing addresses. LP39542 has
empty spaces in address register map, and it is recommended to use autoincrement mode only for writing in pattern command
registers.
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34
than the peak inductor current (ca. 1A). Average current rating
of the schottky diode should be higher than maximum output
current (400 mA). Schottky diodes with a low forward drop
and fast switching speeds are ideal for increasing efficiency
in portable applications. Choose a reverse breakdown of the
schottky diode larger than the output voltage. Do not use ordinary rectifier diodes, since slow switching speeds and long
recovery times cause the efficiency and the load regulation to
suffer.
OUTPUT CAPACITOR, COUT
The output capacitor COUT directly affects the magnitude of
the output ripple voltage. In general, the higher the value of
COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR are the best choice. At the
lighter loads, the low ESR ceramics offer a much lower Vout
ripple that the higher ESR tantalums of the same value. At the
higher loads, the ceramics offer a slightly lower Vout ripple
magnitude than the tantalums of the same value. However,
the dv/dt of the Vout ripple with the ceramics is much lower
than the tantalums under all load conditions. Capacitor voltage rating must be sufficient, 10V or greater is recommended.
Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction with the
increased applied DC voltage, so called DC bias effect.
The capacitance value can fall to below half of the nominal capacitance. Too low output capacitance will increase noise and it can make the boost converter
unstable. Recommended maximum DC bias effect at 5V
DC voltage is -50%.
INDUCTOR, L1
The LP39542’s high switching frequency enables the use of
the small surface mount inductor. A 4.7 μH shielded inductor
is suggested for 2 MHz operation, 10 μH should be used at 1
MHz. The inductor should have a saturation current rating
higher than the peak current it will experience during circuit
operation (ca. 1A). Less than 300 mΩ ESR is suggested for
high efficiency. Open core inductors cause flux linkage with
circuit components and interfere with the normal operation of
the circuit. This should be avoided. For high efficiency,
choose an inductor with a high frequency core material such
as ferrite to reduce the core losses. To minimize radiated
noise, use a toroid, pot core or shielded core inductor. The
inductor should be connected to the SW pin as close to the
IC as possible. Examples of suitable inductors are: TDK
VLF4012AT-4R7M1R1 and Panasonic ELLVEG4R7N.
INPUT CAPACITOR, CIN
The input capacitor CIN directly affects the magnitude of the
input ripple voltage and to a lesser degree the VOUT ripple. A
higher value CIN will give a lower VIN ripple. Capacitor voltage
rating must be sufficient, 10V or greater is recommended.
OUTPUT DIODE, D1
A schottky diode should be used for the output diode. Peak
repetitive current rating of the schottky diode should be larger
LIST OF RECOMMENDED EXTERNAL COMPONENTS
Symbol
Value
Unit
CVDD1
Symbol explanation
C between VDD1 and GND
100
nF
Ceramic, X7R / X5R
Type
CVDD2
C between VDD2 and GND
100
nF
Ceramic, X7R / X5R
CVDDIO
C between VDDIO and GND
100
nF
Ceramic, X7R / X5R
CVDDA
C between VDDA and GND
1
μF
Ceramic, X7R / X5R
COUT
C between FB and GND
10
μF
Ceramic, X7R / X5R, 10V
CIN
C between battery voltage and GND
10
μF
Ceramic, X7R / X5R
L1
L between SW and VBAT at 2 MHz
4.7
μH
Shielded, low ESR, Isat 1A
CVREF
C between VREF and GND
100
nF
Ceramic, X7R
CVDDIO
C between VDDIO and GND
100
nF
Ceramic, X7R
RFLASH
R between IFLASH and GND
1.2
kΩ
±1%
RRBG
R between IRGB and GND
5.6
kΩ
±1%
RRT
R between IRT and GND
82
kΩ
±1%
D1
Rectifying Diode (Vf @ maxload)
0.3
V
Schottky diode
CASE
C between Audio input and ASE
100
nF
Ceramic, X7R / X5R
LEDs
DLIGHT
User defined
Light Sensor
TDK BSC2015
35
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LP39542
Recommended External Components
LP39542
Application Examples
EXAMPLE 1
30008555
—
—
—
—
—
MAIN BACKLIGHT
SUB BACKLIGHT
AUDIO SYNCHRONIZED FUNLIGHTS
RGB INDICATION LIGHT
FLASH LED
FLIP PHONE
www.national.com
36
LP39542
EXAMPLE 2
30008556
—
—
—
—
—
6 WHITE LED BACKLIGHT
KEYPAD LIGHTS
RGB INDICATION LED
WHITE SINGLE LED FLASH
TEMPERATURE SENSOR
SMART PHONE
37
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LP39542
EXAMPLE 3
30008557
—
—
—
—
MAIN BACKLIGHT
KEYPAD LIGHTS
AUDIO SYNCHRONIZED FUNLIGHTS
VIBRA
CANDYBAR PHONE
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38
LP39542
EXAMPLE 4
30008565
—
—
—
—
MAIN BACKLIGHT
SUB BACKLIGHT
AUDIO SYNCHRONIZED FUNLIGHTS
RGB INDICATION LIGHT
There may be cases where the audio input signal going into the LP39542 is too weak for audio synchronization. This figure presents a single-supply inverting
amplifier connected to the ASE input for audio signal amplification. The amplification is +20 dB, which is well enough for 20 mVp-p audio signal. Because the
amplifier (LMV321) is operating in single supply voltage, a voltage divider using R3 and R4 is implemented to bias the amplifier so the input signal is within the
input common-mode voltage range of the amplifier. The capacitor C1 is placed between the inverting input and resistor R1 to block the DC signal going into the
audio signal source. The values of R1 and C1 affect the cutoff frequency, fc = 1/(2π*R1*C1), in this case it is around 160 Hz. As a result, the LMV321 output
signal is centered around mid-supply, that is VDDA/2. The output can swing to both rails, maximizing the signal-to-noise ratio in a low voltage system
USING EXTRA AMPLIFIER
39
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LP39542
EXAMPLE 5
30008569
—
—
—
—
MAIN BACKLIGHT
SUB BACKLIGHT
AUDIO SYNCHRONIZED FUNLIGHTS
RGB INDICATION LIGHT
Here, a second order RC-filter is used on the ASE input to convert a PWM signal to an analog waveform.
USING PWM SIGNAL
More application information is available in the document "LP39542 Evaluation Kit".
www.national.com
40
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ADC output
Boost output
0C
0D
Boost_frq
Enables
0B
0E
WLED5-6
B1 cycle
06
0A
B1 blink
05
WLED1-4
G1 cycle
04
09
G1 blink
03
WLED control
R1 cycle
02
08
R1 blink
01
Ext. PWM control
RGB Ctrl
00
07
REGISTER
ADDR
(HEX)
0
0
0
0
0
0
0
nstby
pwm_
sync
0
0
0
1
0
0
en_
boost
0
0
0
0
0
0
0
slope_w1_4
0
0
r1_pwm
0
b1_on[1]
0
g1_on[1]
0
r1_on[1]
0
r1sw
D5
slope_w5_6
wled5_6
_pwm
0
0
wled1_4
_pwm
b1_on[2]
b1_on[3]
0
r1_on[2]
r1_on[3]
0
1
1
g1_on[2]
cc_rgb2
cc_rgb1
g1_on[3]
D6
D7
LP39542 Control Register Names and Default Values
1
0
0
0
0
0
b1sw
D3
0
0
0
0
0
0
0
boost[7:0]
data[7:0]
wled5_6[7:0]
1
0
0
0
0
en_fade_w1_4
1
1
0
1
en_
autoload
0
0
0
displ
0
r2_pwm
b1_cycle[2]
b1_cycle en
b1_pwm
0
0
b1_off[2]
g1_cycle[2]
g1_cycle en
b1_off[3]
0
0
g1_off[2]
r1_cycle[2]
r1_cycle en
g1_off[3]
0
r1_off[2]
0
r2sw
D2
0
r1_off[3]
wled1_4[7:0]
en_fade_w5_6
0
g1_pwm
0
b1_on[0]
0
g1_on[0]
0
r1_on[0]
0
g1sw
D4
1
D0
1
1
0
0
0
0
0
en_w5_6
0
b2_pwm
0
b1_cycle[0]
0
b1_off[0]
0
g1_cycle[0]
0
g1_off[0]
0
r1_cycle[0]
0
r1_off[0]
0
b2sw
rgb_sel[1:0]
freq_sel[2:0]
1
0
0
0
0
0
en_w1_4
0
g2_pwm
0
b1_cycle[1]
0
b1_off[1]
0
g1_cycle[1]
0
g1_off[1]
0
r1_cycle[1]
0
r1_off[1]
0
g2sw
D1
LP39542
41
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42
REGISTER
HC_Flash
Pattern gen ctrl
RGB1 max current
RGB2 max current
Audio sync CTRL1
Audio sync CTRL2
Command 1A
Command 1B
Command 2A
Command 2B
Command 3A
Command 3B
Command 4A
Command 4B
Command 5A
Command 5B
ADDR
(HEX)
10
11
12
13
2A
2B
50
51
52
53
54
55
56
57
58
59
0
0
0
0
0
0
0
0
0
0
0
D7
0
0
cet[1:0]
cet[1:0]
cet[1:0]
cet[1:0]
cet[1:0]
0
0
r[2:0]
0
0
r[2:0]
0
0
r[2:0]
0
0
r[2:0]
0
0
r[2:0]
0
gain_sel[2:0]
hc_pwm
en_safety
0
0
0
0
0
0
0
0
0
0
0
0
0
D5
D6
0
0
0
b[2:0]
0
0
b[2:0]
0
0
b[2:0]
0
0
b[2:0]
0
0
b[2:0]
0
0
en_avg
0
sync_mode
ir2[1:0]
ir1[1:0]
0
D4
fl_t[1:0]
0
0
g[2:0]
0
0
g[2:0]
0
0
g[2:0]
0
0
g[2:0]
0
0
g[2:0]
0
0
ig2[1:0]
ig1[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
en_sync
0
0
tt[2:0]
0
0
tt[2:0]
0
0
tt[2:0]
0
0
cet[3:2]
cet[3:2]
cet[3:2]
cet[3:2]
cet[3:2]
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
log
speed_ctrl[1:0]
tt[2:0]
0
0
ib2[1:0]
ib1[1:0]
D0
en_
hcflash
input_sel[1:0]
tt[2:0]
0
0
1
0
0
0
0
0
0
loop
hc[1:0]
D1
0
D2
rgb_start
mode_ctrl[1:0]
en_agc
0
0
0
D3
LP39542
REGISTER
Command 6A
Command 6B
Command 7A
Command 7B
Command 8A
Command 8B
Reset
ADDR
(HEX)
5A
5B
5C
5D
5E
5F
60
0
0
0
0
0
0
D7
cet[1:0]
cet[1:0]
cet[1:0]
0
0
r[2:0]
0
0
r[2:0]
0
0
r[2:0]
D6
0
0
0
0
0
0
D5
0
0
g[2:0]
0
0
g[2:0]
0
0
g[2:0]
D3
Writing any data to Reset Register resets LP39542
0
b[2:0]
0
0
b[2:0]
0
0
b[2:0]
0
D4
0
0
0
0
0
0
D2
0
tt[2:0]
0
0
tt[2:0]
0
0
tt[2:0]
0
D1
cet[3:2]
cet[3:2]
cet[3:2]
0
0
0
0
0
0
D0
LP39542
43
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LP39542
LP39542 Registers
REGISTER BIT EXPLANATIONS
Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition:
Register Bit Accessibility and Initial Condition
Key
Bit Accessibility
rw
r
–0,–1
Read/write
Read only
Condition after POR
RGB CTRL (00H) – RGB LEDS CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
cc_rgb1
cc_rgb2
r1sw
g1sw
b1sw
r2sw
g2sw
b2sw
rw-1
rw-1
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
cc_rgb1
Bit 7
0 - R1, G1 and B1 are constant current sinks, current limited internally
1 - R1, G1 and B1 are switches, limit current with external ballast resistor
cc_rgb2
Bit 6
0 – R2, G2 and B2 are constant current sinks, current limited internally
1 – R2, G2 and B2 are switches, limit current with external ballast resistor
r1sw
Bit 5
0 – R1 disabled
1 – R1 enabled
g1sw
Bit 4
0 – G1 disabled
1 – G1 enabled
b1sw
Bit 3 0 – B1 disabled
1 – B1 enabled
r2sw
Bit 2
0 – R2 disabled
1 – R2 enabled
g2sw
Bit 1
0 – G2 disabled
1 – G2 enabled
b2sw
Bit 0
0 – B2 disabled
1 – B2 enabled
R1/G1/B1 BLINK (01H, 03H, 05H) – BLINKING ON/OFF TIME CONTROL REGISTER
D7
D6
rw-0
rw-0
D5
D4
D3
rw-0
rw-0
R1/G1/B1_ON[3:0]
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rw-0
D2
D1
D0
R1/G1/B1_OFF[3:0]
44
rw-0
rw-0
rw-0
LP39542
RGB1 ON and OFF time
R1_ON[3:0],
R1_OFF[3:0]
G1_ON[3:0],
G1_OFF[3:0]
B1_ON[3:0],
B1_OFF[3:0]
Bits 7-4, 3-0
Bits
ON/OFF time
0000
0%
0001
1%
0010
2.5%
0011
5%
0100
7.5%
0101
10%
0110
15%
0111
20%
1000
30%
1001
40%
1010
50%
1011
60%
1100
70%
1101
80%
1110
90%
1111
100%
R1/G1/B1 CYCLE(02H, 04H, 06H) – BLINKING CYCLE CONTROL REGISTER
D7
D6
D5
D4
D3
D2
R1/G1/
B1_CYCLE_EN
r-0
r-0
r-0
R1_CYCLE_EN
G1_CYCLE_EN
B1_CYCLE_EN
Bit 3
R1_CYCLE[2:0]
G1_CYCLE[2:0]
B1_CYCLE[2:0]
Bits 2-0
r-0
D1
D0
R1/G1/B1_CYCLE[2:0]
rw-0
rw-0
rw-0
rw-0
Blinking enable
0 = disabled, output state is defined with RGB registers
1 = enabled, output state is defined with blinking cycle
RGB1 cycle time
Bits
Blinking cycle time
Blinking frequency
000
0.1s
10 Hz
001
0.25s
4 Hz
010
0.5s
2 Hz
011
1s
1 Hz
100
2s
0.5 Hz
101
3s
0.33 Hz
110
4s
0.25 Hz
111
5s
0.2 Hz
45
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LP39542
EXT_PWM_CONTROL (07H) – EXTERNAL PWM CONTROL REGISTER
D7
D6
wled1_4_pwm wled5_6_pwm
rw-0
D5
D4
D3
D2
D1
D0
r1_pwm
g1_pwm
b1_pwm
r2_pwm
g2_pwm
b2_pwm
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
D2
D1
D0
displ
en_w1_4
en_w5_6
rw-0
rw-0
rw-0
rw-0
wled1_4_pwm
Bit 7
0 – WLED1…WLED4 PWM control disabled
1 – WLED1…WLED4 PWM control enabled
wled5_6_pwm
Bit 6
0 – WLED5, WLED6 PWM control disabled
1 – WLED5, WLED6 PWM control enabled
r1_pwm
Bit 5
0 – R1 PWM control disabled
1 – R1 PWM control enabled
g1_pwm
Bit 4
0 – G1 PWM control disabled
1 – G1 PWM control enabled
b1_pwm
Bit 3
0 – RB PWM control disabled
1 – B1 PWM control enabled
r2_pwm
Bit 2
0 – R2 PWM control disabled
1 – R2 PWM control enabled
g2_pwm
Bit 1
0 – G2 PWM control disabled
1 – G2 PWM control enabled
b2_pwm
Bit 0
0 – B2 PWM control disabled
1 – B2 PWM control enabled
WLED CONTROL (08H) – WLED CONTROL REGISTER
D7
r-0
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D6
D5
D4
slope_w5_6
slope_w1_4
rw-0
rw-0
D3
en_fade_w5_6 en_fade_w1_4
rw-0
rw-0
slope_w5_6
Bit 6
0 – WLED5-6 full range fade execution time 1.3s
1 – WLED5-6 full range fade execution time 0.65s
slope_w1_4
Bit 5
0 – WLED1-4 full range fade execution time 1.3s
1 – WLED1-4 full range fade execution time 0.65s
en_fade_w5_6
Bit 4
0 – disable fade for WLED5-6
1 – enable fade for WLED5-6
en_fade_w1_4
Bit 3
0 – disable fade for WLED1-4
1 – enable fade for WLED1-4
displ
Bit 2
0 – WLED1-4 and WLED5-6 are controlled separately
1 – WLED1-4 and WLED5-6 are controlled with WLED1-4 controls
en_w1_4
Bit 1
0 – WLED1-4 disabled
1 – WLED1-4 enabled
en_w5_6
Bit 0
0 – WLED5-6 disabled
1 – WLED5-6 enabled
46
D7
D6
D5
D4
D3
D2
D1
D0
rw-0
rw-0
rw-0
D2
D1
D0
rw-0
rw-0
rw-0
wled1_4[7:0]
rw-0
rw-0
rw-0
rw-0
rw-0
Adjustment
wled1_4[7:0]
wled1_4[7:0]
Bits 7-0
Typical driver current (mA)
0000 0000
0
0000 0001
0.1
0000 0010
0.2
0000 0011
0.3
0000 0100
0.4
…
…
1111 1101
25.3
1111 1110
25.4
1111 1111
25.5
WLED5-6 (0AH) – WLED5, WLED6 BRIGHTNESS CONTROL REGISTER
D7
D6
D5
D4
D3
wled5_6[7:0]
rw-0
rw-0
rw-0
rw-0
rw-0
Adjustment
wled5_6[7:0]
wled5_6[7:0]
Bits 7-0
Typical driver current (mA)
0000 0000
0
0000 0001
0.1
0000 0010
0.2
0000 0011
0.3
0000 0100
0.4
…
…
1111 1101
25.3
1111 1110
25.4
1111 1111
25.5
47
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LP39542
WLED1-4 (09H) – WLED1…WLED4 BRIGHTNESS CONTROL REGISTER
LP39542
ENABLES (0BH) – ENABLES REGISTER
D7
D6
D5
pwm_sync
nstby
en_boost
D4
rw-0
rw-0
rw-0
D3
D2
D1
en_autoload
r-0
r-0
rw-1
pwm_sync
Bit 7
0 – synchronization to external clock disabled
1 – synchronization to external clock enabled
nstby
Bit 6
0 – LP39542 standby mode
1 – LP39542 active mode
en_boost
Bit 5
0 – boost converter disabled
1 – boost converter enabled
en_autoload
Bit 2
0 – internal boost converter loader off
1 – internal boost converter loader on
D0
rgb_sel[1:0]
rw-0
rw-0
Color LED control mode selection
rgb_sel[1:0]
Audio sync
Pattern generator
Blinking sequence
00
-
RGB1 & RGB2
-
01
-
RGB2
RGB1
10
RGB2
RGB1
-
11
RGB1 & RGB2
-
-
Bits 1-0
rgb_sel[1:0]
ADC_OUTPUT (0CH) – ADC DATA REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
r-0
r-0
r-0
r-0
data[7:0]
r-0
r-0
data[7:0]
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r-0
Bits 7-0
r-0
Data register ADC (Audio input, light or temperature sensors)
48
D7
D6
D5
D4
D3
D2
D1
D0
rw-1
rw-1
rw-1
rw-1
D1
D0
Boost[7:0]
rw-0
rw-0
rw-1
rw-1
Adjustment
Bits 7-0
Boost[7:0]
Boost[7:0]
Typical boost output (V)
0000 0000
4.00
0000 0001
4.25
0000 0011
4.40
0000 0111
4.55
0000 1111
4.70
0001 1111
4.85
0011 1111
5.00 (default)
0111 1111
5.15
1111 1111
5.30
BOOST_FRQ (0EH) – BOOST FREQUENCY CONTROL REGISTER
D7
D6
D5
D4
D3
D2
r-0
r-0
r-0
r-0
r-0
rw-1
freq_sel[2:0]
rw-1
rw-1
Adjustment
freq_sel[2:0]
freq_sel[2:0]
Frequency
1xx
2.00 MHz
01x
1.67 MHz
00x
1.00 MHz
Bits 7-0
49
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LP39542
BOOST_OUTPUT (0DH) – BOOST OUTPUT VOLTAGE CONTROL REGISTER
LP39542
HC_FLASH (10H) – HIGH CURRENT FLASH DRIVER CONTROL REGISTER
D7
r-0
D6
D5
en_safety
hc_pwm
D4
rw-0
rw-0
D3
D2
fl_t[1:0]
rw-0
D1
hc[1:0]
rw-0
rw-0
en_safety
Bit 6
0 - flash timeout feature disabled
1 - flash timeout feature enabled
hc_pwm
Bit 5
0 – ext. PWM for high current flash driver disabled
1 – ext. PWM for high current flash driver enabled
D0
en_hcflash
rw-0
rw-0
Flash duration for high current driver
fl_t[1:0]
Bits 4-3
fl_t[1:0]
Typical flash duration
00
200 ms
01
400 ms
10
600 ms
11
EN_FLASH pin on duration
Current control for high current flash driver
hc[1:0]
Bits 2-1
Bit 0
en_hcflash
hc[1:0]
current
00
0.25×IMAX(FLASH)
01
0.50×IMAX(FLASH)
10
0.75×IMAX(FLASH)
11
1.00×IMAX(FLASH)
0 – high current flash driver disabled
1 – high current flash driver enabled
PATTERN_GEN_CTRL (11H) – PATTERN GENERATOR CONTROL REGISTER
D7
r-0
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D6
r-0
D5
r-0
D4
D3
D2
D1
D0
en_blink
rgb_start
loop
log
rw-0
rw-0
rw-0
rw-0
r-0
en_blink
Bit 3
0 - blinking sequences start bit disabled
1 - blinking sequences start bit enabled
rgb_start
Bit 2
0 – pattern generator disabled
1 – execution pattern starting from command 1
loop
Bit 1
0 – pattern generator loop disabled (single pattern)
1 – pattern generator loop enabled (execute until stopped)
log
Bit 0
0 – color intensity mode 0
1 – color intensity mode 1
50
D7
D6
D5
D4
D3
ir1[1:0]
r-0
r-0
rw-0
D2
D1
ig1[1:0]
rw-0
rw-0
D0
ib1[1:0]
rw-0
rw-0
rw-0
Maximum current for R1 driver
ir1[1:0]
Bits 5-4
ir1[2:0]
Maximum output current
00
0.25×IMAX
01
0.50×IMAX
10
0.75×IMAX
11
1.00×IMAX
Maximum current for G1 driver
ig1[1:0]
Bits 3-2
ig2[1:0]
Maximum output current
00
0.25×IMAX
01
0.50×IMAX
10
0.75×IMAX
11
1.00×IMAX
Maximum current for B1 driver
ib1[1:0]
Bits 1-0
ib1[1:0]
Maximum output current
00
0.25×IMAX
01
0.50×IMAX
10
0.75×IMAX
11
1.00×IMAX
51
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LP39542
RGB1_MAX_CURRENT (12H) – RGB1 DRIVER INDIVIDUAL MAXIMUM CURRENT CONTROL REGISTER
LP39542
RGB2_MAX_CURRENT (13H) – RGB2 DRIVER INDIVIDUAL MAXIMUM CURRENT CONTROL REGISTER
D7
D6
D5
D4
D3
ir2[1:0]
r-0
r-0
rw-0
D2
rw-0
rw-0
Bits 5-4
rw-0
ir2[2:0]
Maximum output current
00
0.25×IMAX
01
0.50×IMAX
10
0.75×IMAX
11
1.00×IMAX
Maximum current for G2 driver
ig2[1:0]
Bits 3-2
ig2[1:0]
Maximum output current
00
0.25×IMAX
01
0.50×IMAX
10
0.75×IMAX
11
1.00×IMAX
Maximum current for B2 driver
ib2[1:0]
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Bits 1-0
ib2[1:0]
Maximum output current
00
0.25×IMAX
01
0.50×IMAX
10
0.75×IMAX
11
1.00×IMAX
52
D0
ib2[1:0]
Maximum current for R2 driver
ir2[1:0]
D1
ig2[1:0]
rw-0
rw-0
D7
D6
D5
gain_sel[2:0]
rw-0
rw-0
D4
D3
D2
sync_mode
en_agc
en_sync
rw-0
rw-0
rw-0
rw-0
D1
D0
input_sel[1:0]
rw-1
rw-1
Input signal gain control
gain_sel[2:0]
gain, dB
000
0 (default)
001
3
010
6
Bits 7-5
gain_sel[2:0]
011
9
100
12
101
15
110
18
111
21
sync_mode
Bit 4
Input filter mode control
0 – Amplitude mode
1 – Frequency mode
en_agc
Bit 3
0 – automatic gain control disabled
1 – automatic gain control enabled
en_sync
Bit 2
0 – audio synchronization disabled
1 – audio synchronization enabled
ADC input selector
input_sel[1:0]
Input
00
Single ended input signal (ASE)
Bits 1-0
input_sel[1:0]
01
Temperature measurement
10
Ambient light measurement
11
No input (default)
AUDIO_SYNC_CTRL2 (2BH) – AUDIO SYNCHRONIZATION AND ADC CONTROL REGISTER 2
D7
D6
D5
r-0
r-0
r-0
D4
D3
en_avg
mode_ctrl[1:0]
rw-0
en_avg
Bit 4
mode_ctrl[1:0]
Bits 3-2
D2
rw-0
D1
D0
speed_ctrl[1:0]
rw-0
rw-0
rw-0
0 – averaging disabled. fsample = 122 Hz, data in
register changes every 8.2 ms.
1 – averaging enabled. fsample = 244 Hz, averaging of
64 samples, data in register changes every 262 ms
(3.2Hz).
Filtering mode control
LEDs light response time to audio input
speed_ctrl[1:0]
Bits 1-0
speed_ctrl[1:0]
Response
00
FASTEST (default)
01
FAST
10
MEDIUM
11
SLOW
53
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LP39542
AUDIO_SYNC_CTRL1 (2AH) – AUDIO SYNCHRONIZATION AND ADC CONTROL REGISTER 1
LP39542
PATTERN CONTROL REGISTERS
Command_[1:8]A – Pattern Control Register A
D7
D6
D5
D4
rw-0
D3
r[2:0]
D2
D1
rw-0
rw-0
rw-0
D1
D0
g[2:0]
rw-0
rw-0
rw-0
D7
D6
D5
rw-0
rw-0
rw-0
D0
cet[3:2]
Command_[1:8]B – Pattern Control Register B
D4
cet[1:0]
rw-0
D3
D2
rw-0
rw-0
b[2:0]
tt[2:0]
rw-0
rw-0
Red color intensity
r[2:0]
current, %
log=0
r[2:0]
Bits
7-5A
log=1
000
0×IMAX
0×IMAX
001
7%×IMAX
1%×IMAX
010
14%×IMAX
2%×IMAX
011
21%×IMAX
4%×IMAX
100
32%×IMAX
10%×IMAX
101
46%×IMAX
21%×IMAX
110
71%×IMAX
46%×IMAX
111
100%×IMAX
100%×IMAX
Green color intensity
g[2:0]
current, %
log=0
log=1
0×IMAX
0×IMAX
001
7%×IMAX
1%×IMAX
010
14%×IMAX
2%×IMAX
011
21%×IMAX
4%×IMAX
100
32%×IMAX
10%×IMAX
101
46%×IMAX
21%×IMAX
110
71%×IMAX
46%×IMAX
111
100%×IMAX
100%×IMAX
000
g[2:0]
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Bits
4-2A
54
rw-0
LP39542
Command execution time
cet[3:0]
Bits
1-0A
7-6B
cet[3:0]
CET duration, ms
0000
197
0001
393
0010
590
0011
786
0100
983
0101
1180
0110
1376
0111
1573
1000
1769
1001
1966
1010
2163
1011
2359
1100
2556
1101
2753
1110
2949
3146
1111
Blue color intensity
b[2:0]
current, %
log=0
log=1
0×IMAX
0×IMAX
001
7%×IMAX
1%×IMAX
010
14%×IMAX
2%×IMAX
011
21%×IMAX
4%×IMAX
100
32%×IMAX
10%×IMAX
101
46%×IMAX
21%×IMAX
110
71%×IMAX
46%×IMAX
100%×IMAX
100%×IMAX
000
b[2:0]
Bits
5-3B
111
Transition time
tt[2:0]
tt[2:0]
Bits
2-0B
Transition time, ms
000
0
001
55
010
110
011
221
100
442
101
885
110
1770
111
3539
RESET (60H) - RESET REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
w-0
w-0
Writing any data to Reset Register in address 60H can reset LP39542
w-0
w-0
w-0
w-0
w-0
55
w-0
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LP39542
Physical Dimensions inches (millimeters) unless otherwise noted
The dimension for X1 ,X2 and X3 are as given:
— X1=3.00 mm ±0.03 mm
— X2=3.00 mm ±0.03 mm
— X3=0.60 mm ±0.075 mm
36-bump micro SMD Package, 3 x 3 x 0.6 mm, 0.5 mm pitch
NS Package Number TLA36AAA
www.national.com
56
LP39542
The dimension for X1 ,X2 and X3 are as given:
— X1=3.00 mm ±0.03 mm
— X2=3.00 mm ±0.03 mm
— X3=0.65 mm ±0.075 mm
36-bump micro SMDxt Package, 3 x 3 x 0.65 mm, 0.5 mm pitch
NS Package Number RLA36AAA
See Application notes AN–1112 and AN–1412 for PCB design and assembly instructions.
57
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LP39542 Advanced Lighting Management Unit
Notes
THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION
(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,
IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT.
TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT
NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL
PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR
APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND
APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE
NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.
EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO
LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY
RIGHT.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other
brand or product names may be trademarks or registered trademarks of their respective holders.
Copyright© 2007 National Semiconductor Corporation
For the most current product information visit us at www.national.com
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