LP61L256C Preliminary 32K X 8 BIT HIGH SPEED CMOS SRAM Document Title 32K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue November 9, 2001 Preliminary (November, 2001, Version 0.0) AMIC Technology, Inc. LP61L256C Preliminary 32K X 8 BIT HIGH SPEED CMOS SRAM Features n Single +3.3V power supply n Access times: 12/15 ns (max.) n Current: Operating: 120mA (max.) Standby: 5mA (max.) n Full static operation, no clock or refreshing required n n n n All inputs and outputs are directly TTL compatible Common I/O using three-state output Data retention voltage: 2V (min.) Available in 28-pin SOJ package General Description Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2V. The LP61L256C is a high-speed, low-power 262,144-bit static random access memory organized as 32,768 words by 8 bits and operates on a single 3.3V power supply. It is built using high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Pin Configurations n SOJ 1 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 (November, 2001, Version 0.0) LP61L256C PRELIMINARY A14 1 AMIC Technology, Inc. LP61L256C Series Block Diagram A0 VCC A5 GND A6 A7 ROW 256 X 1024 DECODER MEMORY ARRAY A9 A10 A11 A12 I/O0 COLUMN I/O INPUT DATA CIRCUIT COLUMN DECODER I/O7 A1 A2 A3 A4 A8 A13 A14 CE OE CONTROL CIRCUIT WE Pin Descriptions - SOJ PRELIMINARY Pin No. Symbol 1 - 10, 21, 23 - 26 A0 - A14 Address Inputs 11 - 13, 15 - 19 I/O0 - I/O7 Data Inputs/Outputs 14 GND Ground 28 VCC Power Supply 20 CE Chip Enable 22 OE Output Enable 27 WE Write Enable (November, 2001, Version 0.0) 2 Description AMIC Technology, Inc. LP61L256C Series Recommended DC Operating Conditions (TA = 0°C to + 70°C) Symbol Parameter VCC Supply Voltage GND Ground Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 V VIH Input High Voltage 2.2 - VCC + 0.3 V VIL Input Low (1) Voltage -0.5 0 +0.8 V CL Output Load - - 30 pF Absolute Maximum Ratings* *Comments VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC +0.5V Operating Temperature, Topr . . . . . . . . . . . 0°C to +70°C Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C Temperature Under Bias, Tbias . . . . . . . . -10°C to +85°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 1.0W Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol (TA = 0°C to + 70°C, VCC = 3.3V ± 10%, GND = 0V) Parameter LP61L256C-12/15 Min. Max. Unit Conditions ILI Input Leakage - 2 µA VIN = GND to VCC ILO Output Leakage - 2 µA CE = VIH or OE = VIH VI/O = GND to VCC Dynamic Operating Current - 120 mA CE = VIL, II/O = 0 mA Min. Cycle, Duty = 100% - 30 mA CE = VIH CE ≥ VCC - 0.2V VIN ≥ VCC -0.2V or VIN ≤ 0.2V ICC1 (2) ISB ISB1 Standby Power Supply Current - 5 mA VOL Output Low Voltage - 0.4 V IOL = 8 mA VOH Output High Voltage 2.4 - V IOH = -4 mA Notes: 1. VIL = -3.0V for pulses less than 20 ns. 2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns. PRELIMINARY (November, 2001, Version 0.0) 3 AMIC Technology, Inc. LP61L256C Series Truth Table Mode I/O Operation Supply Current CE OE WE Standby H X X High Z ISB, ISB1 Output Disable L H H High Z ICC1 Read L L H DOUT ICC1 Write L X L DIN ICC1 Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 10 pF VIN = 0V CI/O* Input/Output Capacitance 10 pF VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V ± 10%) Symbol LP61L256C-12 Parameter LP61L256C-15 Unit Min. Max. Min. Max. 12 - 15 - ns Read Cycle tRC Read Cycle Time tAA Address Access Time - 12 - 15 ns tACE Chip Enable Access Time - 12 - 15 ns tOE Output Enable to Output Valid - 6 - 8 ns tCLZ Chip Enable to Output in Low Z 3 - 3 - ns tOLZ Output Enable to Output in Low Z 0 - 0 - ns tCHZ Chip Disable Output in High Z 0 6 - 8 ns tOHZ Output Disable to Output in High Z 0 6 0 8 ns tOH Output Hold from Address Change 3 - 3 - ns PRELIMINARY (November, 2001, Version 0.0) 4 AMIC Technology, Inc. LP61L256C Series AC Characteristics (continued) Symbol LP61L256C-12 Parameter Min. Max. LP61L256C-15 Min. Max Unit Write Cycle tWC Write Cycle Time 12 - 15 - ns tCW Chip Enable to End of Write 10 - 12 - ns tAS Address Setup Time of Write 0 - 0 - ns tAW Address Valid to End of Write 10 - 12 - ns tWP Write Pulse Width 10 - 12 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z 0 6 0 8 ns tDW Data to Write Time Overlap 6 - 7 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 3 - 3 - ns Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levles. Timing Waveforms (1) Read Cycle 1 tRC Address tAA OE tOE tOH tOLZ5 CE tOHZ5 tCHZ5 tACE tCLZ5 DOUT PRELIMINARY (November, 2001, Version 0.0) 5 AMIC Technology, Inc. LP61L256C Series Timing Waveforms (continued) (1, 2, 4) Read Cycle 2 tRC Address tAA tOH tOH DOUT (1, 3, 4,) Read Cycle 3 CE tACE tCLZ 5 tCHZ 5 DOUT Notes: 1. 2. 3. 4. 5. WE is high for Read Cycle. Device is continuously enabled, CE = VIL. Address valid prior to or coincident with CE transition low. OE = VIL. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (November, 2001, Version 0.0) 6 AMIC Technology, Inc. LP61L256C Series Timing Waveforms (continued) (6) Write Cycle 1 (Write Enable Controlled) tWC Address tAW tWR 3 tCW5 CE (4) tAS1 tWP 2 WE tDW tDH DIN tWHZ7 tOW 7 DOUT Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 CE tWR 3 tCW5 (4) tWP 2 WE tDW tDH DIN tWHZ7 DOUT Notes: 1. 2. 3. 4. tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low CE and a low WE . tWR is measured from the earliest of CE or WE going high to the end of the Write cycle If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (November, 2001, Version 0.0) 7 AMIC Technology, Inc. LP61L256C Series AC Test Conditions Input Pulse Levels 0V to 3.0V Input Rise and Fall Time 2 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 +3.3V 317Ω I/O OUTPUT RL=50Ω ZO=50Ω 351Ω 5pF* VT=1.5V * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW Data Retention Characteristics (TA = 0°C to 70°C) Symbol VDR Parameter VCC for Data Retention Min. Max. Unit 2 3.6 V ICCDR Data Retention Current - 2 mA tCDR Chip Disable to Data Retention Time 0 - ns tR Operation Recovery Time Conditions CE ≥ VCC - 0.2V VCC = 2.0V CE ≥ VCC - 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V See Retention Waveform tRC* - ns tRC = Read Cycle Time PRELIMINARY (November, 2001, Version 0.0) 8 AMIC Technology, Inc. LP61L256C Series Low VCC Data Retention Waveform DATA RETENTION MODE VCC 3.0V 3.0V tCDR tR VDR ≥ 2.0V VIH CE VIH CE ≥ VDR - 0.2V Ordering Information Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) LP61L256CS-12 12 120 5 28L SOJ LP61L256CS-15 15 120 5 28L SOJ PRELIMINARY (November, 2001, Version 0.0) 9 Package AMIC Technology, Inc. LP61L256C Series Package Information SOJ 28L Outline Dimensions 15 1 14 E 28 HE unit: inches/mm L A A2 C D b b1 A1 e D S Seating Plane Symbol e1 y Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A - - 0.140 - - 3.56 A1 0.027 - - 0.69 - - A2 0.095 0.100 0.105 2.41 2.54 2.67 b1 0.028 TYP 0.71 TYP b 0.018 TYP 0.46 TYP C 0.010 TYP 0.25 TYP D - 0.710 0.730 - 18.03 18.54 E 0.295 0.300 0.305 7.49 7.62 7.75 e 0.050 BSC 1.27 BSC e1 0.255 0.265 0.275 6.48 6.73 6.99 HE 0.329 0.337 0.345 8.36 8.56 8.76 L 0.077 0.087 0.097 1.96 2.21 2.46 S - - 0.045 - - 1.14 y - - 0.004 - - 0.10 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. PRELIMINARY (November, 2001, Version 0.0) 10 AMIC Technology, Inc.