LP8545 LP8545 High-Efficiency LED Backlight Driver for Notebooks Literature Number: SNVS635B LP8545 High-Efficiency LED Backlight Driver for Notebooks General Description Features The LP8545 is a white LED driver with integrated boost converter. It has six adjustable current sinks which can be controlled by PWM input or with I2C-compatible serial interface. The boost converter has adaptive output voltage control based on the LED driver voltages. This feature minimizes the power consumption by adjusting the voltage to lowest sufficient level in all conditions. LED outputs have 8-bit current resolution and up to 13-bit PWM resolution with additional 1-3 bit dithering to achieve smooth and precise brightness control. Proprietary Phase Shift PWM control is used for LED outputs to reduce peak current from the boost converter, thus making the boost capacitors smaller. The Phase Shifting scheme also eliminates audible noise. Internal EEPROM is used for storing the configuration data. This makes it possible to have minimum external component count and make the solution very small. LP8545 has safety features which make it possible to detect LED outputs with open or short fault. As well low input voltage and boost over-current conditions are monitored and chip is turned off in case of these events. Thermal de-rating function prevents overheating of the device by reducing backlight brightness when set temperature has been reached. LP8545 is available in National's LLP 24-pin package. ■ High-voltage DC/DC boost converter with integrated FET ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ with four switching frequency options: 156/312/625/1250 kHz Configurable for use with external FET for applications needing higher output voltage 2.7V – 22V input voltage range to support 1x…5x cell LiIon batteries Programmable PWM resolution — 8 to 13 true bit (steady state) — Additional 1 to 3 bits using dithering during brightness changes I2C and PWM brightness control PWM output frequency and LED current set through resistors Optional synchronization to display VSYNC signal 6 LED outputs with LED fault (short/open) detection Low input voltage, over-temperature, over-current detection and shutdown Minimum number of external components LLP 24-pin package, 4 x 4 x 0.8 mm Applications ■ Notebook and Netbook LCD Display LED Backlight ■ LED Lighting Typical Application (1) 30108470 © 2011 National Semiconductor Corporation 301084 www.national.com LP8545 High-Efficiency LED Backlight Driver for Notebooks September 23, 2011 LP8545 Typical Application for Low Input Voltage (2) 30108471 Note: Separate 5V rail to VLDO can be also used to improve efficiency for applications with higher battery voltage. No power sequencing requirements between VIN/VLDO and VBATT. Typical Application for High Output Voltage (3) 30108468 www.national.com 2 LP8545 Connection Diagrams and Package Mark Information 24–pin Leadless Leadframe Package (LLP) 4.0 x 4.0 x 0.8mm, 0.5 mm pitch NS Package Number SQA24A 30108475 30108472 Top View Bottom View Package Mark 30108496 Package Mark - Top View U = Fab Z = Assembly XY = 2–Digit Date Code TT = Die Traceability xxxx = Product Identification Ordering Information Order Number Spec/flow Package Marking Supplied As LP8545SQX NOPB / HFLF L8545SQ 4500 units, Tape-and-Reel 3 www.national.com LP8545 Pin Descriptions Pin # Name 1 GND_SW Type G Description Boost switch ground 2 PWM A PWM dimming input. This pin must be connected to GND if not used. 3 ISET A Set resistor for LED current. This pin can be left floating if not used. 4 EN I Enable input pin 5 FSET A PWM frequency set resistor. This pin can be left floating if not used. 6 GD A Gate driver for external FET. If not used, can be left floating. 7 FAULT OD 8 VDDIO P Digital IO reference voltage (1.65V...5V) for I2C interface. If brightness is controlled with PWM input pin then this pin can be connected to GND. 9 GND_S G Signal ground 10 SCLK I Serial clock. This pin must be connected to GND if not used. 11 SDA I/O Serial data. This pin must be connected to GND if not used. 12 OUT1 A Current sink output 13 OUT2 A Current sink output 14 OUT3 A Current sink output 15 GND_L G LED ground 16 OUT4 A Current sink output 17 OUT5 A Current sink output 18 OUT6 A Current sink output 19 VSYNC I VSYNC input. This pin must be connected to GND if not used. 20 FILTER A Low pass filter for PLL. This pin can be left floating if not used. 21 FB A Boost feedback input 22 VLDO P LDO output voltage. External 5V rail can be connected to this pin in low voltage application. 23 VIN P Input power supply up to 22V. If 2.7V ≤ VBATT < 5.5V (Typical Application for Low Input Voltage (2)) then external 5V rail must be used for VLDO and VIN. 24 SW A Boost switch. With external FET (typ. app. (3)) this pin acts as a current sense. Fault indication output. If not used, can be left floating. A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, I/O: Input/Output Pin, O: Output Pin, OD: Open Drain Pin www.national.com 4 (Note 1, Note 2) Input Voltage Range (VIN) 5.5V to 22.0V typ. app. (1), (3) Input Voltage Range (VIN + VLDO) 4.5V to 5.5V typ. app. (2) VDDIO 1.65V to 5V V(OUT1...OUT6, SW, FB) 0V to 40V Junction Temperature (TJ) Range -30°C to +125°C Ambient Temperature (TA) Range -30°C to +85°C (Note 6) 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN VLDO Voltage on Logic Pins (VSYNC, PWM, EN, SCLK, SDA) Voltage on Logic Pin (FAULT) Voltage on Analog Pins (FILTER, GD, VDDIO, ISET, FSET) V (OUT1...OUT6, SW, FB) Continuous Power Dissipation (Note 3) Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Lead Temperature (Soldering) ESD Rating Human Body Model: Machine Model: Charged Device Model: -0.3V to +24.0V -0.3V to +6.0V -0.3V to +6.0V -0.3V to VDDIO + 0.3V -0.3V to +6.0V Thermal Properties Junction-to-Ambient Thermal Resistance (θJA), SQA Package (Note 7) -0.3V to +44.0V Internally Limited 35 to 50°C/W 125°C -65°C to +150°C (Note 4) (Note 5) 2 kV 200V 1 kV Electrical Characteristics (Note 2, Note 8) Limits in standard typeface are for TA = 25°C. Limits in boldface type apply over the full operating ambient temperature range (-30°C ≤ TA ≤ +85°C). Unless otherwise specified: VIN = 12.0V, CVLDO = 1 μF, L1 = 15 μH, CIN = 10 μF, COUT = 10 μF. RISET = 16 kΩ (Note 9) Symbol Parameter Standby Supply Current IIN Normal Mode Supply Current Condition Min Typ Internal LDO disabled EN=L and PWM=L LDO enabled, boost enabled, no current going through LED outputs, Internal FET used 5 MHz PLL Clock 4.0 10 MHz PLL Clock 4.8 20 MHz PLL Clock 6.0 Max Units 1 μA mA 40 MHz PLL Clock 8.4 fOSC Internal Oscillator Frequency Accuracy -4 -7 VLDO Internal LDO Voltage 4.5 ILDO Internal LDO External Loading 5.0 +4 +7 % 5.5 V 5.0 mA Max Units Boost Converter Electrical Characteristics Symbol Parameter RDSON Switch ON Resistance VMAX Boost Maximum Output Voltage ILOAD Maximum Continuous Load Current, Internal FET ILOAD Maximum Continuous Load Current, External FET Condition ISW = 0.5A Min Typ 0.12 Ω 40 V 9.0V ≤ VBATT, VOUT = 35V 450 6.0V ≤ VBATT, VOUT = 35V 300 3.0V ≤ VBATT, VOUT = 25V 180 9.0V ≤ VBATT, VOUT = 50V 320 6.0V ≤ VBATT, VOUT = 50V 190 5 mA mA www.national.com LP8545 Operating Ratings Absolute Maximum Ratings (Note 1, Note LP8545 Symbol Parameter Condition Min Typ VOUT/VIN Conversion Ratio Max Units 10 fSW Switching Frequency BOOST_FREQ = 00 BOOST_FREQ = 01 BOOST_FREQ = 10 BOOST_FREQ = 11 VOV Over-voltage Protection Voltage VBOOST ≥ 38V VBOOST < 38V tPULSE Switch Pulse Minimum Width no load tSTARTUP Startup Time (Note 10) IMAX SW Pin Current Limit BOOST_IMAX[1:0] = 00 BOOST_IMAX[1:0] = 01 BOOST_IMAX[1:0] = 10 BOOST_IMAX[1:0] = 11 VGD Gate Driver Pin Voltage EN_EXT_FET = 1 156 312 625 1250 kHz VBOOST + 1.6V VBOOST + 4V V 50 ns 6 ms 0.9 1.4 2.0 2.5 A 0 VLDO V LED Driver Electrical Characteristics Symbol Typ Max Units Leakage Current Outputs OUT1...OUT6, VOUT = 40V 0.1 1 µA IMAX Maximum Source Current OUT1...OUT6 EN_I_RES = 0, CURRENT[7:0] = FFh 30 EN_I_RES = 1 50 IOUT Output Current Accuracy (Note 11) Output current set to 23 mA, EN_I_RES = 1 IMATCH Matching (Note 11) Output current set to 23 mA, EN_I_RES = 1 0.5 fLED = 5 kHz, fPLL = 5 MHz 10 fLED = 10 kHz, fPLL = 5 MHz 9 ILEAKAGE PWMRES fLED VSAT Parameter PWM Output Resolution (Note 14) Condition Min -3 -4 Saturation Voltage (Note 12) +3 +4 fLED = 20 kHz, fPLL = 5 MHz 8 fLED = 5 kHz, fPLL = 40 MHz 13 fLED = 10 kHz, fPLL = 40 MHz 12 fLED = 20 kHz, fPLL = 40 MHz 11 PWM_FREQ[4:0] = 00000b LED Switching Frequency (Note PLL clock 5 MHz 14) PWM_FREQ[4:0] = 11111b PLL clock 5 MHz mA % % bits 600 Hz 19.2k Output current set to 20 mA 55 120 175 Output current set to 30 mA 80 180 270 Min Typ Max Units 25 kHz mV PWM Interface Characteristics Symbol Parameter Condition fPWM PWM Frequency Range tMIN_ON Minimum Pulse ON time 1 tMIN_OFF Minimum Pulse OFF time 1 tSTARTUP Turn on delay from standby to backlight on PWM input active, EN pin rise from low to high 6 ms TSTBY Turn Off Delay PWM input low time for turn off, slope disabled 50 ms PWM Input Resolution fIN < 9.0 kHz fIN < 4.5 kHz fIN < 2.2 kHz fIN < 1.1 kHz 10 11 12 13 bits PWMRES www.national.com 0.1 6 µs LP8545 Under-Voltage Protection Symbol Parameter Condition Min UVLO[1:0] = 00 VUVLO VIN UVLO Threshold Voltage Typ Max Units Disabled UVLO[1:0] = 01, falling 2.55 2.70 2.94 UVLO[1:0] = 01, rising 2.62 2.76 3.00 UVLO[1:0] = 10, falling 5.11 5.40 5.68 UVLO[1:0] = 10, rising 5.38 5.70 5.98 UVLO[1:0] = 11, falling 7.75 8.10 8.45 UVLO[1:0] = 11, rising 8.36 8.73 9.20 V Logic Interface Characteristics Symbol Parameter Condition Min Typ Max Units 0.4 V 1.0 µA 0.4 V 1.0 µA 55000 Hz 0.4 V 1.0 µA 0.2xVDDIO V 1.0 µA Logic Input EN VIL Input Low Level VIH Input High Level 1.2 II Input Current -1.0 V Logic Input VSYNC VIL Input Low Level VIH Input High Level 2.2 II Input Current -1.0 fVSYNC Frequency Range 58 V 60 Logic Input PWM VIL Input Low Level VIH Input High Level 2.2 II Input Current -1.0 V Logic Inputs SCL, SDA VIL Input Low Level VIH Input High Level II Input Current 0.8xVDDIO V -1.0 Logic Outputs SDA, FAULT VOL Output Low Level IOUT = 3 mA (pull-up current) IL Output Leakage Current VOUT = 2.8V I2C Serial Bus Timing Parameters (SDA, SCLK) Symbol 0.3 -1.0 V 1.0 µA (Note 13) Limit Parameter 0.5 Min Max 400 Units fSCLK Clock Frequency 1 Hold Time (repeated) START Condition 0.6 µs 2 Clock Low Time 1.3 µs 3 Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time 50 ns 6 Data Setup Time 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns 9 Set-up Time for STOP condition 100 600 7 kHz ns ns www.national.com LP8545 10 Bus Free Time between a STOP and a START Condition 1.3 Cb Capacitive Load Parameter for Each Bus Line Load of 1 pF corresponds to 1 ns. 10 µs 200 ns 30108498 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 130°C (typ.). Note 4: For detailed soldering specifications and information, please refer to National Semiconductor AN1187: Leadless Leadframe Package (LLP). Note 5: Human Body Model, applicable standard JESD22-A114C. Machine Model, applicable standard JESD22- A115-A. Charged Device Model, applicable standard JESD22A-C101. Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 9: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Note 10: Start-up time is measured from the moment boost is activated until the VOUT crosses 90% of its target value. Note 11: Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1 to OUT6), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN/ AVG). The largest number of the two (worst case) is considered the matching figure. The typical specification provided is the most likely norm of the matching figure for all parts. Note that some manufacturers have different definitions in use. Note 12: Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1V. Note 13: Guaranteed by design. VDDIO = 1.65V to 5.5V. Note 14: PWM output resolution and frequency depend on the PLL settings. Please see section “PWM Frequency Settings” for full description www.national.com 8 LP8545 Typical Performance Characteristics Unless otherwise specified: VBATT = 12.0V, CVLDO = 1 μF, L1 = 33 μH, CIN = 10 μF, COUT = 10 μF LED Drive Efficiency, fLED = 19.2 kHz, L1 = 15 μH LED Drive Efficiency, fLED = 19.2 kHz 30108492 30108493 LED Drive Efficiency, fLED = 19.2 kHz, External FET Boost Converter Efficiency 30108490 30108491 Battery Current ILED vs. RISET 30108488 30108489 9 www.national.com LP8545 Typical Waveforms, fLED = 9.6 kHz Typical Waveforms, fLED = 9.6 kHz 30108485 30108486 Boost Line Transient Response 30108484 www.national.com 10 LP8545 Modes of Operation 30108403 In the RESET mode all the internal registers are reset to the default values. Reset is entered always VLDO voltage is low. EN pin is enable for the internal LDO. Power On Reset (POR) will activate during the chip startup or when the supply voltage VLDO fall below POR level. Once VLDO rises above POR level, POR will inactivate and the chip will continue to the STANDBY mode. STANDBY: The STANDBY mode is entered if the register bit BL_CTL is LOW and external PWM input is not active and POR is not active. This is the low-power consumption mode, when only internal 5V LDO is enabled. Registers can be written in this mode and the control bits are effective immediately after startup. STARTUP: When BL_CTL bit is written high or PWM signal is high, the INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (VREF, Bias, Oscillator etc.). Internal EPROM and EEPROM are read in this mode. To ensure the correct oscillator initialization etc, a 2 ms delay is generated by the internal statemachine. If the chip temperature rises too high, the Thermal Shutdown (TSD) disables the chip operation and STARTUP mode is entered until no thermal shutdown event is present. BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is raised in low current PWM mode during the 4 ms delay generated by the state-machine. All LED outputs are off during the 4 ms delay to ensure smooth startup. The Boost startup is entered from Internal Startup Sequence if EN_BOOST is HIGH. NORMAL: During NORMAL mode the user controls the chip using the external PWM input or with Control Registers through I2C. The registers can be written in any sequence and any number of bits can be altered in a register in one write. RESET: 11 www.national.com LP8545 Functional Overview LP8545 is a high voltage LED driver for medium sized LCD backlight applications. It includes high voltage boost converter which can be used either with internal FET or with external FET depending on boost output voltage requirements. Boost voltage automatically sets to the correct level needed to drive the LED strings. This is done by monitoring LED output voltage drop in real time. Six constant current sinks with PWM control are used for driving LEDs. Constant current value is set with EEPROM bits and with RISET resistor. Brightness (PWM) is controlled either with I2C register or with PWM input. PWM frequencies are set with EEPROM bits and with RFSET resistor. Special PhaseShift PWM mode can be used to reduce boost output current peak, thus reducing output ripple, capacitor size and audible noise. With LP8545 it is possible to synchronize the PWM output frequency to VSYNC signal received from video processor. Internal PLL ensures that the PWM output clock is always synchronized to the VSYNC signal. Special dithering mode makes it possible to increase output resolution during fading between two brightness values and by this making the transition look very smooth with virtually no stepping. Transition slope time can be adjusted with EEPROM bits. Safety features include LED fault detection with open and short detection. LED fault detection will prevent system over- heating in case of open in some of the LED strings. Chip internal temperature is constantly monitored and based on this LP8545 can reduce the brightness of the backlight to reduce thermal loading once certain trip point is reached. Threshold is programmable in EEPROM. If chip internal temperature reaches too high, the boost converter and LED outputs are completely turned off until the internal temperature has reached acceptable level. Boost converter is protected against too high load current and over-voltage. LP8545 notifies the system about the fault through I2C register and with FAULT pin. EEPROM programmable functions include: • PWM frequencies • Phase shift PWM mode • LED constant current • Boost output frequency • Temperature thresholds • Slope for brightness changes • Dithering options • PWM output resolution • Boost control bits External components RISET and RFSET can also be used for selecting the output current and PWM frequencies. Block Diagram 30108474 www.national.com 12 LP8545 has internal 5 MHz oscillator which is used for clocking the boost converter, state machine, PWM input duty cycle measurement, internal timings such as slope time for output brightness changes. Internal clock can be used for generating the PWM output frequency. In this case the 5 MHz clock can be multiplied with the internal PLL to achieve higher resolution. The higher the clock frequency for PWM generation block, the higher the resolution but the tradeoff is higher IQ of the part. Clock multiplication is set with <PWM_RESOLUTION[1:0]> EEPROM Bits. The PLL can also be used for generating the required PWM generation clock from the VSYNC signal. This makes sure that 30108404 Principle of the Clock Generation 13 www.national.com LP8545 the LED output PWM is always synchronized to the VSYNC signal and there is no clock variation between LCD display video update and the LED backlight output frequency. Also HSYNC signal up to 55 kHz can be used. PLL has internal counter which has 13-bit control <PLL[12:0] > to achieve correct output clock frequency based on the VSYNC frequency. For the PLL it can take couple of seconds to synchronize to 60 Hz VSYNC signal in startup and before this correct PWM clock frequency is generated from internal oscillator. FILTER pin component selection affects the time it takes from the PLL to lock to VSYNC signal. When backlight is turned off the EN pin must be set low to ensure correct PLL behavior during next startup. Clock Generation LP8545 different frequency than input in this mode and also phase shift PWM mode can be used. Slope and dither are effective in this mode. PWM input resolution is defined by the input PWM clock frequency. Brightness Control Methods LP8545 controls the brightness of the backlight with PWM. PWM control is received either from PWM input pin or from I2C register bits. The PWM source selection is done with <BRT_MODE[1:0]> bits as follows: BRT_MODE BRT_MODE [1] [0] BRIGHTNESS REGISTER CONTROL With brightness register control the output PWM is controlled with 8-bit resolution <BRT7:0> register bits. Phase shift scheme can be used with this and the output PWM frequency can be freely selected. Slope and dither are effective in this mode. PWM source 0 0 PWM input pin duty cycle control. Default. 0 1 PWM input pin duty cycle control. 1 0 Brightness register 1 1 PWM direct control (PWM in = PWM out) PWM DIRECT CONTROL With PWM direct control the output PWM will directly follow the input PWM. Due to the internal logic structure the input is anyway clocked with the 5 MHz clock or the PLL clock. PSPWM mode is not possible in this mode. Slope and dither are not effective in this mode. PWM INPUT DUTY CYCLE With PWM input pin duty cycle control the output PWM is controlled by PWM input duty cycle. PWM detector block measures the duty cycle in the PWM pin and uses this 13-bit value to generate the output PWM. Output PWM can have PWM CALCULATION DATA FLOW Below is flow chart of the PWM calculation data flow. In PWM direct control mode most of the blocks are bypassed and this flow chart does not apply. 30108405 PWM Calculation Data Flow PWM DETECTOR SLOPER PWM detector block measures the duty cycle of the input Sloper makes the smooth transition from one brightness valPWM signal. Resolution depends on the input signal frequenue to another. Slope time can be adjusted from 0 to 500 ms cy. Hysteresis selection sets the minimum allowable change with <SLOPE[3:0]> EEPROM bits. The sloper output is 16-bit to the input. If smaller change is detected, it is ignored. With value. hysteresis the constant changing between two brightness valDITHER ues is avoided if there is small jitter in the input signal. With dithering the output resolution can be “artificially” inBRIGHTNESS CONTROL creased during sloping from one brightness value to another. Brightness control block gets 13-bit value from the PWM deThis way the brightness change steps are not visible to eye. tector, 12-bit value from the temperature sensor and also 8Dithering can be from 0 to 3 bits, and is selected with bit value from the brightness register. <BRT_MODE[1:0]> <DITHER[1:0]> EEPROM bits. selects whether to use PWM input duty cycle value or the PWM COMPARATOR brightness register value as described earlier. Based on the The PWM counter clocks the PWM comparator based on the temperature sensor value the duty cycle is reduced if the duty cycle value received from Dither block. Output of the temperature has reached the temperature limit set to the PWM comparator controls directly the LED drivers. If PSPWM <TEMP_LIM[1:0]> EEPROM bits. mode is used, then the signal to each LED output is delayed RESOLUTION SELECTOR certain amount. Resolution selector takes the necessary MSB bits from the input data to match the output resolution. For example if 11bit resolution is used for output, then 11 MSB bits are selected from the input. Dither bits are not taken into account for the output resolution. This is to make sure that in steady state condition, there is no dithering used for the output. www.national.com 14 PWM FREQUENCY SETTING PWM frequency is selected with PWM_FREQ[4:0] EEPROM register. If PLL clock frequency multiplication is used, it will effect to the output PWM frequency as well. <PWM_RESOLUTION[1:0]> EEPROM bits will select the PLL output frequency and hence the PWM frequency and resolution. Below are listed PWM frequencies with <EN_VSYNC]> = 0. PWM resolution setting affects the PLL clock frequency (5 MHz… 40 MHz). Highlighted frequencies with boldface can be selected also with external resistor RFSET. To activate RFSET frequency selection the <EN_F_RES> EEPROM bit must be 1. Default value for CURRENT[7:0] = 7Fh (127d). Therefore the output current can be calculated as follows: PWM_RES[1:0] 00 01 10 11 PWM FREQ[4:0] 5 MHz 10 MHz 20 MHz 40 MHz Resolution (bits) 11111 19232 - - - 8 11110 16828 - - - 8 11101 14424 - - - 8 11100 12020 - - - 8 11011 9616 19232 - - 9 11010 7963 15927 - - 9 11001 6386 12771 - - 9 11000 4808 9616 19232 - 10 10111 4658 9316 18631 - 10 10110 4508 9015 18030 - 10 10101 4357 8715 17429 - 10 10100 4207 8414 16828 - 10 10011 4057 8114 16227 - 10 10010 3907 7813 15626 - 10 10001 3756 7513 15025 - 10 10000 3606 7212 14424 - 10 01111 3456 6912 13823 - 10 01110 3306 6611 13222 - 10 01101 3155 6311 12621 - 10 01100 3005 6010 12020 - 10 01011 2855 5710 11419 - 10 01010 2705 5409 10818 - 10 01001 2554 5109 10217 - 10 01000 2404 4808 9616 19232 11 00111 2179 4357 8715 17429 11 00110 1953 3907 7813 15626 11 00101 1728 3456 6912 13823 11 00100 1503 3005 6010 12020 11 00011 1202 2404 4808 9616 12 00010 1052 2104 4207 8414 12 00001 826 1653 3306 6611 12 00000 601 1202 2404 4808 13 15 www.national.com LP8545 E.g. If 16 kΩ RISET resistor is used, then the LED maximum current is 23 mA. Note: formula is only approximation for the actual current. CURRENT SETTING Maximum current of the LED outputs is controlled with CURRENT[7:0] EEPROM register bits linearly from 0 to 30 mA. If EN_I_RES = 1 the maximum LED output current can be scaled also with external resistor, RISET. RISET controls the LED current as follows: LP8545 RFSET resistance values with corresponding PWM frequencies: PWM_RES[1:0] 00 RFSET (kΩ) 5 MHz Clock Resolution 01 10 11 10 MHz Clock Resolution 20 MHz Clock Resolution 40 MHz Clock Resolution 10...15 19232 8 19232 9 19232 10 19232 11 26...29 16828 8 15927 9 16227 10 17429 11 36...41 14424 8 12771 9 14424 10 15626 11 50...60 12020 8 9616 10 12020 10 12020 11 85...100 9616 9 8715 10 9616 11 9616 12 135...150 7963 9 7813 10 7813 11 8414 12 200...300 6386 9 6311 10 6010 11 6811 12 450... 4808 10 4808 11 4808 12 4808 13 on boost output by x6 and therefore transfers the possible audible noise to so high frequency that human ear cannot hear it. Description of the PSPWM mode is seen on the following diagram. PSPWM mode is enabled by setting <EN_PSPWM> EEPROM bit to 1. Shift time is the delay between outputs and it is defined as 1 / (fPWM x 6). If the <EN_PSPWM> bit is 0, then the delay is 0 and all outputs are active simultaneously. PHASE SHIFT PWM SCHEME Phase shift PWM scheme allows delaying the time when each LED output is active. When the LED output are not activated simultaneously, the peak load current from the boost output is greatly decreased. This reduces the ripple seen on the boost output and allows smaller output capacitors. Reduced ripple also reduces the output ceramic capacitor audible ringing. PSPWM scheme also increases the load frequency seen 30108406 Phase Shift PWM Mode www.national.com 16 30108483 Sloper Operation 30108494 Example of the Dithering, 1-bit dither, 10-bit resolution DRIVER HEADROOM CONTROL ward voltage is the one which has highest VF across the LEDs. The strings with highest forward voltage is detected Driver headroom can be controlled with automatically. To achieve best possible efficiency smallest <DRV_HEADR[2:0]> EEPROM bits. Driver headroom control possible headroom voltage should be selected. If there is high sets the minimum threshold for the voltage over the LED outvariation between LED strings, the headroom can be raised put which has the smallest driver headroom and controls the slightly to prevent any visual artifacts. boost output voltage accordingly. Boost output voltage step size is 125 mV. The LED output which has the smallest for- 17 www.national.com LP8545 ms. Same slope time is used for sloping up and down. Advanced slope makes brightness changes smooth for eye. Dithering can be programmed with EEPROM bits <DITHER [1:0]> from 0 to 3 bits. Example below is for 1-bit dithering, e.g., for 3-bit dithering, every 8th pulse is made 1 LSB longer to increase the average value by 1/8 of LSB. SLOPE AND DITHERING During transition between two brightness (PWM) values special dithering scheme is used if the slope is enabled. It allows increased resolution and smaller average steps size. Dithering is not used in steady state condition. Slope time can be programmed with EEPROM bits <SLOPE[3:0]> from 0 to 500 LP8545 written through the serial interface, and data will be effective immediately. To read and program NVM, separate commands need to be sent. Erase and program voltages are generated on-chip charge pump, no other voltages than normal input voltage are required. A complete EEPROM memory map is shown in the chapter LP8545 EEPROM Memory Map. EEPROM EEPROM memory stores various parameters for chip control. The 64-bit EEPROM memory is organized as 8 x 8 bits. The EEPROM structure consists of a register front-end and the non-volatile memory (NVM). Register data can be read and 30108439 current is measured and controlled with the feedback. Switching frequency is selectable between 156 kHz and 1.25 MHz with EEPROM bit <BOOST_FREQ[1:0]>. When <EN_BOOST> EEPROM register bit is set to 1, then boost will activate automatically when backlight is enabled. In adaptive mode the boost output voltage is adjusted automatically based on LED driver headroom voltage. Boost output voltage control step size is, in this case, 125 mV to ensure as small as possible driver headroom and high efficiency. Enabling the adaptive mode is done with <EN_ADAPT> EEPROM bit. If boost is started with adaptive mode enabled, then the initial boost output voltage value is defined with the <VBOOST[4:0]> EEPROM register bits in order to eliminate long output voltage iteration time when boost is started for the first time. The following figure shows the boost topology with the protection circuitry: Boost Converter OPERATION The LP8545 boost DC/DC converter generates a 10…40V supply voltage for the LEDs from 2.7…22V input voltage. The output voltage can be controlled either with EEPROM register bits <VBOOST[4:0]> or automatic adaptive voltage control can be used. Higher output voltages can be achieved with external FET and by using resistor divider in the FB pin. GD pin operates as gate driver for the external FET in this case. To activate external FET gate driver, <EN_EXT_FET> bit in EEPROM register must be set to 1. The converter is a magnetic switching PWM mode DC/DC converter with a current limit. The topology of the magnetic boost converter is called CPM (current programmed mode) control, where the inductor 30108440 www.national.com 18 ADAPTIVE BOOST CONTROL Adaptive boost control function adjusts the boost output voltage to the minimum sufficient voltage for proper LED driver operation. The output with highest VF LED string is detected and boost output voltage adjusted accordingly. Driver headroom can be adjusted with <DRIVER_HEADR[2:0]> EEPROM bits from ~300 mV to 1200 mV. Boost adaptive control voltage step size is 125 mV. Boost adaptive control operates similarly with and without PSPWM. MANUAL OUTPUT VOLTAGE CONTROL User can control the boost output voltage with <VBOOST[4:0] > EEPROM register bits when adaptive mode is disabled. VBOOST[4:0] Voltage (typical) Bin Dec Volts 00000 0 10 00001 1 11 00010 2 12 00011 3 13 00100 4 14 ... ... ... 11101 29 39 11110 30 40 11111 31 40 30108441 Boost Adaptive Control Principle with PSPWM If resistor divider is used for the FB pin to get higher output voltage with external FET, the boost output voltages are scaled accordingly. 19 www.national.com LP8545 PROTECTION Three different protection schemes are implemented: 1. Over-voltage protection, limits the maximum output voltage. — Over-voltage protection limit changes dynamically based on output voltage setting. — Keeps the output below breakdown voltage. — Prevents boost operation if battery voltage is much higher than desired output. 2. Over-current protection, limits the maximum inductor current. 3. Duty cycle limiting. LP8545 fault bit is set in fault register. LEDs and boost will start again when the voltage has increased above the threshold level. Hysteresis is implemented to threshold level to avoid continuous triggering of fault when threshold is reached. Fault is cleared by setting EN pin low or by reading the fault register. Fault Detection LP8545 has fault detection for LED fault, low-battery voltage, over-current and thermal shutdown. The open drain output pin (FAULT) can be used to indicate occurred fault. The cause for the fault can be read from status register. Reading the fault register will also reset the fault. Setting the EN pin low will also reset the faults, even if an external 5V line is used to power VLDO pin. OVER-CURRENT PROTECTION LP8545 has detection for too-high loading on the boost converter. When over-current fault is detected, the LP8545 will shut down. Fault is cleared by setting EN pin low or by reading the fault register. LED FAULT DETECTION With LED fault detection, the voltages across the LED drivers are constantly monitored. LED fault detection is enabled with <EN_LED_FAULT> EEPROM bit. Shorted or open LED string is detected. If LED fault is detected: • The corresponding LED string is taken out of boost adaptive control loop; • Fault bits are set in the fault register to identify whether the fault has been open/short and how many strings are faulty; and • Fault open-drain pin is pulled down. LED fault sensitivity can be adjusted with <LED_FAULT_THR [1:0]> EEPROM bits which sets the allowable variation between LED output voltage from 2.3V to 5.3V. Depending on application and how much variation there can be in normal operation between LED string forward voltages this setting can be adjusted. Fault is cleared by setting EN pin low or by reading the fault register. DEVICE THERMAL REGULATION LP8545 has an internal temperature sensor which can be used to measure the junction temperature of the device and protect the device from overheating. During thermal regulation, LED PWM is reduced by 2% of full scale per °C whenever the temperature threshold is reached. Temperature regulation is enabled automatically when chip is enabled. 11-bit temperature value can be read from Temp MSB and Temp LSB registers, MSB should be read first. Temperature limit can be programmed in EEPROM as shown in the following table. Thermal regulation function does not generate fault signal. UNDER-VOLTAGE DETECTION LP8545 has detection for too-low VIN voltage. Threshold level for the voltage is set with EEPROM register bits as seen in the following table: UVLO[1:0] OFF 01 2.7V 10 5.7V 11 8.7V When under voltage is detected the LED outputs and boost will shutdown, FAULT pin is pulled down and corresponding www.national.com Over-Temp Limit (°C) 00 OFF 01 110 10 120 11 130 THERMAL SHUTDOWN If the LP8545 reaches thermal shutdown temperature (150° C ) the LED outputs and boost will shut down to protect it from damage. Also the fault pin will be pulled down to indicate the fault state. Device will activate again when temperature drops below 130°C degrees. Fault is cleared by setting EN pin low or by reading the fault register. Threshold (V) 00 TEMP_LIM[1:0] 20 INTERFACE BUS OVERVIEW The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCLK). These lines should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is idle. Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the SCLK. The LP8545 is always a slave device. 30108449 Bit Transfer Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process. DATA TRANSACTIONS One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock SCLK. Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line during the high state of the SCLK and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCLK state. This protocol permits a single data line to 30108420 Start and Stop The Master device on the bus always generates the Start and In addition to the first Start Condition, a repeated Start ConStop Conditions (control codes). After a Start Condition is dition can be generated in the middle of a transaction. This generated, the bus is considered busy and it retains this staallows another device to be accessed, or a register read cycle. tus until a certain time after a Stop Condition is generated. A ACKNOWLEDGE CYCLE high-to-low transition of the data line (SDA) while the clock The Acknowledge Cycle consists of two signals: the acknowl(SCLK) is high indicates a Start Condition. A low-to-high tranedge clock pulse the master sends with each byte transferred, sition of the SDA line while the SCLK is high indicates a Stop and the acknowledge signal sent by the receiving device. Condition. The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte. “ACKNOWLEDGE AFTER EVERY BYTE” RULE The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked out of the slave. This 30108450 Start and Stop Conditions 21 www.national.com LP8545 transfer both command/control information and data using the synchronous serial clock. I2C Compatible Serial Bus Interface LP8545 “negative acknowledge” still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. ADDRESSING TRANSFER FORMATS Each device on the bus has a unique slave address. The LP8545 operates as a slave device with 7-bit address combined with data direction bit. Slave address is 2Ch as 7-bit or 58h for write and 59h for read in 8-bit format. Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit. When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver. Control Register Read Cycle • Master device generates a start condition. • Master device sends slave address (7 bits) and the data direction bit (r/w = 0). • Slave device sends acknowledge signal if the slave address is correct. • Master sends control register address (8 bits). • Slave sends acknowledge signal. • Master device generates repeated start condition. • Master sends the slave address (7 bits) and the data direction bit (r/w = 1). • Slave sends acknowledge signal if the slave address is correct. • Slave sends data byte from addressed register. • If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register. • Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition. I2C Chip Address Data Read and Write Cycles Address Mode Data Read <Start Condition> <Slave Address><r/w = 0>[Ack] <Register Addr.>[Ack] <Repeated Start Condition> <Slave Address><r/w = 1>[Ack] [Register Data]<Ack or NAck> … additional reads from subsequent register address possible <Stop Condition> Data Write <Start Condition> <Slave Address><r/w=’0’>[Ack] <Register Addr.>[Ack] <Register Data>[Ack] … additional writes to subsequent register address possible <Stop Condition> 30108451 Control Register Write Cycle • Master device generates start condition. • Master device sends slave address (7 bits) and the data direction bit (r/w = 0). • Slave device sends acknowledge signal if the slave address is correct. • Master sends control register address (8 bits). • Slave sends acknowledge signal. • Master sends data byte to be written to the addressed register. • Slave sends acknowledge signal. • If master will send further data bytes the control register address will be incremented by one after acknowledge signal. • Write cycle ends when the master creates stop condition. www.national.com <>Data from master [ ] Data from slave 22 LP8545 Register Read and Write Detail 30108447 30108495 23 www.national.com LP8545 Recommended External Components reduce the effective capacitance by up to 80%, which needs to be considered in capacitance value selection. For light loads a 4.7 µF capacitor is sufficient. Effectively the capacitance should be 4 µF for < 150 mA loads. For maximum output voltage/current 10 µF capacitor (or two 4.7 µF capacitors) is recommended to minimize the output ripple. For high output voltage (55V) application 100V voltage rating capacitors should be used. 2 x 2.2 µF capacitors are enough. INDUCTOR SELECTION There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of application should be requested from the manufacturer. Shielded inductors radiate less noise and should be preferred. The saturation current should be greater than the sum of the maximum load current and the worst case average to peak inductor current. The equation below shows the worst case conditions. LDO CAPACITOR A 1µF ceramic capacitor with 10V voltage rating is recommended for the LDO capacitor. OUTPUT DIODE A Schottky diode should be used for the output diode. Peak repetitive current should be greater than inductor peak current (2.5A) to ensure reliable operation. Average current rating should be greater than the maximum output current. Schottky diodes with a low forward drop and fast switching speeds are ideal for increasing efficiency in portable applications. Choose a reverse breakdown voltage of the Schottky diode significantly larger (~60V) than the output voltage. Do not use ordinary rectifier diodes, since slow switching speeds and long recovery times cause the efficiency and the load regulation to suffer. BOOST CONVERTER TRANSISTOR FET transistor with high enough voltage rating (VDS at least 60V) should be used. Current rating for the FET should be the same as inductor peak current (2.5A with highest programmed inductor current). Gate drive voltage for the FET is 5V. • IRIPPLE: Average to peak inductor current • IOUTMAX: Maximum load current • VIN: Maximum input voltage in application • L: Min inductor value including worst case tolerances • f: Minimum switching frequency • D: Duty cycle for CCM Operation • VOUT: Output voltage Example using above equations: • VIN = 12V • VOUT = 38V • IOUT = 400 mA • L = 15 µH − 20% = 12 µH • f = 1.25 MHz • ISAT = 1.6A As a result the inductor should be selected according to the ISAT. A more conservative and recommended approach is to choose an inductor that has a saturation current rating greater than the maximum current limit of 2.5A. A 15 μH inductor with a saturation current rating of 2.5A is recommended for most applications. The inductor’s resistance should be less than 300 mΩ for good efficiency. For high efficiency choose an inductor with high frequency core material such as ferrite to reduce core losses. To minimize radiated noise, use shielded core inductor. Inductor should be placed as close to the SW pin and the IC as possible. Special care should be used when designing the PCB layout to minimize radiated noise and to get good performance from the boost converter. RESISTOR DIVIDER FOR THE BOOST FEEDBACK Recommended values for feedback resistor divider to get 55V boost output voltage are R1 = 63.4 kΩ and R2 = 59 kΩ. Resistor values can be fine tuned to get desired maximum boost output voltage based on how many LEDs are driven in series and what are the forward voltage specifications for the LEDs. Voltage on FB pin must not exceed 40V any time. RESISTORS FOR SETTING THE LED CURRENT AND PWM FREQUENCY See EEPROM register description on how to select values for these resistors FILTER COMPONENT VALUES Optimal components for 60 Hz VSYNC frequency and 4 Hz cutoff frequency of the low-pass filter are shown in the typical application diagrams and in the figure below. If 2 Hz cut-off frequency i.e. slower response time is desired, filter components are: C1 = 1 µF, C2 = 10 µF and R = 47 kΩ. If different VSYNC frequency or response time is desired, please contact National Semiconductor representative for guidance. OUTPUT CAPACITOR A ceramic capacitor with 50V voltage rating or higher is recommended for the output capacitor. The DC-bias effect can www.national.com 30108481 24 REGISTER Brightness Control Device Control Fault ID Direct Control Temp MSB Temp LSB EEPROM_control ADDR 00H 01H 02H 03H 04H 05H 06H 72H Register Map EE_READY PANEL OPEN D7 TEMP[2:0] SHORT D6 D4 D3 TEMP[10:3] D1 OCP EE_PROG REV[2:0] TSD BRT_MODE[1:0] D2 EE_INIT OUT[6:1] BL_FAULT BRT[7:0] 1_CHANNEL MFG[3:0] 2_CHANNELS D5 EE_READ UVLO BL_CTL D0 DEFAULT 0000 0000 0000 0000 0000 0000 0000 0000 1111 1100 0000 0000 0000 0000 0000 0000 LP8545 25 www.national.com www.national.com 26 REGISTER eeprom addr 0 eeprom addr 1 eeprom addr 2 eeprom addr 3 eeprom addr 4 eeprom addr 5 eeprom addr 6 eeprom addr 7 ADDR A0H A1H A2H A3H A4H A5H A6H A7H EEPROM Memory Map D6 EN_VSYNC D5 EN_I_RES EN_PSPWM ADV_SLOPE EN_LED_FAU LT PLL[4:0] DITHER[1:0] PWM_RESOLUTION[1:0] UVLO[1:0] ADAPTIVE_SPEED[1:0] BOOST_FREQ[1:0] D7 D3 EN_ADAPT PLL[12:5] LED_FAULT_THR[1:0] EN_EXT_FET TEMP_LIM[1:0] CURRENT[7:0] D4 EN_F_RES VBOOST[4:0] D0 BOOST_MAX[1:0] SLOPE[2:0] D1 HYSTERESIS[1:0] DRV_HEADR[2:0] PWM_FREQ[4:0] EN_BOOST D2 LP8545 LP8545 Register Bit Explanations BRIGHTNESS CONTROL Address 00h Reset value 0000 0000b Brightness Control register 7 6 5 4 3 2 1 2 1 0 BRT[7:0] Name Bit Access BRT 7:0 R/W Description Backlight PWM 8-bit linear control. DEVICE CONTROL Address 01h Reset value 0000 0000b Device Control register 7 6 5 4 3 0 BRT_MODE[1:0] BL_CTL Name Bit Access BRT_MODE 2:1 R/W Description PWM source mode 00b = PWM input pin duty cycle control (default) 01b = PWM input pin duty cycle control 10b = Brightness register 11b = Direct PWM control from PWM input pin BL_CTL 0 R/W Enable backlight 0 = Backlight disabled and chip turned off if BRT_MODE[1:0] = 10. In external PWM pin control the state of the chip is defined with the PWM pin and this bit has no effect. 1 = Backlight enabled and chip turned on if BRT_MODE[1:0] = 10. In external PWM pin control the state of the chip is defined with the PWM pin and this bit has no effect. FAULT Address 02h Reset value 0000 0000b Fault register 7 6 5 4 3 2 1 0 OPEN SHORT 2_CHANNELS 1_CHANNEL BL_FAULT OCP TSD UVLO Name Bit Access OPEN 7 R Description LED open fault detection 0 = No fault 1 = LED open fault detected. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. SHORT 6 R LED short fault detection 0 = No fault 1 = LED short fault detected. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. 27 www.national.com LP8545 Fault register 2_CHANNEL S 5 R LED fault detection 0 = No fault 1 = 2 or more channels have generated either short or open fault. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. 1_CHANNEL 4 R LED fault detection 0 = No fault 1 = 1 channel has generated either short or open fault. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. BL_FAULT 3 R LED fault detection 0 = No fault 1 = LED fault detected. Generated with OR function of all LED faults. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. OCP 2 R Over current protection 0 = No fault 1 = Over current detected in boost output. OCP detection block monitors the boost output and if the boost output has been too low for more than 50 ms it will generate OCP fault and disable the boost. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. After clearing the fault boost will startup again. TSD 1 R Thermal shutdown 0 = No fault 1 = Thermal fault generated, 150°C reached. Boost converted and LED outputs will be disabled until the temperature has dropped down to 130°C. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. UVLO 0 R Under voltage detection 0 = No fault 1 = Under voltage detected in VIN pin. Boost converted and LED outputs will be disabled until VIN voltage is above the threshold voltage. Threshold voltage is set with EEPROM bits from 3V...9V. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. IDENTIFICATION Address 03h Reset value 1111 1100b Identification register 7 6 5 PANEL 4 3 MFG[3:0] 1 REV[2:0] Name Bit Access PANEL 7 R Panel ID code MFG 6:3 R Manufacturer ID code REV 2:0 R Revision ID code www.national.com 2 Description 28 0 LP8545 DIRECT CONTROL Address 04h Reset value 0000 0000b Direct Control register 7 6 5 4 3 2 1 0 OUT[6:1] Name Bit Access OUT 5:0 R/W Description Direct control of the LED outputs 0 = Normal operation. LED output are controlled with PWM. 1 = LED output is forced to 100% PWM. TEMP MSB Address 05h Reset value 0000 0000b Temp MSB register 7 6 5 4 3 2 1 0 TEMP[10:3] Name Bit Access TEMP 7:0 R Description Device internal temperature sensor reading first 8 MSB. MSB must be read before LSB, because reading of MSB register latches the data. TEMP LSB Address 06h Reset value 0000 0000b Temp LSB register 7 6 5 4 3 2 1 0 TEMP[2:0] Name Bit Access TEMP 7:5 R Description Device internal temperature sensor reading last 3 LSB. MSB must be read before LSB, because reading of MSB register latches the data. 29 www.national.com LP8545 EEPROM CONTROL Address 72h Reset value 0000 0000b EEPROM Control register 7 6 5 4 3 EE_READY 2 1 0 EE_INIT EE_PROG EE_READ Name Bit Access EE_READY 7 R Description EE_INIT 2 R/W EEPROM initialization bit. This bit must be written 1 before EEPROM read or programming. EE_PROG 1 R/W EEPROM programming. 0 = Normal operation 1 = Start the EEPROM programming sequence. EE_INIT must be written 1 before EEPROM programming can be started. Programs data currently in the EEPROM registers to non volatile memory (NVM). Programming sequence takes about 200 ms. Programming voltage is generated inside the chip. EE_READ 0 R/W EEPROM read 0 = Normal operation 1 = Reads the data from NVM to the EEPROM registers. Can be used to restore default values if EEPROM registers are changed during testing. EEPROM ready 0 = EEPROM programming or read in progress 1 = EEPROM ready, not busy Programming sequence (program data permanently from registers to NVM): 1. 2. 3. 4. 5. 6. Turn on the chip by writing BL_CTL bit to 1 and BRT_MODE[1:0] to 10b (05h to address 01h) Write data to EEPROM registers (address A0h…A7h). Write EE_INIT to 1 in address 72h. (04h to address 72h). Write EE_PROG to 1 and EE_INIT to 0 in address 72h. (02h to address 72h). Wait 200 ms. Write EE_PROG to 0 in address 72h. (00h to address 72h). Read sequence (load data from NVM to registers): 1. 2. 3. 4. 5. Turn on the chip by writing BL_CTL bit to 1 and BRT_MODE[1:0] to 10b (05h to address 01h). Write EE_INIT to 1 in address 72h. (04h to address 72h). Write EE_READ to 1 and EE_INIT to 0 in address 72h. (01h to address 72h). Wait 200 ms. Write EE_READ to 0 in address 72h. (00h to address 72h). Note: Data written to EEPROM registers is effective immediately even if the EEPROM programming sequence has not been done. When power is turned off, the device will however lose the data if it is not programmed to the NVM. During startup device automatically loads the data from NVM to registers. www.national.com 30 LP8545 EEPROM Bit Explanations EEPROM Default Values ADDR LP8545SQX A0H 0111 1111 A1H 1011 0101 A2H 1010 1111 A3H 0111 1011 A4H 0010 1000 A5H 1100 1111 A6H 0110 0100 A7H 0010 1101 EEPROM ADDRESS 0 Address A0h EEPROM ADDRESS 0 register 7 6 5 4 3 2 1 0 CURRENT[7:0] Name Bit Access Description CURRENT 7:0 R/W Backlight current adjustment. If EN_I_RES = 0 the maximum backlight current is defined only with these bits as described below. If EN_I_RES = 1, then the external resistor connected to ISET pin also scales the LED current. With 16 kΩ resistor and CURRENT set to 7FH the output current is then 23 mA. EN_I_RES = 0 EN_I_RES = 1 0000 0000 0 mA 0 mA 0000 0001 0.12 mA (1/255) x 600 x 1.23V/RISET 0000 0010 0.24 mA (2/255) x 600 x 1.23V/RISET ... ... ... 0111 1111 (default) 15.00 mA (127/255) x 600 x 1.23V/RISET ... ... ... 1111 1101 29.76 mA (253/255) x 600 x 1.23V/RISET 1111 1110 29.88 mA (254/255) x 600 x 1.23V/RISET 1111 1111 30.00 mA (255/255) x 600 x 1.23V/RISET EEPROM ADDRESS 1 Address A1h EEPROM ADDRESS 1 register 7 6 BOOST_FREQ[1:0] 5 EN_LED_FAULT Name Bit Access BOOST_FREQ 7:6 R/W 4 3 TEMP_LIM[1:0] 2 1 0 SLOPE[2:0] Description Boost Converter Switch Frequency 00 = 156 kHz 01 = 312 kHz 10 = 625 kHz 11 = 1250 kHz 31 www.national.com LP8545 EEPROM ADDRESS 1 register EN_LED_FAULT 5 R/W Enable LED fault detection 0 = LED fault detection disabled 1 = LED fault detection enabled TEMP_LIM 4:3 R/W Thermal deration function temperature threshold 00 = thermal deration function disabled 01 = 110°C 10 = 120°C 11 = 130°C SLOPE 2:0 R/W Slope time for brightness change 000 = Slope function disabled, immediate brightness change 001 = 50 ms 010 = 75 ms 011 = 100 ms 100 = 150 ms 101 = 200 ms 110 = 300 ms 111 = 500 ms EEPROM ADDRESS 2 Address A2h EEPROM ADDRESS 2 register 7 6 ADAPTIVE_SPEED[1:0] 5 4 3 2 ADV_SLO PE EN_EXT_FET EN_ADAPT EN_BOOST 1 0 BOOST_IMAX[1:0] Name Bit Access ADAPTIVE SPEED[1] 7 R/W Boost converter adaptive control speed adjustment 0 = Normal mode 1 = Adaptive mode optimized for light loads. Activating this helps the voltage droop with light loads during boost / backlight startup. ADAPTIVE SPEED[0] 6 R/W Boost converter adaptive control speed adjustment 0 = Adjust boost once for each phase shift cycle or normal PWM cycle 1 = Adjust boost every 16th phase shift cycle or normal PWM cycle ADV_SLOPE 5 R/W Advanced slope 0 = Advanced slope is disabled 1 = Use advanced slope for brightness change to make brightness changes smooth for eye EN_EXT_FET 4 R/W Enable external FET gate driver 0 = Internal FET used 1 = External FET used and GD pin used for driving the external FET gate EN_ADAPT 3 R/W Enable boost converter adaptive mode 0 = adaptive mode disabled, boost converter output voltage is set with VBOOST EEPROM register bits 1 = adaptive mode enabled. Boost converter startup voltage is set with VBOOST EEPROM register bits, and after startup voltage is reached the boost converter will adapt to the highest LED string VF. LED driver output headroom is set with DRV_HEADR EEPROM control bits. EN_BOOST 2 R/W Enable boost converter 0 = boost is disabled 1 = boost is enabled and will turn on automatically when backlight is enabled www.national.com Description 32 LP8545 EEPROM ADDRESS 2 register BOOST_IMAX 1:0 R/W Boost converter inductor maximum current 00 = 0.9A 01 = 1.4A 10 = 2.0A 11 = 2.5A (recommended) EEPROM ADDRESS 3 Address A3h EEPROM ADDRESS 3 register 7 6 UVLO[1:0] 5 4 3 EN_PSPWM 2 1 0 PWM_FREQ[4:0] Name Bit Access UVLO 7:6 R/W Description 00 = Disabled 01 = 2.7V 10 = 6V 11 = 9V EN_PSPWM 5 R/W Enable phase shift PWM scheme 0 = phase shift PWM disabled, normal PWM mode used 1 = phase shift PWM enabled PWM_FREQ 4:0 R/W PWM output frequency setting. See pg. 15 for full description of selectable PWM frequencies. EEPROM ADDRESS 4 Address A4h EEPROM ADDRESS 4 register 7 6 PWM_RESOLUTION[1:0] 5 EN_I_RES 4 3 LED_FAULT_THR[1:0] 2 1 0 DRV_HEADR[2:0] Name Bit Access Description PWM RESOLUTION 7:6 R/W PWM output resolution selection. Actual resolution depends also on the output frequency. See pg. 15 for full description. 00 = 8...10 bits (19.2 kHz...4.8 kHz) 01 = 9...11 bits (19.2 kHz... 4.8 kHz) 10 = 10...12 bits (19.2 kHz...4.8 kHz) 11 = 11...13 bits (19.2 kHz...4.8 kHz) EN_I_RES 5 R/W Enable LED current set resistor 0 = Resistor is disabled and current is set only with CURRENT EEPROM register bits 1 = Enable LED current set resistor. LED current is defined by the RISET resistor and the CURRENT EEPROM register bits. LED_FAULT_T HR 4:3 R/W LED fault detector thresholds. VSAT is the saturation voltage of the driver, typically 200 mV. 00 = 2.3V 01 = 3.3V 10 = 4.3V 11 = 5.3V 33 www.national.com LP8545 EEPROM ADDRESS 4 register DRV_HEADR 2:0 R/W LED output driver headroom control. VSAT is the saturation voltage of the driver, typically 200 mV. 000 = VSAT + 125 mV 001 = VSAT + 250 mV 010 = VSAT + 375 mV 011 = VSAT + 500 mV 100 = VSAT + 625 mV 101 = VSAT + 750 mV 110 = VSAT + 875 mV 111 = VSAT + 1000 mV EEPROM ADDRESS 5 Address A5h EEPROM ADDRESS 5 register 7 6 EN_VSYNC 5 4 3 DITHER[1:0] 2 1 0 VBOOST[4:0] Name Bit Access EN_VSYNC 7 R/W Description Enable VSYNC function 0 = VSYNC input disabled 1 = VSYNC input enabled. VSYNC signal is used by the internal PLL to generate PWM output and boost frequency. DITHER 6:5 R/W Dither function controls 00 = Dither function disabled 01 = 1-bit dither used for output PWM transitions 10 = 2-bit dither used for output PWM transitions 11 = 3-bit dither used for output PWM transitions VBOOST 4:0 R/W Boost voltage control from 10V to 40V with 1V step (without FB resistor divider). If adaptive boost control is enabled, this sets the initial start voltage for the boost converter. If adaptive mode is disabled, this will directly set the output voltage of the boost converter. 0 0000 = 10V 0 0001 = 11V 0 0010 = 12V ... 1 1101 = 39V 1 1110 = 40V 1 1111 = 40V www.national.com 34 LP8545 EEPROM ADDRESS 6 Address A6h EEPROM ADDRESS 6 register 7 6 5 4 3 2 1 0 PLL[12:5] Name Bit Access PLL 7:0 R/W Description 13-bit counter value for PLL, 8 MSB bits. PLL[12:0] bits are used when en_vsync = 1. See table below for PLL value calculation. EEPROM ADDRESS 7 Address A7h EEPROM ADDRESS 7 register 7 6 5 4 3 PLL[4:0] 2 EN_F_RES 1 0 HYSTERESIS[1:0] Name Bit Access PLL 7:3 R/W Description 13-bit counter value for PLL, 5 LSB bits. PLL[12:0] bits are used when en_vsync = 1. See table below for PLL value calculation. EN_F_RES 2 R/W Enable PWM output frequency set resistor 0 = Resistor is disabled and PWM output frequency is set with PWM_FREQ EEPROM register bits 1 = PWM frequency set resistor is enabled. RFSET defines the output PWM frequency. See pg. 15 for full description of the PWM frequencies. HYSTERESIS 1:0 R/W PWM input hysteresis function. Will define how small changes in the PWM input are ignored to remove constant switching between two values. 00 = OFF 01 = 1-bit hysteresis with 11-bit resolution 10 = 1-bit hysteresis with 10-bit resolution 11 = 1-bit hysteresis with 8-bit resolution PLL value calculation en_vsync PLL frequency [MHz] 0 5, 10, 20, 40 not used 5 5 MHz / (26 x fVSYNC) 10 10 MHz / (50 x fVSYNC) 20 20 MHz / (98 x fVSYNC) 40 40 MHz / (196 x fVSYNC) 1 PLL[12:0] PLL frequency is set by PWM_RESOLUTION[1:0] bits. For Example: If fPLL = 5 MHz and fVSYNC = 60 Hz, then PLL[12:0] = 5000000 Hz / (26 * 60 Hz) = 3205d = C85h. If fPLL = 10 MHz and fVSYNC = 75 Hz, then PLL[12:0] = 10000000 Hz / (50 * 75 Hz) = 2667d = A6Bh. 35 www.national.com LP8545 Physical Dimensions inches (millimeters) unless otherwise noted SQA24A: LLP-24, 0.5mm pitch, no pullback www.national.com 36 LP8545 Notes 37 www.national.com LP8545 High-Efficiency LED Backlight Driver for Notebooks Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2011 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Technical Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Technical Support Center Email: [email protected] National Semiconductor Asia Pacific Technical Support Center Email: [email protected] National Semiconductor Japan Technical Support Center Email: [email protected] IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page www.ti.com/video e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated