LTC1608 High Speed, 16-Bit, 500ksps Sampling A/D Converter with Shutdown U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO A Complete, 500ksps 16-Bit ADC 90dB S/(N+D) and –100dB THD (Typ) Power Dissipation: 270mW (Typ) No Pipeline Delay No Missing Codes Over Temperature Nap (7mW) and Sleep (10µW) Shutdown Modes Operates with Internal 15ppm/°C Reference or External Reference True Differential Inputs Reject Common Mode Noise 5MHz Full Power Bandwidth ±2.5V Bipolar Input Range 36-Pin SSOP Package Pin Compatible with the LTC1604 The LTC®1608 is a 500ksps, 16-bit sampling A/D converter that draws only 270mW from ±5V supplies. This high performance device includes a high dynamic range sample-and-hold, a precision reference and a high speed parallel output. Two digitally selectable power shutdown modes provide power savings for low power systems. Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems The ADC has µP compatible,16-bit parallel output port. There is no pipeline delay in conversion results. A separate convert start input and a data ready signal (BUSY) ease connections to FlFOs, DSPs and microprocessors. The LTC1608’s full-scale input range is ± 2.5V. Outstanding AC performance includes 90dB S/(N+D) and – 100dB THD at a sample rate of 500ksps. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 15MHz bandwidth. The 68dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. U APPLICATIO S ■ ■ ■ ■ ■ ■ , LTC and LT are registered trademarks of Linear Technology Corporation. Circuitry in the LTC1608 is covered under US Patent #5,764,175 U TYPICAL APPLICATIO 10µF 2.2µF 10Ω + 3 VREF 5V 10µF + 36 AVDD 5V 35 9 AVDD 10µF + 10 DVDD LTC1608 4096 Point FFT DGND SHDN 33 4 REFCOMP 7.5k 1.75X + CONTROL LOGIC AND TIMING 2.5V REF 0 CONVST 31 RD 30 OVDD 29 + + 1 AIN DIFFERENTIAL ANALOG INPUT ± 2.5V – 2 AIN + – OGND 28 16-BIT SAMPLING ADC AGND 5 AGND 6 OUTPUT BUFFERS B15 TO B0 AGND 7 8 16-BIT PARALLEL BUS 1608 TA01 34 + 10µF 5V OR 3V 10µF –40 –60 –80 –100 D15 TO D0 11 TO 26 AGND VSS –20 µP CONTROL LINES BUSY 27 22µF fSAMPLE = 500kHz fIN = 98.754kHz SINAD = 86.7dB THD = –92.6dB CS 32 AMPLITUDE (dB) LTC1608 –120 –140 0 50 100 150 FREQUENCY (kHz) 200 250 1608 TA02 –5V 1 LTC1608 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO AVDD = DVDD = OVDD = VDD (Notes 1, 2) ORDER PART NUMBER TOP VIEW Supply Voltage (VDD) ................................................ 6V Negative Supply Voltage (VSS) ............................... – 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V) VREF Voltage (Note 4) ................. – 0.3V to (VDD + 0.3V) REFCOMP Voltage (Note 4) ......... – 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) ....................– 0.3V to 10V Digital Output Voltage .................. – 0.3V to (VDD + 0.3V) Power Dissipation ............................................. 500mW Operating Temperature Range .................... 0°C to 70°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C AIN+ 1 AIN– 2 36 AVDD 35 AVDD VREF 3 34 VSS REFCOMP 4 33 SHDN AGND 5 32 CS AGND 6 31 CONV AGND 7 30 RD AGND 8 29 OVDD DVDD 9 28 OGND DGND 10 27 BUSY D15 (MSB) 11 26 D0 D14 12 25 D1 D13 13 24 D2 D12 14 23 D3 D11 15 22 D4 D10 16 21 D5 D9 17 20 D6 D8 18 LTC1608CG LTC1608ACG 19 D7 G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 95°C/W Consult factory for parts specified with wider operating temperature ranges. U CO VERTER CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6), unless otherwise noted. PARAMETER CONDITIONS MIN Resolution (No Missing Codes) Integral Linearity Error 15 ● (Note 7) (Note 8) Offset Error (Note 9) Offset Tempco (Note 9) Full-Scale Error Internal Reference External Reference Full-Scale Tempco IOUT(Reference) = 0, Internal Reference U U A ALOG I PUT MIN 16 ±1 ● Transition Noise LTC1608 TYP MAX 16 ±4 16 ±0.5 0.7 ±2 0.5 ± 0.125 ± 0.25 ±0.25 % FSR ppm/°C ±0.125 ±0.25 ±0.25 ±15 LSB LSBRMS ±0.05 ±0.125 0.5 UNITS Bits 0.7 ± 0.05 ± 0.125 ● LTC1608A TYP MAX ±15 % % ppm/°C The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (Note 2) 4.75 ≤ VDD ≤ 5.25V, – 5.25 ≤ VSS ≤ – 4.75V, VSS ≤ (AIN–, AIN+) ≤ AVDD IIN Analog Input Leakage Current CS = High CIN Analog Input Capacitance Between Conversions During Conversions tACQ tAP tjitter Sample-and-Hold Acquisition Delay Time Jitter CMRR 2 MIN TYP MAX ±2.5 V ±1 ● UNITS µA 43 5 pF pF Sample-and-Hold Acquisition Time 380 ns Sample-and-Hold Acquisition Delay Time – 1.5 ns Analog Input Common Mode Rejection Ratio – 2.5V < (AIN– = AIN +) < 2.5V 5 psRMS 68 dB LTC1608 W U DY A IC ACCURACY TA = 25°C (Note 5) SYMBOL PARAMETER CONDITIONS MIN S/N Signal-to-Noise Ratio 5kHz Input Signal 100kHz Input Signal 90 88 dB dB S/(N + D) Signal-to-(Noise + Distortion) Ratio 5kHz Input Signal 100kHz Input Signal (Note 10) 90 84 dB dB THD Total Harmonic Distortion Up to 5th Harmonic 5kHz Input Signal 100kHz Input Signal – 100 – 91 dB dB SFDR Spurious Free Dynamic Range 100kHz Input Signal 94 dB IMD Intermodulation Distortion fIN1 = 29.37kHz, fIN2 = 32.446kHz – 88 Full Power Bandwidth Full Linear Bandwidth (S/(N + D) ≥ 84dB) U U U I TER AL REFERE CE CHARACTERISTICS PARAMETER TYP MAX UNITS dB 5 MHz 350 kHz TA = 25°C (Note 5) CONDITIONS MIN TYP MAX UNITS VREF Output Voltage IOUT = 0 2.475 2.500 2.515 VREF Output Tempco IOUT = 0 ±15 ppm/°C VREF Line Regulation 4.75 ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ – 4.75V 0.01 0.01 LSB/V LSB/V VREF Output Resistance 0 ≤ IOUT ≤ 1mA 7.5 kΩ REFCOMP Output Voltage IOUT = 0 V 4.375 V U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER VIH High Level Input Voltage VDD = 5.25V ● VIL Low Level Input Voltage VDD = 4.75V ● 0.8 V IIN Digital Input Current VIN = 0V to VDD ● ±1 0 µA CIN Digital Input Capacitance VOH High Level Output Voltage VOL Low Level Output Voltage CONDITIONS MIN VDD = 4.75V, IOUT = – 10µA VDD = 4.75V, IOUT = – 400µA ● VDD = 4.75V, IOUT = 160µA VDD = 4.75V, IOUT = 1.6mA ● VOUT = 0V to VDD, CS High ● ● TYP MAX 2.4 UNITS V 5 pF 4.5 V V 4.0 0.05 0.10 0.4 V V ±10 µA IOZ Hi-Z Output Leakage D15 to D0 COZ Hi-Z Output Capacitance D15 to D0 CS High (Note 11) ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VDD 10 mA 15 pF 3 LTC1608 U W POWER REQUIRE E TS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS VDD Positive Supply Voltage (Notes 12, 13) VSS Negative Supply Voltage (Note 12) IDD Positive Supply Current Nap Mode Sleep Mode CS = RD = 0V CS = 0V, SHDN = 0V CS = 5V, SHDN = 0V ● 22 1.5 1 35 2.4 100 mA mA µA ISS Negative Supply Current Nap Mode Sleep Mode CS = RD = 0V CS = 0V, SHDN = 0V CS = 5V, SHDN = 0V ● 32 1 1 49 100 100 mA µA µA PD Power Dissipation Nap Mode Sleep Mode CS = RD = 0V CS = 0V, SHDN = 0V CS = 5V, SHDN = 0V ● 270 7.5 0.01 420 12 1 mW mW mW WU TI I G CHARACTERISTICS MIN TYP MAX UNITS 4.75 5.25 V – 4.75 – 5.25 V The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN fSMPL(MAX) Maximum Sampling Frequency ● 500 600 tCONV Conversion Time ● 1.0 1.45 tACQ Acquisition Time (Notes 11, 14) TYP ● tACQ+CONV(MIN) Throughput Time (Acquisition + Conversion) 1.67 ● MAX UNITS kHz 1.8 µs 400 ns 2 µs t1 CS to RD Setup Time (Notes 11, 12, 15) ● 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 11, 12) ● 10 ns t3 SHDN↓ to CS↑ Setup Time (Notes 11, 12) ● 10 t4 SHDN↑ to CONVST↓ Wake-Up Time CS = Low (Note 12) t5 CONVST Low Time (Note 12) t6 CONVST to BUSY Delay CL = 25pF ns 400 ● 40 ns 36 80 ● t7 ns Data Ready Before BUSY↑ 60 ns ns ● 32 ns ns t8 Delay Between Conversions (Note 12) ● 200 ns t9 Wait Time RD↓ After BUSY↑ (Note 12) ● –5 ns t10 Data Access Time After RD↓ CL = 25pF 25 40 50 ns ns 45 60 75 ns ns 30 50 60 ns ns ● CL = 100pF (Note 11) ● t11 Bus Relinquish Time ● t12 RD Low Time (Note 12) ● t10 t13 CONVST High Time (Note 12) ● 40 t14 Aperture Delay of Sample-and-Hold Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, OGND and AGND wired together unless otherwise noted. 4 ns ns 2 ns Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. LTC1608 ELECTRICAL CHARACTERISTICS Note 4: When these pin voltages are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = – 5V, fSMPL = 500kHz, and t r = t f = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specification apply for a singleended AIN+ input with AIN– grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Typical RMS noise at the code transitions. Note 9: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion is measured at 100kHz. These results are used to calculate Signal-to-Nosie Plus Distortion (SINAD). Note 11: Guaranteed by design, not subject to test. Note 12: Recommended operating conditions. Note 13: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best performance ensure that CONVST returns high either within 250ns after conversion start or after BUSY rises. Note 14: The acquisition time would go up to 400ns and the conversion time would go up to 1.8µs. However, the throughput time (acquisition + conversion) is guaranteed by test to be 2µs max. Note 15: If RD↓ precedes CS↓, the output enable will be gated by CS↓. U W TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity vs Output Code Differential Nonlinearity vs Output Code 1.5 0.5 DNL (LSB) 0 –0.5 –1.0 –1.5 –2.0 –32768 –16384 0 CODE 16384 100 90 0.6 80 0.4 70 0.2 0 –0.2 20 –0.8 10 0 CODE 16384 Signal-to-Noise Ratio vs Input Frequency AMPLITUDE (dB BELOW THE FUNDAMENTAL) SIGNAL-TO-NOISE RATIO (dB) 80 70 60 50 40 30 20 10 10k 100k FREQUENCY (Hz) 1M 1608 G04 10k 100k FREQUENCY (Hz) Spurious-Free Dynamic Range vs Input Frequency 0 0 –10 –20 –30 –40 –50 –60 –70 –80 THD 3RD 2ND –90 –100 –110 1k 1M 1608 G03 Distortion vs Input Frequency 90 0 1k 0 1k 32767 1608 G02 1608 G01 100 VIN = –40dB 40 30 –16384 VIN = –20dB 50 –0.6 –1.0 –32768 32767 VIN = 0dB 60 –0.4 10k 100k INPUT FREQUENCY (Hz) 1M 1608 G05 SPURIOUS-FREE DYNAMIC RANGE (dB) INL (LSB) 1.0 1.0 0.8 SINAD (dB) 2.0 S/(N + D) vs Input Frequency and Amplitude –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1608 G06 5 LTC1608 U W TYPICAL PERFOR A CE CHARACTERISTICS Power Supply Feedthrough vs Ripple Frequency fSAMPLE = 500kHz fIN1 = 96.56kHz fIN2 = 99.98kHz AMPLITUDE (dB) –20 –40 –60 –80 AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) 0 0 –20 Input Common Mode Rejection vs Input Frequency 80 fSAMPLE = 500kHz VRIPPLE = 10mV COMMON MODE REJECTION (dB) Intermodulation Distortion –40 –60 –80 –100 –100 AVDD –120 –120 V SS –140 –140 0 50 100 150 200 250 FREQUENCY (kHz) 1k 10k 100k INPUT FREQUENCY (Hz) 1608 G07 1M 70 60 50 40 30 20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1608 G08 1M 1608 G14a U U U PI FU CTIO S AIN+ (Pin 1): Positive Analog Input. The ADC converts the difference voltage between AIN+ and AIN– with a differential range of ±2.5V. AIN+ has a ±2.5V input range when AIN– is grounded. AIN– (Pin 2): Negative Analog Input. Can be grounded, tied to a DC voltage or driven differentially with AIN+ . VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with 2.2µF tantalum in parallel with 0.1µF ceramic. REFCOMP (Pin 4): 4.375V (Nominal) Reference Compensation Pin. Bypass to AGND with 22µF tantalum in parallel with 0.1µF ceramic. This is not recommended for use as an external reference due to part-to-part output voltage variations and glitches that occur during the conversion. AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground plane. DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND with 10µF tantalum in parallel with 0.1µF ceramic. DGND (Pin 10): Digital Ground for Internal Logic. Tie to analog ground plane. D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15 is the Most Significant Bit. BUSY (Pin 27): The BUSY output shows the converter status. It is low when a conversion is in progress. Data is valid on the rising edge of BUSY. 6 OGND (Pin 28): Digital Ground for Output Drivers. OVDD (Pin 29): Digital Power Supply for Output Drivers. Bypass to OGND with 10µF tantalum in parallel with 0.1µF ceramic. RD (Pin 30): Read Input. A logic low enables the output drivers when CS is low. CONVST (Pin 31): Conversion Start Signal. This active low signal starts a conversion on its falling edge when CS is low. CS (Pin 32): The Chip Select Input. Must be low for the ADC to recognize CONVST and RD inputs. SHDN (Pin 33): Power Shutdown. Drive this pin low with CS low for nap mode. Drive this pin low with CS high for sleep mode. VSS (Pin 34): – 5V Negative Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic. AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic. AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic and connect this pin to Pin 35 with a 10Ω resistor. LTC1608 W FU CTIO AL BLOCK DIAGRA U 10µF U 2.2µF 10Ω + 3 VREF 5V 10µF + 36 AVDD 5V 35 9 AVDD 10µF + 10 DVDD DGND SHDN 33 4 REFCOMP + 7.5k 1.75X 4.375V CS 32 CONTROL LOGIC AND TIMING 2.5V REF µP CONTROL LINES CONVST 31 RD 30 BUSY 27 22µF OVDD 29 + 1 AIN+ DIFFERENTIAL ANALOG INPUT ±2.5V 2 AIN– OGND 28 + 16-BIT SAMPLING ADC – AGND AGND 6 5 OUTPUT BUFFERS B15 TO B0 AGND 7 D15 TO D0 16-BIT PARALLEL BUS 11 TO 26 AGND VSS 8 5V OR 3V 10µF 34 1608 BD + 10µF –5V TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay 5V 5V 1k DN 1k DN 1k DN 1k CL CL (A) Hi-Z TO VOH AND VOL TO VOH DN (B) Hi-Z TO VOL AND VOH TO VOL 1608 TC01 (A) VOH TO Hi-Z CL CL (B) VOL TO Hi-Z 1608 TC02 U W U U APPLICATIO S I FOR ATIO CONVERSION DETAILS The LTC1608 uses a successive approximation algorithm and internal sample-and-hold circuit to convert an analog signal to a 16-bit parallel output. The ADC is complete with a sample-and-hold, a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion, the successive approximation register (SAR) resets. Once a conversion cycle has begun, it cannot be restarted. During the conversion, the internal differential 16-bit capacitive DAC output is sequenced by the SAR from the Most Significant Bit (MSB) to the Least Significant Bit (LSB). Referring to Figure 1, the AIN+ and AIN– inputs are acquired during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a duration of 480ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the convert phase, the comparator zeroing switches open, putting the comparator into compare mode. The input switches connect the CSMPL capacitors to ground, transferring the differential analog input charge onto the summing junctions. This input charge is successively 7 LTC1608 U W U U APPLICATIO S I FOR ATIO 3V Input/Output Compatible CSMPL AIN+ SAMPLE The LTC1608 operates on ±5V supplies, which makes the device easy to interface to 5V digital systems. This device can also talk to 3V digital systems: the digital input pins (SHDN, CS, CONVST and RD) of the LTC1608 recognize 3V or 5V inputs. The LTC1608 has a dedicated output supply pin (OVDD) that controls the output swings of the digital output pins (D0 to D15, BUSY) and allows the part to talk to either 3V or 5V digital systems. The output is two’s complement binary. HOLD ZEROING SWITCHES CSMPL AIN– HOLD SAMPLE HOLD HOLD +CDAC + –CDAC COMP – +VDAC Power Shutdown –VDAC 16 SAR OUTPUT LATCHES • • • D15 D0 1608 F01 Figure 1. Simplified Block Diagram compared with the binary-weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN– input charges. The SAR contents (a 16-bit data word) which represent the difference of AIN+ and AIN– are loaded into the 16-bit output latches. DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. The LTC1608 provides two power shutdown modes, Nap and Sleep, to save power during inactive periods. The Nap mode reduces the power by 95% and leaves only the digital logic and reference powered up. The wake-up time from Nap to active is 200ns. In Sleep mode, all bias currents are shut down and only leakage current remains (about 1µA). Wake-up time from Sleep mode is much longer since the reference circuit must power up and settle. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 80ms with the recommended 22µF capacitor. Shutdown is controlled by Pin 33 (SHDN). The ADC is in shutdown when SHDN is low. The shutdown mode is selected with Pin 32 (CS). When SHDN is low, CS low selects nap and CS high selects sleep. SHDN t3 CS 1608 F02a Internal Clock The A/D converter has an internal clock that runs the A/D conversion. The internal clock is factory trimmed to achieve a typical conversion time of 1.45µs and a maximum conversion time of 1.8µs over the full temperature range. No external adjustments are required. The guaranteed maximum acquisition time is 400ns. In addition, a throughput time (acquisition + conversion) of 2µs and a minimum sampling rate of 500ksps are guaranteed. Figure 2a. Nap Mode to Sleep Mode Timing SHDN t4 CONVST 1608 F02b Figure 2b. SHDN to CONVST Wake-Up Timing 8 LTC1608 U W U U APPLICATIO S I FOR ATIO (e.g., CONVST low time >tCONV), accuracy is unaffected. For best results, keep t 5 less than 500ns or greater than tCONV. CS t2 CONVST Figures 5 through 9 show several different modes of operation. In modes 1a and 1b (Figures 5 and 6), CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. t1 RD 1608 F03 Figure 3. CS top CONVST Setup Timing CHANGE IN DNL (LSB) 4 In mode 2 (Figure 7) CS is tied low. The falling edge of CONVST signal starts the conversion. Data outputs are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared data bus. 3 2 tCONV tACQ 1 0 0 250 500 750 1000 1250 1500 1750 2000 CONVST LOW TIME, t5 (ns) 1608 F04 Figure 4. Change in DNL vs CONVST Low Time. Be Sure the CONVST Pulse Returns High Early in the Conversion or After the End of Conversion Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A falling edge applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. We recommend using a narrow logic low or narrow logic high CONVST pulse to start a conversion as shown in Figures 5 and 6. A narrow low or high CONVST pulse prevents the rising edge of the CONVST pulse from upsetting the critical bit decisions during the conversion time. Figure 4 shows the change of the differential nonlinearity error versus the low time of the CONVST pulse. As shown, if CONVST returns high early in the conversion (e.g., CONVST low time <300ns), accuracy is unaffected. Similarly, if CONVST returns high after the conversion is over In slow memory and ROM modes (Figures 8 and 9), CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the combined CONVST-RD signal. Conversions are started by the MPU or DSP (no external sample clock is needed). In slow memory mode, the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low, forcing the processor into a wait state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high, releasing the processor and the processor takes RD (= CONVST) back high and reads the new conversion data. In ROM mode, the processor takes RD (= CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion. DIFFERENTIAL ANALOG INPUTS Driving the Analog Inputs The differential analog inputs of the LTC1608 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN – input is grounded). The AIN+ and AIN – inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current 9 LTC1608 U W U U APPLICATIO S I FOR ATIO t CONV CS = RD = 0 t5 CONVST t6 t8 BUSY t7 DATA DATA (N + 1) D15 TO D0 DATA N D15 TO D0 DATA (N – 1) D15 TO D0 1608 F05 Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) tCONV CS = RD = 0 t8 t5 t13 CONVST t6 t6 BUSY t7 DATA (N – 1) D15 TO D0 DATA DATA N D15 TO D0 DATA (N + 1) D15 TO D0 1608 F06 Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) t13 tCONV t5 CS = 0 t8 CONVST t6 BUSY t9 t 12 t 11 RD t 10 DATA DATA N D15 TO D0 1608 F07 Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD 10 LTC1608 U W U U APPLICATIO S I FOR ATIO t8 t CONV CS = 0 RD = CONVST t6 t 11 BUSY t 10 t7 DATA (N – 1) D15 TO D0 DATA DATA N D15 TO D0 DATA N D15 TO D0 DATA (N + 1) D15 TO D0 1608 F08 Figure 8. Mode 2. Slow Memory Mode Timing t CONV CS = 0 t8 RD = CONVST t6 t 11 BUSY t 10 DATA DATA N D15 TO D0 DATA (N – 1) D15 TO D0 1608 F09 Figure 9. ROM Mode Timing Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of +1 and has a unity-gain bandwidth of 50MHz, then 10 ACQUISITION TIME (µs) spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1608 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 10). For minimum acquisition time with high source impedance, a buffer amplifier should be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 200ns for full throughput rate). 1 0.1 0.01 1 10 100 1k SOURCE RESISTANCE (Ω) 10k 1608 F10 Figure 10. tACQ vs Source Resistance the output impedance at 50MHz should be less than 100Ω. The second requirement is that the closed-loop bandwidth must be greater than 15MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. 11 LTC1608 U W U U APPLICATIO S I FOR ATIO The best choice for an op amp to drive the LTC1608 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1608. More detailed information is available in the Linear Technology databooks, the LinearViewTM CD-ROM and on our web site at: www.linear-tech. com. LT ® 1007: Low Noise Precision Amplifier. 2.7mA supply current, ±5V to ±15V supplies, gain bandwidth product 8MHz, DC applications. LT1097: Low Cost, Low Power Precision Amplifier. 300µA supply current, ±5V to ±15V supplies, gain bandwidth product 0.7MHz, DC applications. minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 11 shows a 3000pF capacitor from AIN+ to ground and a 100Ω source resistor to limit the input bandwidth to 530kHz. The 3000pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. ANALOG INPUT 100Ω 3000pF Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1608 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 15MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to 12 AIN– 4 VREF REFCOMP 22µF 5 AGND 1608 F11 LT1363: 50MHz Voltage Feedback Amplifier. 6.3mA supply current, good AC/DC specs. LT1469: Dual 90MHz, 22V/µs 16-Bit Accurate Operational Amplifier. 4.1mA supply current, excellent DC specs and very low distortion performance to 100kHz. 2 3 LT1360: 37MHz Voltage Feedback Amplifier. 3.8mA supply current, ±5V to ±15V supplies, good AC/DC specs. LT1468: 90MHz, 22V/µs 16-Bit Accurate Operational Amplifier. 3.8mA supply current, excellent DC specs and very low distortion performance to 100kHz. AIN+ LTC1608 LT1227: 140MHz Video Current Feedback Amplifier. 10mA supply current, ±5V to ±15V supplies, low noise and low distortion. LT1364/LT1365: Dual and Quad 50MHz Voltage Feedback Amplifiers. 6.3mA supply current per amplifier, good AC/DC specs. 1 Figure 11. RC Input Filter Input Range The ±2.5V input range of the LTC1608 is optimized for low noise and low distortion. Most op amps also perform well over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Some applications may require other input ranges. The LTC1608 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range. Internal Reference The LTC1608 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500V. It is connected internally to a reference amplifier and is available at VREF (Pin 3) (see Figure 12a). LinearView is a trademark of Linear Technology Corporation. LTC1608 U W U U APPLICATIO S I FOR ATIO 2.500V 4.375V R1 7.5k 3 VREF BANDGAP REFERENCE 1 ANALOG INPUT 2V TO 2.7V DIFFERENTIAL AIN+ 2 AIN– 2V TO 2.7V 3 LTC1608 4 REFCOMP REFERENCE AMP LTC1450 R2 12k 22µF 5 AGND 4 VREF REFCOMP 22µF R3 16k 5 AGND LTC1608 1608 F13 1608 F12a Figure 13. Driving VREF with a DAC Figure 12a. LTC1608 Reference Circuit Differential Inputs ANALOG INPUT VIN LT1019A-2.5 VOUT 1 AIN+ 2 AIN– 3 VREF LTC1608 4 + 22µF 0.1µF 5 REFCOMP AGND 1608 F12b Figure 12b. Using the LT1019-2.5 as an External Reference A 7.5k resistor is in series with the output so that it can be easily overdriven by an external reference or other circuitry (see Figure 12b). The reference amplifier gains the voltage at the VREF pin by 1.75 to create the required internal reference voltage. This provides buffering between the VREF pin and the high speed capacitive DAC. The reference amplifier compensation pin (REFCOMP, Pin 4) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 22µF or greater. Using a 0.1µF ceramic in parallel is recommended. The VREF pin can be driven with a DAC or other means shown in Figure 13. This is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC1608 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of 20ms should be allowed for after a reference adjustment. The LTC1608 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of AIN+ – AIN– independent of the common mode voltage (see Figure 15a). The common mode rejection holds up to extremely high frequencies (see Figure 14a). The only requirement is that both inputs can not exceed the AVDD or VSS power supply voltages. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar zero error (BZE) will vary. The change in BZE is typically less than 0.1% of the common mode voltage. Dynamic performance is also affected by the common mode voltage. THD will degrade as the inputs approach either power supply rail, from 96dB with a common mode of 0V to 86dB with a common mode of 2.5V or – 2.5V. 80 COMMON MODE REJECTION (dB) 5V 70 60 50 40 30 20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1608 G14a Figure 14a. CMRR vs Input Frequency 13 LTC1608 U W U U APPLICATIO S I FOR ATIO Differential inputs allow greater flexibility for accepting different input ranges. Figure 14b shows a circuit that converts a 0V to 5V analog input signal with only an additional buffer that is not in the signal path. ±2.5V 0V TO 5V + AIN+ 2 AIN– 3 011...110 OUTPUT CODE ANALOG INPUT 1 011...111 VREF 000...001 000...000 111...111 111...110 100...001 100...000 – LTC1608 FS – 1LSB – (FS – 1LSB) 4 INPUT VOLTAGE (AIN+ – AIN– ) REFCOMP 1608 F15a 22µF 5 AGND Figure 15a. LTC1608 Transfer Characteristics 1608 F14b ANALOG INPUT Figure 14b. Selectable 0V to 5V or ±2.5V Input Range Full-Scale and Offset Adjustment Figure 15a shows the ideal input/output characteristics for the LTC1608. The code transitions occur midway between successive integer LSB values (i.e., – FS + 0.5LSB, – FS + 1.5LSB, – FS + 2.5LSB,... FS – 1.5LSB, FS – 0.5LSB). The output is two’s complement binary with 1LSB = FS – (– FS)/65536 = 5V/65536 = 76.3µV. In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 15b shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN– input. For zero offset error, apply – 38µV (i.e., – 0.5LSB) at AIN+ and adjust the offset at the AIN– input by varying the output voltage of pin VOUTA from the LTC1662 until the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. For full-scale adjustment, an input voltage of 2.499886V (FS/2 – 1.5LSBs) is applied to AIN+ and the output voltage of pin VOUTB is adjusted until the output code flickers between 0111 1111 1111 1110 and 0111 1111 1111 1111. BOARD LAYOUT AND GROUNDING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1608, a printed circuit board with 14 5V LTC1662 R1 40.2k CS/LD VOUTA GND SCK VCC SDI VOUTB REF R3 1.5M OFFSET ADJ RANGE: ±0.125% FULL-SCALE ADJ RANGE: ±0.25% AIN+ 2 AIN– R2 100Ω 3 LTC1608 VREF + 2.2µF 0.1µF 1 80.6k 1% + 22µF 4 5 REFCOMP AGND –5V 1608 F15b Figure 15b. Offset and Full-Scale Adjust Circuit ground plane is required. Layout should ensure that digital and analog signal lines are separated as much as possible. Particular care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.The analog input should be screened by AGND. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 5 to Pin 8 (AGNDs), Pin 10 (ADC’s DGND) and all other analog grounds should be connected to this single analog ground point. The REFCOMP bypass capacitor and the DVDD bypass capacitor should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In LTC1608 U W U U APPLICATIO S I FOR ATIO EXAMPLE LAYOUT applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. Figures 17a, 17b, 17c, 17d and 17e show the schematic and layout of an evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground plane with a 4-layer printed circuit board. DC PERFORMANCE The noise of an ADC can be evaluated in two ways: signalto-noise raio (SNR) in frequency domain and histogram in time domain. The LTC1608 excels in both. Figure 19a demonstrates that the LTC1608 has an SNR of over 90dB in frequency domain. The noise in the time domain histogram is the transition noise associated with a high resolution ADC which can be measured with a fixed DC signal applied to the input of the ADC. The resulting output codes are collected over a large number of conversions. The shape of the distribution of codes will give an indication of the magnitude of the transition noise. In Figure 18, the distribution of output codes is shown for a DC input that has been digitized 4096 times. The distribution is Gaussian and the RMS code transition noise is about 0.66LSB. This corresponds to a noise level of 90.9dB relative to full scale. Adding to that the theoretical 98dB of quantization error for 16-bit ADC, the resultant corresponds to an SNR level of 90.1dB which correlates very well to the frequency domain measurements in Dynamic Performance section. The LTC1608 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN– leads will be rejected by the input CMRR. The AIN– input can be used as a ground sense for the AIN+ input; the LTC1608 will hold and convert the difference voltage between AIN+ and AIN– . The leads to AIN+ (Pin 1) and AIN– (Pin 2) should be kept as short as possible. In applications where this is not possible, the AIN+ and AIN– traces should be run side by side to equalize coupling. SUPPLY BYPASSING High quality, low series resistance ceramic, 10µF or 22µF bypass capacitors should be used at the VDD and REFCOMP pins as shown in Figure 16 and in the Typical Application on the first page of this data sheet. Surface mount ceramic capacitors such as Taiyo Yuden’s LMK325BJ106MN and LMK432BJ226MM provide excellent bypassing in a small board space. Alternatively, 10µF tantalum capacitors in parallel with 0.1µF ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. 1 ANALOG INPUT CIRCUITRY + – AIN+ AIN– 2 DYNAMIC PERFORMANCE The LTC1608 has excellent high speed sampling capability. Fast fourier transform (FFT) test techniques are used to test the ADC’s frequency response, distortions and DIGITAL SYSTEM LTC1608 VREF REFCOMP AGND 3 4 2.2µF 22µF VSS 5, 6, 7, 8 AVDD AVDD DVDD DGND OVDD OGND 34 36 35 9 10µF 10µF 10µF 10µF 10 29 28 10µF 1608 F16 Figure 16. Power Supply Grounding Practice 15 LTC1608 U W U U APPLICATIO S I FOR ATIO E5 3V + + C13 22µF E3 VREF C11 2.2µF 1 AIN+ 2 AIN– 3 C10 22µF 4 5 6 7 C9 5V 1µF 8 9 E4 GND E2 –5V OVDD 10 11 12 13 14 15 16 17 18 + E1 5V R6 JP1 10Ω C28 22µF C8 0.1µF OVDD C12 22µF U5 TC7SH08FUTE85L C7 E6 1µF GND 5V U1 LTC1608 AIN+ AVDD1 AIN– AVDD2 VREF VSS REFCOMP SHDN AGND CS AGND CONV AGND RD AGND OVDD DVDD OGND DGND BUSY D15 D0 D14 D1 D2 D13 D3 D12 D4 D11 D10 D5 D9 D6 D7 D8 36 R3 C6 10Ω 1µF 5V R5 10k JP3 R2 10k R4 10k C1 0.1µF 35 34 C5 1µF U2 MC74HC574ADT 20 1 OE VCC 19 2 D0 Q0 18 3 D1 Q1 17 4 D2 Q2 16 5 D3 Q3 15 6 D4 Q4 14 7 D5 Q5 13 8 D6 Q6 12 9 D7 Q7 11 10 GND CLK 33 32 31 30 29 C4 1µF OVDD 28 27 26 25 24 23 R17 10k C14 1000pF 2 + 1 19 2 6 C27 100pF – 8 8 + 1 4 –5V C17 10pF 7 9 U4A LT1469 C20 0.1µF R11 50Ω AIN (U1-1) R13 50Ω 10 OE VCC 6 D0 Q0 J4 R10 50Ω AIN– R16 10k 5 C19 1000pF U4B LT1469 + C24 100pF R9 402Ω 7 D1 Q1 17 19 21 23 25 27 31 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND CLK R12 50Ω C22 100pF 37 39 17 16 15 14 13 12 OVDD 11 JP2 U6 TC7SH04F C26 1000pF R14 50Ω 35 18 AIN– (U1-2) C23 100pF Figure 17a. LTC1608 Suggested Evaluation Circuit Schematic 16 15 19 C25 100pF C16 10pF – 13 20 R8 402Ω R15 100Ω 9 33 C15 10pF C18 10pF CLK MSB 11 U3 74HC574 5V AIN+ 7 OVDD 5 3 3 29 20 C21 0.1µF J1 CONN20 1 5 C3 0.1µF 21 4 R7 50Ω E7 GND OVDD 22 3 J3 J2 CONVERT START R1 51k LSB LTC1608 U W U U APPLICATIO S I FOR ATIO Figure 17b. Suggested Evaluation Circuit Board. Component Side Silkscreen and Signal Traces ANALOG GROUND PLANE DIGITAL GROUND PLANE Figure 17d. Suggested Evaluation Circuit Board. Inner Layer 1 Showing Separate Analog and Digital Ground Planes 2500 COUNT ANALOG GROUND PLANE DIGITAL GROUND PLANE Figure 17e. Suggested Evaluation Circuit Board. Inner Layer 2 Showing Separate Analog and Digital Ground Planes noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figures 19a and 19b show typical LTC1608 FFT plots. 2000 1500 1000 Signal-to-Noise Ratio 500 0 Figure 17c. Suggested Evaluation Circuit Board. Bottom Side Showing Signal Traces –5 –4 –3 –2 –1 0 1 CODE 2 3 4 5 1608 F18 Figure 18. Histogram for 4096 Conversions The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 19a shows a typical spectral content with a 500kHz sampling rate and a 3kHz input. 17 LTC1608 U W U U APPLICATIO S I FOR ATIO 0 fSAMPLE = 500kHz fIN = 2.807kHz SINAD = 88.9dB THD = –98dB EFFECTIVE BITS –40 –60 –80 –100 –120 98 15 92 14 86 13 80 12 74 11 68 10 62 9 56 8 –140 0 50 100 150 200 250 1k FREQUENCY (kHz) 10k 100k FREQUENCY (Hz) SINAD (dB) AMPLITUDE (dB) –20 16 50 1M 1608 F20 1608 F19a Figure 19a. This FFT of the LTC1608’s Conversion of a Full-Scale 3kHz Sine Wave Shows Outstanding Response with a Very Low Noise Floor When Sampling at 500ksps Figure 20. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency Total Harmonic Distortion 0 fSAMPLE = 500kHz fIN = 98.754kHz SINAD = 86.7dB THD = –92.6dB AMPLITUDE (dB) –20 –40 –60 –80 –100 THD = 20Log –120 –140 0 50 100 150 200 250 FREQUENCY (kHz) 1608 F19b Figure 19b. Even with Inputs at 100kHz, the LTC1608’s Dynamic Linearity Remains Robust The dynamic performance is excellent for input frequencies up to and beyond the Nyquist limit of 250kHz. Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOB = [S/(N + D) – 1.76]/6.02 where ENOB is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 500kHz, the LTC1608 maintains above 14 bits up to the Nyquist input frequency of 250kHz (refer to Figure 20). 18 Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: V22 + V32 + V 42 + ...Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs Input Frequency is shown in Figure 21. The LTC1608 has good distortion performance up to the Nyquist frequency and beyond. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include LTC1608 U W U U AMPLITUDE (dB BELOW THE FUNDAMENTAL) APPLICATIO S I FOR ATIO (fa ± fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: 0 –10 –20 –30 –40 ( –50 –70 –80 THD 3RD 2ND –90 –100 –110 1k 10k 100k INPUT FREQUENCY (Hz) Amplitude at (fa ± fb) Amplitude at fa Peak Harmonic or Spurious Noise 1M 1608 F21 Figure 21. Distortion vs Input Frequency The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth 0 fSAMPLE = 500kHz fIN1 = 96.56kHz fIN2 = 99.98kHz –20 AMPLITUDE (dB) ) IMD fa ± fb = 20Log –60 The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. –40 –60 The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 84dB (13.66 effective bits). The LTC1608 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. –80 –100 –120 –140 0 50 100 150 250 200 FREQUENCY (kHz) 1608 F22 Figure 22. Intermodulation Distortion Plot U PACKAGE DESCRIPTIO G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.67 – 12.93* (.499 – .509) 5.20 – 5.38** (.205 – .212) 1.73 – 1.99 (.068 – .078) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 0° – 8° .13 – .22 (.005 – .009) .55 – .95 (.022 – .037) .65 (.0256) BSC NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 7.65 – 7.90 (.301 – .311) .25 – .38 (.010 – .015) .05 – .21 (.002 – .008) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 G36 SSOP 0501 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC1608 U TYPICAL APPLICATIO Using the LTC1608 and Two LTC1391s as an 8-Channel Differential 16-Bit ADC System 5V 1 2 3 4 5 6 7 CH7 + 8 CH0 V+ CH1 D V CH2 DOUT CH4 DIN CH5 CS CH6 CLK CH7 GND 16 VREF 2 3 4 5 6 7 CH7 – 8 V+ CH1 D CH2 V– CH3 DOUT CH4 DIN CH5 CS CH6 CLK CH7 GND AVDD 10 9 DVDD AVDD DGND SHDN 33 –5V LTC1608 1µF + 13 4 REFCOMP 12 + 4.375V 22µF 11 7.5k 1.75X CONTROL LOGIC AND TIMING 2.5V REF CS 32 RD 30 BUSY 27 OVDD 29 + 1 AIN 9 – 2 AIN + OGND 28 + – 16-BIT SAMPLING ADC OUTPUT BUFFERS B15 TO B0 15 AGND AGND AGND 5 6 7 34 –5V 14 + + 12 CS 10 1608 TA03 10µF –5V DIN 11 11 TO 26 AGND VSS 8 5V OR 3V 10µF 16-BIT PARALLEL BUS D15 TO D0 3000pF 1µF 16 13 µP CONTROL LINES CONVST 31 10 LTC1391 CH0 + 35 15 5V 1 5V 10µF + 36 3000pF CH0 – 5V 10µF 10Ω 3 1µF – 14 CH3 10µF + + LTC1391 CH0+ 2.2µF CLK µP CONTROL LINES 9 RELATED PARTS SAMPLING ADCs PART NUMBER DESCRIPTION COMMENTS LTC1410 12-Bit, 1.25Msps, ±5V ADC 71.5dB SINAD at Nyquist, 150mW Dissipation LTC1415 12-Bit, 1.25Msps, Single 5V ADC 55mW Power Dissipation, 72dB SINAD LTC1418 14-Bit, 200ksps, Single 5V ADC 15mW, Serial/Parallel ±10V LTC1419 Low Power 14-Bit, 800ksps ADC True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation LTC1604 16-Bit, 333ksps, ±5V ADC 90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608 LTC1605 16-Bit, 100ksps, Single 5V ADC ±10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606 LTC1606 16-Bit, 250ksps, Single 5V ADC ±10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605 PART NUMBER DESCRIPTION COMMENTS LTC1595 16-Bit Serial Multiplying IOUT DAC in SO-8 ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade LTC1596 16-Bit Serial Multiplying IOUT DAC ±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade LTC1597/LTC1591 16-Bit/14-Bit Parallel, Multiplying DACs ±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors LTC1650 16-Bit Serial VOUT DAC Low Power, Low Gritch, 4-Quadrant Multiplication 20 Linear Technology Corporation DACs 1608f LT/TP 0601 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 2000