LTC2216/LTC2215 16-Bit, 80Msps/65Msps Low Noise ADC DESCRIPTION FEATURES n n n n n n n n n n n n n n n The LTC®2216/LTC2215 are 80Msps/65Msps sampling 16bit A/D converters designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 400MHz. The input range of the ADC is fixed at 2.75VP-P. Sample Rate: 80Msps/65Msps 81.5dBFS Noise Floor 100dB SFDR SFDR >95dB at 70MHz 85fsRMS Jitter 2.75VP-P Input Range 400MHz Full Power Bandwidth S/H Optional Internal Dither Optional Data Output Randomizer LVDS or CMOS Outputs Single 3.3V Supply Power Dissipation: 970mW/700mW Clock Duty Cycle Stabilizer Pin-Compatible with LTC2208, LTC2217 64-Pin (9mm × 9mm) QFN Package The LTC2216/LTC2215 are perfect for demanding communications applications, with AC performance that includes 81.5dBFS noise floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 85fsRMS allows undersampling of high input frequencies while maintaining excellent noise performance. Maximum DC specs include ±3.5LSB INL, ±1LSB DNL (no missing codes). The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. APPLICATIONS n n n n n n Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems ATE The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 3.3V LTC2216: 64k Point FFT, fIN = 4.9MHz, –1dBFS SENSE 2.2μF AIN+ 1.575V COMMON MODE BIAS VOLTAGE + ANALOG INPUT AIN– 16-BIT PIPELINED ADC CORE S/H AMP – OVDD INTERNAL ADC REFERENCE GENERATOR 0.5V TO 3.6V 1μF OUTPUT DRIVERS CORRECTION LOGIC AND SHIFT REGISTER OF CLKOUT D15 • • • D0 CMOS OR LVDS 1μF 1μF OGND CLOCK/DUTY CYCLE CONTROL 3.3V VDD GND 1μF 22165 TA01 ENC + ENC – SHDN DITH MODE LVDS RAND 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 AMPLITUDE (dBFS) VCM 0 10 20 30 FREQUENCY (MHz) 40 22165 TA01b ADC CONTROL INPUTS 22165f 1 LTC2216/LTC2215 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION OVDD = VDD (Notes 1 and 2) 64 NC 63 RAND 62 MODE 61 LVDS 60 OF+/OFA 59 OF–/DA15 58 D15+/DA14 57 D15–/DA13 56 D14+/DA12 55 D14–/DA11 54 D13+/DA10 53 D13–/DA9 52 D12+/DA8 51 D12–/DA7 50 OGND 49 OVDD TOP VIEW SENSE 1 GND 2 VCM 3 GND 4 VDD 5 VDD 6 GND 7 AIN+ 8 AIN– 9 GND 10 GND 11 ENC+ 12 ENC– 13 GND 14 VDD 15 VDD 16 48 D11+/DA6 47 D11–/DA5 46 D10+/DA4 45 D10–/DA3 44 D9+/DA2 43 D9–/DA1 42 D8+/DA0 41 D8–/CLKOUTA 40 CLKOUT+/CLKOUTB 39 CLKOUT –/OFB 38 D7+/DB15 37 D7–/DB14 36 D6+/DB13 35 D6–/DB12 34 D5+/DB11 33 D5–/DB10 65 VDD 17 GND 18 SHDN 19 DITH 20 –/DB0 21 D0 +/DB1 22 DO D1–/DB2 23 D1+/DB3 24 D2–/DB4 25 D2+/DB5 26 D3–/DB6 27 D3+/DB7 28 D4–/DB8 29 D4+/DB9 30 OGND 31 OVDD 32 Supply Voltage (VDD) ................................... –0.3V to 4V Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V Digital Output Ground Voltage (OGND)........ –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................–0.3V to (OVDD + 0.3V) Power Dissipation.............................................2000mW Operating Temperature Range LTC2215C/LTC2216C ............................... 0°C to 70°C LTC2215I/LTC2216I..............................–40°C to 85°C Storage Temperature Range ..................–65°C to 150°C TJMAX = 150°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2215CUP#PBF LTC2215CUP#TRPBF LTC2215UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2215IUP#PBF LTC2215IUP#TRPBF LTC2215UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C LTC2216CUP#PBF LTC2216CUP#TRPBF LTC2216UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2216IUP#PBF LTC2216IUP#TRPBF LTC2216UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2215CUP LTC2215CUP#TR LTC2215UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2215IUP LTC2215IUP#TR LTC2215UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C LTC2216CUP LTC2216CUP#TR LTC2216UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2216IUP LTC2216IUP#TR LTC2216UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 22165f 2 LTC2216/LTC2215 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Integral Linearity Error Differential Analog Input (Note 5) l ±1.2 ±3.5 LSB Differential Linearity Error Differential Analog Input l 0.16/–0.2 ±1 LSB Offset Error (Note 6) l ±1.5 ±8 mV Offset Drift ±4 Gain Error External Reference l μV/°C ±0.3 ±1 %FS Full-Scale Drift Internal Reference External Reference –65 ±12 ppm/°C ppm/°C Transition Noise External Reference 2 LSBRMS ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ – AIN–) 3.135V ≤ VDD ≤ 3.465V VIN, CM Analog Input Common Mode Differential Input (Note 7) l 1.2 IIN Analog Input Leakage Current 0V ≤ AIN+, AIN– ≤ VDD l –1 ISENSE SENSE Input Leakage Current 0V ≤ SENSE ≤ VDD l –3 IMODE MODE Pin Pull-Down Current to GND ILVDS LVDS Pin Pull-Down Current to GND CIN Analog Input Capacitance tAP Sample-and-Hold Acquisition Delay Time tJITTER Sample-and-Hold Aperture Jitter CMRR Analog Input Common Mode Rejection Ratio BW-3dB Full Power Bandwidth Sample Mode ENC+ < ENC– Hold Mode ENC+ > ENC– MIN TYP MAX 2.75 1.575 UNITS VP-P 1.8 V 1 μA 3 μA 10 μA 10 μA 9.1 1.8 pF pF 0.35 ns 85 fs RMS 1.2V < (AIN+ = AIN–) <1.8V 80 dB RS < 25Ω 400 MHz 22165f 3 LTC2216/LTC2215 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS with 2.75V range unless otherwise noted. (Note 4) LTC2215 SYMBOL PARAMETER SNR Signal-to-Noise Ratio CONDITIONS MIN TYP l 80.8 80.5 81.4 81 l 80 79.7 80.6 80.2 5MHz Input 15MHz Input, TA = 25°C 15MHz Input SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic IMD Spurious Free Dynamic Range at –25dBFS Dither “ON” Intermodulation Distortion dBFS 81.2 80.8 dBFS dBFS 81.1 dBFS 80 79.7 80.5 80.2 dBFS dBFS 5MHz Input 100 100 dBc 100 99 dBc dBc 95 dBc 97 97 dBc dBc 15MHz Input, TA = 25°C 15MHz Input l 88 88 100 96 88 88 91 l 85 84 96 95 85 84 140MHz Input 89 91 dBc 5MHz Input 105 105 dBc 105 dBc 105 dBc 103 dBc 15MHz Input l 95 105 94 105 l 94 104 93 140MHz Input 100 100 dBc 5MHz Input 81.5 81.3 dBc 81.1 80.7 dBFS dBFS 80.8 dBFS 80.4 80.1 dBFS dBFS 15MHz Input, TA = 25°C 15MHz Input 70MHz Input, TA = 25°C 70MHz Input SFDR 81.3 80.6 80.2 dBFS l 80.3 80.2 30MHz Input Spurious Free Dynamic Range at –25dBFS Dither “OFF” UNITS 79 70MHz Input SFDR MAX 79 30MHz Input S/(N+D) Signal-to-Noise Plus Distortion Ratio TYP 140MHz Input 70MHz Input, TA = 25°C 70MHz Input Spurious Free Dynamic Range 4th Harmonic or Higher MIN 81.2 30MHz Input SFDR MAX 81.5 30MHz Input, TA = 25°C 70MHz Input, TA = 25°C 70MHz Input LTC2216 81.2 80.8 80.2 80 80.9 l 79.3 79.2 80.3 80 79.6 79.4 140MHz Input 78.8 78.8 dBFS 5MHz Input 105 105 dBFS 15MHz Input 105 105 dBFS 30MHz Input 105 105 dBFS 70MHz Input 105 105 dBFS 140MHz Input 100 100 dBFS 5MHz Input 15MHz Input 115 l 100 115 100 115 dBFS 115 dBFS 30MHz Input 115 115 dBFS 70MHz Input 115 115 dBFS 140MHz Input 110 110 dBFS fIN1 = 14MHz, fIN2 = 21MHz, –7dBFS fIN1 = 67MHz, fIN2 = 74MHz, –7dBFS 100 96 100 97 dBc dBc 22165f 4 LTC2216/LTC2215 COMMON MODE BIAS CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS l MIN TYP MAX 1.475 1.575 1.675 UNITS VCM Output Voltage IOUT = 0 VCM Output Tempco IOUT = 0 ±60 ppm/°C V VCM Line Regulation 3.135V ≤ VDD ≤ 3.465V 2.4 mV/ V VCM Output Resistance | IOUT | ≤ 0.8mA 1.1 Ω DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Encode Inputs (ENC+, ENC–) VID Differential Input Voltage (Note 7) VICM Common Mode Input Voltage Internally Set Externally Set (Note 7) l 0.2 V 1.6 1.2 3 V V RIN Input Resistance (See Figure 2) 6 kΩ CIN Input Capacitance (Note 7) 3 pF VIH High Level Input Voltage VDD = 3.3V l VIL Low Level Input Voltage VDD = 3.3V l 0.8 V IIN Digital Input Current VIN = 0V to VDD l ±10 μA CIN Digital Input Capacitance (Note 7) Logic Inputs 2 V 1.5 pF 3.299 3.29 V V LOGIC OUTPUTS (CMOS MODE) OVDD = 3.3V VOH VOL High Level Output Voltage Low Level Output Voltage VDD = 3.3V VDD = 3.3V IO = –10μA IO = –200μA l IO = 160μA IO = 1.6mA l 3.1 0.01 0.10 0.4 V V ISOURCE Output Source Current VOUT = 0V –50 mA ISINK Output Sink Current VOUT = 3.3V 50 mA VOH High Level Output Voltage VDD = 3.3V IO = –200μA 2.49 V VOL Low Level Output Voltage VDD = 3.3V IO = 1.60mA 0.1 V VOH High Level Output Voltage VDD = 3.3V IO = –200μA 1.79 V VOL Low Level Output Voltage VDD = 3.3V IO = 1.60mA 0.1 V OVDD = 2.5V OVDD = 1.8V LOGIC OUTPUTS (LVDS MODE) STANDARD LVDS VOD Differential Output Voltage 100Ω Differential Load l 247 350 454 mV VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.2 1.375 V Differential Output Voltage 100Ω Differential Load l 125 175 250 mV 100Ω Differential Load l 1.125 1.2 1.375 Low Power LVDS VOD VOS Output Common Mode Voltage V 22165f 5 LTC2216/LTC2215 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4) LTC2215 SYMBOL PARAMETER CONDITIONS VDD Analog Supply Voltage (Note 8) PSHDN Shutdown Power SHDN = VDD l LTC2216 MIN TYP MAX MIN TYP MAX UNITS 3.135 3.3 3.465 3.135 3.3 3.465 V 17 17 mW Standard LVDS Output Mode OVDD Output Supply Voltage IVDD Analog Supply Current IOVDD PDIS (Note 8) l 3 3.3 3.6 l 217 Output Supply Current l Power Dissipation l 3 3.3 3.6 V 290 300 370 mA 75 90 75 90 mA 964 1254 1240 1518 mW 3.3 3.6 3.3 3.6 V Low Power LVDS Output Mode (Note 8) l OVDD Output Supply Voltage 3 3 IVDD Analog Supply Current l 215 290 298 370 mA IOVDD Output Supply Current l 42 50 42 50 mA PDIS Power Dissipation l 848 1122 1120 1386 mW CMOS Output Mode (Note 8) l OVDD Output Supply Voltage 0.5 3.6 IVDD Analog Supply Current l 212 290 PDIS Power Dissipation l 700 957 0.5 3.6 V 295 370 mA 970 1220 mW TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) LTC2215 SYMBOL PARAMETER CONDITIONS MIN fS Sampling Frequency (Note 8) l 1 7.31 5 TYP LTC2216 MAX MIN 65 1 7.692 7.692 500 500 5.94 4.06 TYP MAX UNITS 80 MHz 6.25 6.25 500 500 ns ns tL ENC Low Time Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) l l tH ENC High Time Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) l l 7.31 5 7.692 7.692 500 500 5.94 4.06 6.25 6.25 500 500 ns ns LVDS Output Mode (Standard and Low Power) tD ENC to DATA Delay (Note 7) l 1.3 2.5 3.8 1.3 2.5 3.8 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.5 3.8 1.3 2.5 3.8 ns (tC-tD) (Note 7) l –0.6 0 0.6 –0.6 0 0.6 ns tSKEW DATA to CLKOUT Skew tRISE Output Rise Time 0.5 0.5 ns tFALL Output Fall Time 0.5 0.5 ns 7 7 Data Latency Data Latency Cycles CMOS Output Mode tD ENC to DATA Delay (Note 7) l 1.3 2.7 4 1.3 2.7 4 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4 1.3 2.7 4 ns tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 –0.6 0 0.6 ns Data Latency Data Latency Full Rate CMOS Demuxed 7 7 7 7 Cycles Cycles 22165f 6 LTC2216/LTC2215 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND, with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 65MHz (LTC2215) or 80MHz (LTC2216), LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave with 1.6V common mode, input range = 2.75VP-P with differential drive, unless otherwise specified. Note 5: Integral nonlinearity is defined as the deviation of a code from a “best fit straight line” to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –1/2LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2’s complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. TIMING DIAGRAM LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels tAP ANALOG INPUT N+1 N+4 N N+3 N+2 tH tL ENC – ENC+ tD N–7 D0-D15, OF CLKOUT+ CLKOUT – N–6 N–5 N–4 N–3 tC 22165 TD01 22165f 7 LTC2216/LTC2215 TIMING DIAGRAMS Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+1 N+4 N N+3 N+2 tH tL – ENC ENC+ tD N–7 DA0-DA15, OFA N–6 N–5 N–4 N–3 tC CLKOUTA CLKOUTB HIGH IMPEDANCE DB0-DB15, OFB 22165 TD02 Demultiplexed CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+1 N N+4 N+2 N+3 tH tL ENC– ENC+ tD DA0-DA15, OFA N–8 N–6 N–4 N–7 N–5 N–3 tD DB0-DB15, OFB tC CLKOUTA CLKOUTB 22165 TD03 22165f 8 LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS LTC2216 Integral Nonlinearity (INL) vs Output Code, Dither “On“ LTC2216 Integral Nonlinearity (INL) vs Output Code, Dither “Off“ LTC2216 Differential Nonlinearity (DNL) vs Output Code 2.0 2.0 1.0 1.5 1.5 0.8 1.0 1.0 0.5 0.5 0.6 0.0 –0.5 –1.0 DNL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 0.4 0.0 –0.5 –1.0 0.2 0.0 –0.2 –0.4 –0.6 –1.5 –1.5 –2.0 –2.0 0 16384 32768 OUTPUT CODE 49152 65536 –0.8 –1.0 0 16384 32768 OUTPUT CODE 49152 22165 G01 12000 4000 2000 32771 OUTPUT CODE 32780 AMPLITUDE (dBFS) 6000 0 10 22165 G04 LTC2216 64k Point FFT, fIN = 15.1MHz, –20dBFS, Dither “Off” 20 30 FREQUENCY (MHz) 40 20 30 FREQUENCY (MHz) 40 22165 G07 20 30 FREQUENCY (MHz) 40 22165 G06 LTC2216 64k Point 2-Tone FFT, fIN = 14.25MHz and 21.5MHz, –7dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10 10 22165 G05 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 0 LTC2216 64k Point FFT, fIN = 15.1MHz, –20dBFS, Dither “On” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 65536 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 AMPLITUDE (dBFS) 8000 49152 LTC2216 64k Point FFT, fIN = 15.1MHz, –1dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 10000 16384 32768 OUTPUT CODE 22165 G03 LTC2216 64k Point FFT, fIN = 4.9MHz, –1dBFS 14000 0 32762 0 22165 G02 LTC2216 AC Grounded Input Histogram COUNT 65536 0 10 20 30 FREQUENCY (MHz) 40 22165 G08 0 10 20 30 FREQUENCY (MHz) 40 22165 G09 22165f 9 LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS LTC2216 64k Point 2-Tone FFT, fIN = 14.25MHz and 21.5MHz, –25dBFS, Dither “On” LTC2216 SFDR vs Input Level, fIN = 15.2MHz, Dither “Off” 140 140 130 130 120 120 110 110 100 90 80 70 60 90 80 70 60 50 50 40 40 10 20 30 FREQUENCY (MHz) 0 40 20 30 10 INPUT LEVEL (dBFS) 22165 G10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 LTC2216 64k Point FFT, fIN = 70.2MHz, –1dBFS 80 79 78 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 0 10 22165 G13 30 40 10 20 FREQUENCY (MHz) 30 40 22165 G16 10 20 30 40 22165 G15 LTC2216 SFDR vs Input Level, fIN = 70.5MHz, Dither “Off” LTC2216 64k Point FFT, fIN = 70.1MHz, –20dBFS, Dither “On” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 FREQUENCY (MHz) 22165 G14 140 130 120 110 SFDR (dBc AND dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 20 FREQUENCY (MHz) LTC2216 64k Point FFT, fIN = 70.1MHz, –20dBFS, Dither “Off” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 81 0 22165 G12 LTC2216 64k Point FFT, fIN = 28.7MHz, –1dBFS 82 0 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 40 22165 G11 LTC2216 SNR vs Input Level, fIN = 15.2MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 100 30 0 SNR (dBFS) SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) AMPLITUDE (dBFS) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 LTC2216 SFDR vs Input Level, fIN = 15.2MHz, Dither “On” 100 90 80 70 60 50 40 0 10 20 FREQUENCY (MHz) 30 40 22165 G17 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22165 G18 22165f 10 LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS LTC2216 SFDR vs Input Level, fIN = 70.5MHz, Dither “On” LTC2216 64k Point 2–Tone FFT, fIN = 67.2MHz and 74.4MHz, –7dBFS LTC2216 SNR vs Input Level, fIN = 70.5MHz 140 82 130 120 SFDR (dBc AND dBFS) AMPLITUDE (dBFS) 81 110 SNR (dBFS) 100 90 80 70 60 80 79 50 40 78 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22165 G19 20 FREQUENCY (MHz) 30 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 40 22165 G22 LTC2216 SFDR vs Input Level, fIN = 140.5MHz, Dither “Off” 140 140 130 130 120 120 110 110 90 80 70 60 20 30 0 40 40 22165 G24 LTC2216 SNR vs Input Level, fIN = 140.5MHz 82 81 80 70 60 40 40 22165 G25 20 30 FREQUENCY (MHz) 22165 G23 90 50 0 10 100 50 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 40 22165 G21 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 LTC2216 SFDR vs Input Level, fIN = 140.5MHz, Dither “On” SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) 10 FREQUENCY (MHz) 100 30 LTC2216 64k Point FFT, fIN = 140.1MHz, –20dBFS, Dither “On” AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10 20 FREQUENCY (MHz) LTC2216 64k Point FFT, fIN = 140.5MHz, –1dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 10 22165 G20 LTC2216 64k Point 2–Tone FFT, fIN = 67.2MHz and 74.4MHz, –25dBFS, Dither “On” 0 0 0 SNR (dBFS) 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 80 79 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22165 G26 78 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22165 G27 22165f 11 LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS LTC2216 SFDR (HD2 and HD3) vs Input Frequency LTC2216 SNR and SFDR vs Sample Rate, fIN = 5.2MHz LTC2216 SNR vs Input Frequency 110 82 110 81 105 LIMIT HD2 105 SNR (dBFS) AND SFDR (dBc) 80 95 HD3 SNR (dBFS) SFDR (dBc) 100 90 85 80 79 78 SFDR 77 75 100 95 90 85 SNR 80 75 70 76 70 0 50 100 150 200 INPUT FREQUENCY (MHz) 250 SFDR 0 50 100 150 200 INPUT FREQUENCY (MHz) 250 0 40 80 SAMPLE RATE (Msps) 22165 G29 22165 G28 LTC2216 SNR and SFDR vs Supply Voltage (VDD), fIN = 5.1MHz 120 22165 G30 LTC2216 IVDD vs Sample Rate and Supply Voltage, fIN = 5MHz, –1dBFS 110 375 LOWER LIMIT 105 325 95 UPPER LIMIT SFDR IVDD (mA) SNR (dBFS) AND SFDR (dBc) VDD = 3.465V 100 90 85 VDD = 3.135V 275 SNR 80 VDD = 3.3V 75 70 2.8 3.0 3.2 3.4 SUPPLY VOLTAGE (V) 225 3.6 0 40 80 120 SAMPLE RATE (Msps) 22165 G31 160 22165 G32 LTC2216 SFDR vs Analog Input Common Mode Voltage, 5MHz and 70MHz, –1dBFS LTC2216 SNR and SFDR vs Clock Duty Cycle, fIN = 5.2MHz 110 110 105 SFDR DCS ON 100 5MHz 95 SFDR DCS OFF 90 SFDR (dBc) SNR (dBFS) AND SFDR (dBc) 100 SNR DCS OFF 80 SNR DCS ON 90 85 80 70MHz 75 70 70 65 60 60 30 40 50 60 DUTY CYCLE (%) 70 22165 G33 0.5 0.75 1 1.25 1.5 1.75 2 ANALOG INPUT COMMON MODE VOLTAGE (V) 22165 G34 22165f 12 LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS LTC2215 Integral Nonlinearity (INL) vs Output Code, Dither “Off” LTC2215 Integral Nonlinearity (INL) vs Output Code, Dither “On” LTC2215 Differential Nonlinearity (DNL) vs Output Code 2.0 2.0 1.0 1.5 1.5 0.8 1.0 1.0 0.5 0.5 0.6 0.0 –0.5 –1.0 DNL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 0.4 0.0 –0.5 –1.0 0.2 0.0 –0.2 –0.4 –0.6 –1.5 –1.5 –2.0 –2.0 0 16384 32768 OUTPUT CODE 49152 65536 –0.8 –1.0 0 22165 G42 AMPLITUDE (dBFS) COUNT 10000 8000 6000 4000 2000 10 20 FREQUENCY (MHz) 0 22165 G48 10 20 FREQUENCY (MHz) LTC2215 64k Point 2–Tone FFT, fIN = 14.25MHz and 21.5MHz, –7dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 FREQUENCY (MHz) 30 22165 G47 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 30 LTC221564k Point FFT, fIN = 15.1MHz, –20dBFS, Dither “On” 30 65536 22165 G44 22165 G46 LTC2215 64k Point FFT, fIN = 15.1MHz, –20dBFS, Dither “Off” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 49152 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 32777 16384 32768 OUTPUT CODE LTC2215 64k Point FFT, fIN = 15.1MHz, –1dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 22165 G45 10 20 FREQUENCY (MHz) 0 AMPLITUDE (dBFS) 12000 0 65536 LTC2215 64k Point FFT, fIN = 4.9MHz, –1dBFS 14000 32768 OUTPUT CODE 49152 22165 G43 LTC2215 AC Grounded Input Histogram 0 3275 16384 32768 OUTPUT CODE 30 22165 G49 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 FREQUENCY (MHz) 30 22165 G50 22165f 13 LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS LTC2215 SFDR vs Input Level, fIN = 15.2MHz, Dither “Off” 10 20 FREQUENCY (MHz) 140 140 130 130 120 120 110 110 100 90 80 70 60 22165 G51 AMPLITUDE (dBFS) SNR (dBFS) 80 79 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 0 10 20 FREQUENCY (MHz) 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 30 22165 G57 10 20 30 FREQUENCY (MHz) 22165 G56 LTC2215 SFDR vs Input Level, fIN = 70.5MHz, Dither “Off” 140 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 130 120 110 SFDR (dBc AND dBFS) AMPLITUDE (dBFS) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 LTC2215 64k Point FFT, fIN = 70.2MHz, –1dBFS 0 30 LTC221564k Point FFT, fIN = 70.1MHz, –20dBFS, Dither “On” LTC2215 64k Point FFT, fIN = 70.1MHz, –20dBFS, Dither “Off” 0 22165 G53 22165 G55 22165 G54 AMPLITUDE (dBFS) 60 40 LTC2215 64k Point FFT, fIN = 28.7MHz, –1dBFS 81 10 20 FREQUENCY (MHz) 70 22165 G52 82 0 80 50 LTC2215 SNR vs Input Level, fIN = 15.2MHz 78 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 90 40 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 30 100 50 AMPLITUDE (dBFS) 0 LTC2215 SFDR vs Input Level, fIN = 15.2MHz, Dither “On” SFDR (dBc AND dBFS) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 SFDR (dBc AND dBFS) AMPLITUDE (dBFS) LTC2215 64k Point 2–Tone FFT, fIN = 14.25MHz and 21.5MHz, –25dBFS, Dither “On” 100 90 80 70 60 50 40 0 10 20 FREQUENCY (MHz) 30 22165 G58 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22165 G59 22165f 14 LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS LTC2215 SFDR vs Input Level, fIN = 70.5MHz, Dither “On” LTC2215 SNR vs Input Level, fIN = 70.5MHz LTC2215 64k Point 2–Tone FFT, fIN = 67.2MHz and 74.4MHz, –7dBFS 82 140 130 120 100 SNR (dBFS) SFDR (dBc AND dBFS) AMPLITUDE (dBFS) 81 110 90 80 70 60 80 79 50 40 78 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 10 20 FREQUENCY (MHz) 10 20 FREQUENCY (MHz) 30 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 22165 G64 LTC2215 SFDR vs Input Level, fIN = 140.5MHz, Dither “Off” 140 140 130 130 120 120 110 110 90 80 70 60 LTC2215 SNR vs Input Level, fIN = 140.5MHz 82 81 90 80 70 60 50 40 40 22165 G66 30 100 50 0 10 20 FREQUENCY (MHz) 22165 G65 LTC2215 SFDR vs Input Level, fIN = 140.5MHz, Dither “On” SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) AMPLITUDE (dBFS) 0 22165 G63 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) LTC221564k Point FFT, fIN = 140.1MHz, –20dBFS, Dither “On” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 30 100 30 22165 G62 LTC2215 64k Point FFT, fIN = 140.5MHz, –1dBFS AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2215 64k Point 2–Tone FFT, fIN = 67.2MHz and 74.4MHz, –25dBFS, Dither “On” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 10 20 FREQUENCY (MHz) 22165 G61 22165 G60 0 0 0 SNR (dBFS) 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 80 79 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22165 G67 78 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22165 G68 22165f 15 LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS LTC2215 SFDR (HD2 and HD3) vs Input Frequency 110 82 110 81 105 LIMIT 105 SNR (dBFS) AND SFDR (dBc) HD3 100 80 95 SNR (dBFS) SFDR (dBc) LTC2215 SNR and SFDR vs Sample Rate, fIN = 5.2MHz LTC2215 SNR vs Input Frequency HD2 90 SFDR 85 79 78 80 77 75 0 50 100 150 200 INPUT FREQUENCY (MHz) 0 250 100 95 90 85 SNR 80 75 70 76 70 SFDR 50 100 150 200 INPUT FREQUENCY (MHz) 250 0 40 80 SAMPLE RATE (Msps) 22165 G70 22165 G69 LTC2215 SNR and SFDR vs Supply Voltage (VDD), fIN = 5.1MHz 120 22165 G71 LTC2215 IVDD vs Sample Rate and Supply Voltage, fIN = 5MHz, –1dBFS 275 110 LOWER LIMIT 250 100 225 95 UPPER LIMIT SFDR 90 IVDD (mA) SNR (dBFS) AND SFDR (dBc) 105 85 VDD = 3.465V VDD = 3.135V 200 175 SNR VDD = 3.3V 80 150 75 70 2.8 125 3.0 3.2 3.4 SUPPLY VOLTAGE (V) 0 3.6 40 80 120 SAMPLE RATE (Msps) 22165 G73 22165 G72 LTC2215 SFDR vs Analog Input Common Mode Voltage, 5MHz and 70MHz, –1dBFS LTC2215 SNR and SFDR vs Clock Duty Cycle, fIN = 5.2MHz 110 110 105 SFDR DCS ON 100 100 SFDR DCS OFF 90 5MHz 95 SFDR (dBc) SNR (dBFS) AND SFDR (dBc) 160 SNR DCS ON 80 SNR DCS OFF 90 85 70MHz 80 75 70 70 65 60 60 30 40 50 60 DUTY CYCLE (%) 70 22165 G74 0.5 0.75 1 1.25 1.5 1.75 2 ANALOG INPUT COMMON MODE VOLTAGE (V) 22165 G75 22165f 16 LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS LTC2216/LTC2215 Input Offset Voltage vs Temperature, Internal Reference, 5 Units LTC2216/LTC2215 Normalized Full-Scale vs Temperature, External Reference, 5 Units 5 1.005 1.004 4 1.004 1.003 3 1.003 1.002 1.001 1 0.999 0.998 0.997 NORMALIZED FULL SCALE 1.005 OFFSET VOLTAGE (mV) NORMALIZED FULL SCALE LTC2216/LTC2215 Normalized Full-Scale vs Temperature, Internal Reference, 5 Units 2 1 0 –1 –2 –3 0.996 –20 0 20 40 60 –5 –40 80 TEMPERATURE (°C) 1.001 1 0.999 0.998 0.997 0.996 –4 0.995 –40 1.002 –20 0 20 40 60 80 0.995 –40 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) 22165 G76 –20 22165 G78 22165 G77 0.5 0.5 4 0.4 0.4 3 0.3 2 1 0 –1 –2 FULL–SCALE ERROR (%) 5 FULL–SCALE ERROR (%) OFFSET VOLTAGE (mV) LTC2216/LTC2215 Full–Scale Settling After Wake-Up from Shutdown or Starting Encode Clock LTC2216/LTC2215 Mid–Scale Settling After Wake-Up from Shutdown or Starting Encode Clock LTC2216/LTC2215 Input Offset Voltage vs Temperature, External Reference, 5 Units WAKE-UP 0.2 0.1 0.0 CLOCK START –0.1 –0.2 0.3 0.2 0.1 0.0 –0.1 –0.3 –0.3 –4 –0.4 –0.4 –5 –40 –0.5 0 20 40 TEMPERATURE (°C) 60 80 22165 G79 CLOCK START –0.2 –3 –20 WAKE-UP –0.5 0 300 600 900 1200 1500 TIME AFTER WAKE-UP OR CLOCK START (μs) 22165 G80 0 400 800 1200 1600 2000 TIME AFTER WAKE-UP OR CLOCK START (μs) 22165 G81 22165f 17 LTC2216/LTC2215 PIN FUNCTIONS For CMOS Mode. Full Rate or Demultiplexed SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full-scale ADC range of 2.75V. GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground. VCM (Pin 3): 1.575V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2μF. Ceramic chip capacitors are recommended. VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. Bypass to GND with 1μF ceramic chip capacitors. AIN+ (Pin 8): Positive Differential Analog Input. AIN– (Pin 9): Negative Differential Analog Input. ENC+ (Pin 12): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2kΩ resistor. Output data can be latched on the rising edge of ENC+. ENC– (Pin 13): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC –. Internally biased to 1.6V through a 6.2kΩ resistor. Bypass to ground with a 0.1μF capacitor for a single-ended Encode signal. SHDN (Pin 19): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. DITH (Pin 20): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. DB0-DB15 (Pins 21-30 and 33-38): Digital Outputs, B Bus. DB15 is the MSB. Active in demultiplexed mode. The B bus is in high impedance state in full rate CMOS mode. OGND (Pins 31 and 50): Output Driver Ground. OVDD (Pins 32 and 49): Positive Supply for the Output Drivers. Bypass to ground with 1μF capacitor. OFB (Pin 39): Over/Under Flow Digital Output for the B Bus. OFB is high when an over or under flow has occurred on the B bus. At high impedance state in full rate CMOS mode. CLKOUTB (Pin 40): Data Valid Output. CLKOUTB will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the falling edge of CLKOUTB. CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the rising edge of CLKOUTA. DA0-DA15 (Pins 42-48 and 51-59): Digital Outputs, A Bus. DA15 is the MSB. Output bus for full rate CMOS mode and demultiplexed mode. OFA (Pin 60): Over/Under Flow Digital Output for the A Bus. OFA is high when an over or under flow has occurred on the A bus. LVDS (Pin 61): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode. MODE (Pin 62): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2’s complement output format and disables the clock duty cycle stabilizer. RAND (Pin 63): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interference. NC (Pin 64): Not Connected Internally. For pin compatibility with the LTC2208 this pin should be connected to GND or VDD as required. Otherwise no connection. GND (Exposed Pad): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground. 22165f 18 LTC2216/LTC2215 PIN FUNCTIONS For LVDS Mode. STANDARD or LOW POWER OGND (Pins 31 and 50): Output Driver Ground. SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full-scale ADC range of 2.75V. OVDD (Pins 32 and 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1μF capacitor. GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground. VCM (Pin 3): 1.575V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2μF. Ceramic chip capacitors are recommended. VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. Bypass to GND with 1μF ceramic chip capacitors. AIN + (Pin 8): Positive Differential Analog Input. AIN – (Pin 9): Negative Differential Analog Input. ENC + (Pin 12): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2kΩ resistor. Output data can be latched on the rising edge of ENC+. ENC – (Pin 13): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC –. Internally biased to 1.6V through a 6.2kΩ resistor. Bypass to ground with a 0.1μF capacitor for a single-ended Encode signal. SHDN (Pin 19): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are set in high impedance state. DITH (Pin 20): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of the data sheet for details on dither operation. D0–/D0+ to D15–/D15+ (Pins 21-30, 33-38, 41-48 and 51-58): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D15+/D15– is the MSB. CLKOUT–/CLKOUT + (Pins 39 and 40): LVDS Data Valid 0utput. Latch data on the rising edge of CLKOUT +, falling edge of CLKOUT –. OF–/OF+ (Pins 59 and 60): Over/Under Flow Digital Output OF is high when an over or under flow has occurred. LVDS (Pin 61): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode. MODE (Pin 62): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2’s complement output format and disables the clock duty cycle stabilizer. RAND (Pin 63): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. The mode of operation reduces the effects of digital output interference. NC (Pin 64): Not Connected Internally. For pin compatibility with the LTC2208 this pin should be connected to GND or VDD as required. Otherwise no connection. GND (Exposed Pad Pin 65): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground. 22165f 19 LTC2216/LTC2215 BLOCK DIAGRAM AIN+ AIN– VDD INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND DITHER SIGNAL GENERATOR CORRECTION LOGIC AND SHIFT REGISTER ADC CLOCKS RANGE SELECT OVDD SENSE PGA VCM BUFFER ADC REFERENCE DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER CONTROL LOGIC OUTPUT DRIVERS • • • VOLTAGE REFERENCE OGND ENC+ ENC– SHDN RAND M0DE LVDS CLKOUT+ CLKOUT– OF+ OF– D15+ D15– D0+ D0– 22165 F01 DITH Figure 1. Functional Block Diagram 22165f 20 LTC2216/LTC2215 OPERATION DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency (Nyquist Frequency). Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full-scale and expressed in dBFS. Full Power Bandwidth Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (Nyquist Frequency). THD is expressed as: THD = − 20Log (( ) V2 2 + V3 2 + V4 2 + ...VN 2 / V1 ) where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. The Full Power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB from a full-scale input signal. Aperture Delay Time The time from when a rising ENC + equals the ENC– voltage to the instant that the input signal is held by the sampleand-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal-to-noise ratio term due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) This formula states SNR due to jitter alone at any amplitude in terms of dBc. 22165f 21 LTC2216/LTC2215 APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2216/LTC2215 are CMOS pipelined multistep converters with a low noise front-end. As shown in Figure 1, these converters have five pipelined ADC stages; a sampled analog input will result in a digitized value seven cycles later (see the Timing Diagram section). The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. The encode input is also differential for improved common mode noise immunity. The LTC2216/LTC2215 have two phases of operation, determined by the state of the differential ENC+/ENC – input pins. For brevity, the text will refer to ENC+ greater than ENC – as ENC high and ENC+ less than ENC – as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the voltage on the sample capacitors is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H amplifier during the high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2216/ LTC2215 CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the NMOS transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions for high to low, the inputs are reconnected to LTC2216/LTC2215 VDD RPARASITIC 3Ω RON 20Ω CSAMPLE 7.3pF AIN+ CPARASITIC 1.8pF VDD RPARASITIC 3Ω RON 20Ω CSAMPLE 7.3pF AIN– CPARASITIC 1.8pF VDD 1.6V 6k ENC+ ENC– 6k 1.6V 22165 F02 Figure 2. Equivalent Input Circuit 22165f 22 LTC2216/LTC2215 APPLICATIONS INFORMATION the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input should swing ±0.6875V for the 2.75V range, around a common mode voltage of 1.575V. The VCM output pin (Pin 3) is designed to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with 2.2μF or greater. Input Drive Impedance As with all high performance, high speed ADCs the dynamic performance of the LTC2216/LTC2215 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC the sample and hold circuit will connect the sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2 • fENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. INPUT DRIVE CIRCUITS Input Filtering A first-order RC low-pass filter at the input of the ADC can serve two functions: limit the noise from input circuitry and provide isolation from ADC S/H switching. The LTC2216/LTC2215 have a very broadband S/H circuit, DC to 400MHz. This can be used in a wide range of applications, therefore, it is not possible to provide a single recommended RC filter. Figures 3 and 4 show two examples of input RC filtering for two ranges of input frequencies. In general it is desirable to make the capacitors as large as can be tolerated–this will help suppress random noise as well as noise coupled from the digital circuitry. The LTC2216/LTC2215 do not require any input filter to achieve data sheet specifications; however, no filtering will put more stringent noise requirements on the input drive circuitry. Transformer Coupled Circuits Figure 3 shows the LTC2216/LTC2215 being driven by an RF transformer with a center-tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the ADC. Source impedance greater than 50Ω can reduce the input bandwidth and increase VCM 2.2μF 5Ω 5Ω AIN+ 10Ω T1 8.2pF 35Ω 0.1μF 10Ω T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2μF 35Ω LTC2216/ LTC2215 8.2pF 5Ω AIN– 8.2pF 22165 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer. Recommended for Input Frequencies from 5MHz to 100MHz 22165f 23 LTC2216/LTC2215 APPLICATIONS INFORMATION high frequency distortion. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Center-tapped transformers provide a convenient means of DC biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. Figure 4 shows transformer coupling using a transmission line balun transformer. This type of transformer has much better high-frequency response and balance than flux coupled center-tap transformers. Coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.575V. VCM 0.1μF ANALOG INPUT 5Ω 2.2μF 10Ω 5Ω AIN+ 25Ω 0.1μF 0.1μF T1 1:1 LTC2216/ LTC2215 4.7pF 4.7pF 25Ω 10Ω T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2μF 5Ω AIN– 4.7pF 22165 F04 Figure 4. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 100MHz to 250MHz VCM HIGH SPEED DIFFERENTIAL AMPLIFIER ANALOG INPUT + CM – 2.2μF LTC2216/ LTC2215 12pF + – AIN+ 25Ω AIN– 25Ω AMPLIFIER = LTC6600-20, LTC1993, ETC. 12pF 22165 F05 Figure 5. DC Coupled Input with Differential Amplifier Reference Operation Figure 6 shows the LTC2216/LTC2215 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. The LTC2216/LTC2215 has three modes of reference operation: Internal Reference, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to VDD. To use an external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in a full-scale range of 2.75VP-P. A 1.575V output, VCM, is provided for a common mode bias for input drive circuitry. An external bypass capacitor is required for the VCM output. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference; which will not be stable without this capacitor. The minimum value required for stability is 2.2μF. Direct Coupled Circuits Figure 5 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop amplifier will degrade the ADC SFDR at high input frequencies. Additionally, wideband op amps or differential amplifiers tend to have high noise. As a result, the SNR will be degraded unless the noise bandwidth is limited prior to the ADC input. TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT AN EXTERNAL 2.5V REFERENCE OR INPUT AN EXTERNAL 1.25V REFERENCE RANGE SELECT AND GAIN CONTROL INTERNAL ADC REFERENCE SENSE PGA 2.5V BANDGAP REFERENCE VCM BUFFER 1.575V 2.2μF 22165 F06 Figure 6. Reference Circuit 22165f 24 LTC2216/LTC2215 APPLICATIONS INFORMATION The internal programmable gain amplifier provides the internal reference voltage for the ADC. This amplifier has very stringent settling requirements and therefore is not accessible for external use. The SENSE pin can be driven ±5% around the nominal 2.5V or 1.25V external reference inputs. This adjustment range can be used to trim the ADC gain error or other system gain errors. When selecting the internal reference, the SENSE pin should be tied to VDD as close to the converter as possible. If the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1μF ceramic capacitor. 3. If the ADC is clocked with a fixed-frequency sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to VDD. Each input may be driven from ground to VDD for single-ended drive. LTC2216/LTC2215 TO INTERNAL ADC CLOCK DRIVERS VCM 1.575V VDD 1.6V 2.2μF 3.3V 1μF 2 LTC1461-2.5 4 6 SENSE VDD LTC2216/ LTC2215 6k ENC+ 2.2μF 1.6V VDD 6k 22165 F07 ENC– Figure 7. A 2.75V Range ADC with an External 2.5V Reference 22165 F08 Driving the Encode Inputs The noise performance of the LTC2216/LTC2215 can depend on the encode signal quality as much as on the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies), take the following into consideration: Figure 8. Equivalent Encode Input Circuit 0.1μF ENC+ T1 50Ω 100Ω 8.2pF 0.1μF LTC2216/ LTC2215 50Ω 0.1μF ENC– 22165 F09 T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 9. Balun-Driven Encode 1. Differential drive should be used. 2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the amplitude. 22165f 25 LTC2216/LTC2215 APPLICATIONS INFORMATION use the clock duty cycle stabilizer, the MODE pin must be connected to 1/3VDD or 2/3VDD using external resistors. ENC+ VTHRESHOLD = 1.6V ENC– 1.6V LTC2216/ LTC2215 0.1μF 22165 F10 Figure 10. Single-Ended ENC Drive, Not Recommended for Low Jitter The lower limit of the LTC2216/LTC2215 sample rate is determined by droop affecting the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for both the LTC2215 and LTC2216 is 1Msps. 3.3V MC100LVELT22 DIGITAL OUTPUTS 3.3V 130Ω Q0 130Ω ENC+ D0 ENC– LTC2216/ LTC2215 Q0 83Ω 83Ω 22165 F11 Figure 11. ENC Drive Using a CMOS to PECL Translator Maximum and Minimum Encode Rates The maximum encode rate for the LTC2216 is 80Msps, while the maximum encode rate for the LTC2215 is 65Msps. For the ADCs to operate properly the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 5.94ns for the LTC2216 internal circuitry to have enough settling time for proper operation. For the LTC2215, each half cycle must be at least 7.31ns. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended ENCODE signal asymmetric rise and fall times can result in duty cycles that are far from 50%. An optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. This circuit uses the rising edge of ENC pin to sample the analog input. The falling edge of ENC is ignored and an internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To Digital Output Modes The LTC2216/LTC2215 can operate in four digital output modes: standard LVDS, low power LVDS, full rate CMOS, and demultiplexed CMOS. The LVDS pin selects the mode of operation. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be used to set the 1/3VDD and 2/3VDD logic levels. Table 1 shows the logic states for the LVDS pin. Table 1. LVDS Pin Function LVDS DIGITAL OUTPUT MODE 0V(GND) Full-Rate CMOS 1/3VDD Demultiplexed CMOS 2/3VDD Low Power LVDS VDD LVDS Digital Output Buffers (CMOS Modes) Figure 11 shows an equivalent circuit for a single output buffer in CMOS Mode, Full-Rate or Demultiplexed. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and eliminates the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2216/LTC2215 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as the 22165f 26 LTC2216/LTC2215 APPLICATIONS INFORMATION resistor, even if the signal is not used (such as OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length. ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used, but is not required since the ADC has a series resistor of 43Ω on-chip. Lower OVDD voltages will also help reduce interference from the digital outputs. OVDD LTC2216/LTC2215 VDD In Low Power LVDS Mode 1.75mA is steered between the differential outputs, resulting in ±175mV at the LVDS receiver’s 100Ω termination resistor. The output common mode voltage is 1.20V, the same as standard LVDS Mode. 0.5V TO 3.6V VDD 0.1μF OVDD DATA FROM LATCH PREDRIVER LOGIC 43Ω Data Format TYPICAL DATA OUTPUT The LTC2216/LTC2215 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be user to set the 1/3VDD and 2/3VDD logic levels. Table 2 shows the logic states for the MODE pin. OGND 22165 F12 Figure 12. Equivalent Circuit for a Digital Output Buffer Digital Output Buffers (LVDS Modes) Table 2. MODE Pin Function Figure 13 shows an equivalent circuit for an LVDS output pair. A 3.5mA current is steered from OUT+ to OUT– or vice versa, which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.20V. For proper operation each LVDS output pair must be terminated with an external 100Ω termination MODE OUTPUT FORMAT CLOCK DUTY CYCLE STABILIZER Offset Binary Off 0V(GND) 1/3VDD Offset Binary On 2/3VDD 2’s Complement On VDD 2’s Complement Off LTC2216/LTC2215 OVDD 3.3V 3.5mA 0.1μF VDD VDD OVDD 43Ω DATA FROM LATCH PREDRIVER LOGIC 10k 10k OVDD 100Ω LVDS RECEIVER 43Ω 1.20V + – OGND 22165 F13 Figure 13. Equivalent Output Buffer in LVDS Mode 22165f 27 LTC2216/LTC2215 APPLICATIONS INFORMATION Overflow Bit An overflow output bit (OF) indicates when the converter is over-ranged or under-ranged. In CMOS mode, a logic high on the OFA pin indicates an overflow or underflow on the A data bus, while a logic high on the OFB pin indicates an overflow on the B data bus. In LVDS mode, a differential logic high on OF+/OF– pins indicates an overflow or underflow. are not affected. The output Randomizer function is active when the RAND pin is high. LTC2216/LTC2215 CLKOUT OF Output Clock In demultiplexed CMOS mode CLKOUTA and CLKOUTB will toggle at 1/2 the frequency of the encode signal. Both the A bus and the B bus may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB. Digital Output Randomizer Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling, or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude. The digital output is “Randomized” by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT output OF D15 The ADC has a delayed version of the encode input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. In both CMOS modes, A bus data will be updated as CLKOUTA falls and CLKOUTB rises. In demultiplexed CMOS mode the B bus data will be updated as CLKOUTA falls and CLKOUTB rises. In Full Rate CMOS Mode, only the A data bus is active; data may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB. CLKOUT D15D0 D14 D2 D14D0 • • • D2D0 D1 RAND = HIGH, SCRAMBLE ENABLED D1D0 RAND D0 D0 22165 F14 Figure 14. Functional Equivalent of Digital Output Randomizer Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. In CMOS mode OVDD can be powered with any logic voltage up to the 3.6V. OGND can be powered with any voltage from ground up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. In LVDS Mode, OVDD should be connected to a 3.3V supply and OGND should be connected to GND. 22165f 28 LTC2216/LTC2215 APPLICATIONS INFORMATION Internal Dither PC BOARD FPGA The LTC2216/LTC2215 is a 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels. CLKOUT OF D15D0 D15 D14D0 As shown in Figure 16, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in typically less than 0.5dB elevation in the noise floor of the ADC, as compared to the noise floor with dither off when a suitable input termination is provided (see Demo Board schematic DC996B). D14 LTC2216/ LTC2215 • • • D2D0 D2 D1D0 D1 D0 D0 22165 F15 Figure 15. Descrambling a Scrambled Digital Output LTC2216/LTC2215 AIN+ ANALOG INPUT AIN– 16-BIT PIPELINED ADC CORE S/H AMP CLOCK/DUTY CYCLE CONTROL PRECISION DAC DIGITAL SUMMATION CLKOUT OF D15 • • • D0 OUTPUT DRIVERS MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR 22165 F16 ENC + ENC – DITH DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF Figure 16. Functional Equivalent Block Diagram of Internal Dither Circuit 22165f 29 LTC2216/LTC2215 APPLICATIONS INFORMATION Grounding and Bypassing The LTC2216/LTC2215 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2216/LTC2215 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VCM, and OVDD pins. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2216/LTC2215 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2216/LTC2215 is transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. It is critical that the exposed pad and all ground pins are connected to a ground plane of sufficient area with as many vias as possible. 22165f 30 LTC2216/LTC2215 APPLICATIONS INFORMATION Layer 1 Component Side Layer 2 GND Plane 22165f 31 LTC2216/LTC2215 APPLICATIONS INFORMATION Layer 3 GND Layer 4 GND 22165f 32 LTC2216/LTC2215 APPLICATIONS INFORMATION Layer 5 GND Layer 6 Bottom Side 22165f 33 16 LTC2217IUP LTC2216IUP LTC2216IUP LTC2215IUP LTC2215IUP DC996B-F DC996B-G DC996B-H DC996B-I DC996B-J 16 16 16 16 16 U2 LTC2217IUP BITS 5 3 1 DC996B-E TP2 PWR GND TP5 3.3V C1 0.01μF ASSEMBLY * VERSION TABLE C10 8.2pF R36 R44 86.6Ω 86.6Ω L1 56nH R45 86.6Ω 4.7pF 4.7pF 1.8pF 4.7pF 1.8pF 4.7pF C8 56nH 8.2pF 7.9pF 8.2pF 18nH 56nH 18nH 18nH 3.9pF 3.9pF L1 56nH 8.2pF 6 4 2 43.2 86.6 43.2 86.6 43.2 86.6 R36, 44 VCC R1 49.9Ω R2 49.9Ω C5 0.01μF C7 0.01μF R15 5Ω 182 86.6 182 86.6 182 86.6 R45 VCC C4 8.2pF R4 5.1Ω R5 5.1Ω T2 5 3 1 5 3 1 OFF RUN WBC1-1LB WBC1-1LB MABAES0060 WBC1-1LB MABAES0060 6 4 2 6 4 2 70MHz TO 140MHz 1MHz TO 70MHz 70MHz TO 140MHz 1MHz TO 70MHz 70MHz TO 140MHz 1MHz TO 70MHz INPUT FREQUENCY R8 1000Ω GND VDD J2 MODE R6 1000Ω ON SHDN DITHER J3 R13 100Ω C17 2.2μF R27 10Ω C8 4.7pF R28 10Ω R14 1000Ω R12 33.2Ω R11 33.2Ω C13 2.2μF VCC R10 10Ω MABAES0060 TP1 EXT REF C12 0.1μF T1 MABA-007159- T2 000000 • • C9-10 J9 AUX PWR CONNECTOR C3 0.01μF • • J7 ENCODE C2 T3 CLOCK 0.01μF ETC1-1-13 C8 8.2pF C6 0.01μF • • J5 AIN R9 10Ω R7 1000Ω 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 VDD16 VDD15 GND14 ENCN ENCP GND11 GND10 AINN AINP GND7 VDD6 VDD5 GND VCM GND2 SENSE 4 3 2 1 R37 100Ω 62 63 GND R3 DNP NC 17 VDD17 61 RAND R41 100Ω VCC GND C15 0.1μF DOUT– DOUT+ GND EN RIN+ U5 FIN1101K8X ON OFF 6 4 2 53 U2 LTC2216IUP/LTC2215IUP RIN– 18 GND18 60 MODE SHDN 59 D0+ 22 LVDS 58 D1– 5 6 7 8 23 DITH 19 VDD D1+ 24 5 D2– 25 OF+ 20 OF– J4 D2+ 26 R16 100Ω 52 3 27 D0– 21 D15+ 57 D15– 56 D14+ 55 D14– 54 D13+ D3– 51 49 50 C22 0.1μF D5– D5+ D8– D8+ D7– D7+ CLKOUT– R42 FERRITE BEAD C14 4.7μF D8– D8+ D9– D9+ D10– D10+ D11– D11+ CLKCOUT+ C20 0.1μF D13– D3+ 27 D12+ D4– 29 D12– D4+ 30 OGND50 OGND31 31 OVDD49 OVDD32 32 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 C24 4.7μF R43 FERRITE BEAD 65 C38 4.7μF 3.3V C34 0.1μF C35 0.1μF C36 0.1μF C28 0.1μF C29 0.1μF C30 0.1μF C31 0.1μF C32 0.1μF R40 100Ω R39 100Ω R38 100Ω R35 100Ω R34 100Ω R33 100Ω R32 100Ω R31 100Ω R30 100Ω R23 100Ω R22 100Ω R21 100Ω R20 100Ω R19 100Ω R18 100Ω R17 100Ω 20 21 18 19 16 17 14 15 10 11 8 9 6 7 4 5 3 22 27 46 13 20 21 18 19 16 17 14 15 10 11 8 9 6 7 4 5 3 22 27 46 13 3.3V 12 25 26 47 48 I8N I8P I7N I7P I6N I6P I5N I5P I4N I4P I3N I3P I2N I2P I1N I1P EN12 EN34 EN58 EN78 EN 41 40 39 38 35 34 33 32 31 30 29 28 O4N O4P O5N O5P O6N O6P O7N O7P O8N O8P 3.3V I8N I8P I7N I7P I6N I6P I5N I5P I4N I4P I3N I3P I2N I2P I1N I1P EN12 EN34 EN58 EN78 EN O8N O8P O7N O7P O6N O6P O5N O5P O4N O4P U4 O3N FIN1108 O3P O2N O2P O1N O1P 29 28 31 30 33 32 35 34 39 38 41 40 43 42 45 44 43 42 O2N O2P 5 44 O3N U3 FIN1108 O3P O1N O1P VC1 VC2 VC3 VC4 VC5 VE1 VE2 VE3 VE4 VE5 1 2 23 36 37 12 25 26 47 48 VC1 VC2 VC3 VC4 VC5 VE1 VE2 VE3 VE4 VE5 34 1 2 23 36 37 VCC C26 0.1μF C25 0.1μF C16 0.1μF C18 OPT C19 OPT 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 4 GND VCC 8 ARRAY EEPROM U1 24LC02ST R24 100k 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 R29 4990Ω 3.3V A1 A0 WP A2 1 2 3 7 5 6 C27 0.1μF 6CL 6DA MEC8-150-02-L-D-EDGE_CONNRE-DIM J1E J1O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 22165 F17 R26 4990Ω R25 4990Ω LTC2216/LTC2215 APPLICATIONS INFORMATION 22165f LTC2216/LTC2215 PACKAGE DESCRIPTION UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ±0.05 7.15 ±0.05 7.50 REF 8.10 ±0.05 9.50 ±0.05 (4 SIDES) 7.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.115 TYP 63 64 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER C = 0.35 7.15 ± 0.10 7.50 REF (4-SIDES) 7.15 ± 0.10 (UP64) QFN 0406 REV C 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 22165f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC2216/LTC2215 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1993 High Speed Differential Op Amp 600MHz BW, 75dBc Distortion at 70MHz LTC2202 16-Bit, 10Msps ADC 150mW, 81.6dB SNR, 100dB SFDR LTC2203 16-Bit, 25Msps ADC 230mW, 81.6dB SNR, 100dB SFDR LTC2204 16-Bit, 40Msps ADC 470mW, 79.1dB SNR, 100dB SFDR LTC2205 16-Bit, 65Msps ADC 530mW, 79dB SNR, 100dB SFDR LTC2206 16-Bit, 80Msps ADC 725mW, 77.9dB SNR, 100dB SFDR LTC2207 16-Bit, 105Msps ADC 900mW, 77.9dB SNR, 100dB SFDR LTC2208 16-Bit, 130Msps ADC 1250mW, 77.7dB SNR, 100dB SFDR LTC2209 16-Bit, 160Msps ADC 1450mW, 77.1dB SNR, 100dB SFDR LTC2217 16-Bit, 105Msps ADC Low Noise 1190mW, 81.2dB SNR, 100dB SFDR LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package LTC2220-1 12-Bit, 185Msps ADC 910mW, 67.5dB SNR, 9mm × 9mm QFN Package LTC2249 14-Bit, 65Msps ADC 230mW, 73dB SNR, 5mm × 5mm QFN Package LTC2250 10-Bit, 105Msps ADC 320mW, 61.6dB SNR, 5mm × 5mm QFN Package LTC2251 10-Bit, 125Msps ADC 395mW, 61.6dB SNR, 5mm × 5mm QFN Package LTC2252 12-Bit, 105Msps ADC 320mW, 70.2dB SNR, 5mm × 5mm QFN Package LTC2253 12-Bit, 125Msps ADC 395mW, 70.2dB SNR, 5mm × 5mm QFN Package LTC2254 14-Bit, 105Msps ADC 320mW, 72.5dB SNR, 5mm × 5mm QFN Package LTC2255 14-Bit, 125Msps ADC 395mW, 72.4dB SNR, 5mm × 5mm QFN Package LTC2299 Dual 14-Bit, 80Msps ADC 445mW, 73dB SNR, 9mm × 9mm QFN Package LT5522 400MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports LT5527 400MHz to 3.7GHz High Linearity Downconverting Mixer High IIP3: 23.5dBm at 1.9GHz, Conversion Gain: 2.3dB at 1.9GHz, NF = 12.5dB LT5557 400MHz to 3.7GHz High Signal Level High IIP3: 23.5dBm at 3.5GHz, Conversion Gain: 1.7dB at 3.5GHz Downconverting Mixer 22165f 36 Linear Technology Corporation LT 0208 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008