LTC3411A 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION Uses Tiny Capacitors and Inductor High Frequency Operation: Up to 4MHz Low RDS(ON) Internal Switches: 0.15Ω High Efficiency: Up to 96% Selectable Low Ripple (25mVP-P) Burst Mode® Operation: IQ = 40μA Stable with Ceramic Capacitors Current Mode Operation for Excellent Line and Load Transient Response Short-Circuit Protected Low Dropout Operation: 100% Duty Cycle Low Shutdown Current: IQ ≤ 1μA Output Voltages from 0.8V to 5V Synchronizable to External Clock Supports Pre-Biased Outputs Small 10-Lead 3mm × 3mm DFN or MSOP Package APPLICATIONS ■ ■ ■ ■ ■ The LTC®3411A is a constant frequency, synchronous step-down DC/DC converter. Intended for medium power applications, it operates from a 2.5V to 5.5V input voltage range and has a user configurable operating frequency up to 4MHz, allowing the use of tiny, low cost capacitors and inductors 1mm or less in height. The output voltage is adjustable from 0.8V to 5.5V. Internal synchronous power switches provide high efficiency. The LTC3411A’s current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. The LTC3411A can be configured for automatic power saving Burst Mode operation (IQ = 40μA) to reduce gate charge losses when the load current drops below the level required for continuous operation. For reduced noise and RF interference, the SYNC/MODE pin can be configured to skip pulses or provide forced continuous operation. To further maximize battery life, the P-channel MOSFET is turned on continuously in dropout (100% duty cycle). In shutdown, the device draws <1μA. Notebook Computers Digital Cameras Cellular Phones Handheld Instruments Board Mounted Power Supplies L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6580258, 6498466, 6611131. TYPICAL APPLICATION Efficiency and Power Loss vs Output Current Step-Down 2.5V/1.25A Regulator 100 VIN 2.5V TO 5.5V 90 80 PVIN PGOOD SVIN LTC3411A 2.2μH SW 22pF VOUT 2.5V 1.25A 0.1 70 60 0.01 50 40 30 ITH 12.1k 680pF 887k SHDN/RT SGND 549k VFB 22μF 10 PGND 412k 3411a TA01a 0.001 VIN = 2.7V VIN = 3.6V VIN = 4.2V 20 0 0.1 1 100 1000 10 OUTPUT CURRENT (mA) fO = 1MHz Burst Mode OPERATION POWER LOSS (W) SYNC/MODE EFFICIENCY (%) 10μF SYNC 1 0.0001 10000 3411A TA01b 3411afa 1 LTC3411A ABSOLUTE MAXIMUM RATINGS (Note 1) PVIN, SVIN Voltages ..................................... –0.3V to 6V VFB, ITH, SHDN/RT Voltages ..........–0.3V to (VIN + 0.3V) SYNC/MODE Voltage .....................–0.3V to (VIN + 0.3V) SW Voltage ..................................–0.3V to (VIN + 0.3V) PGOOD Voltage ........................................... –0.3V to 6V Operating Junction Temperature Range (Notes 2, 5, 8) ........................................ –40°C to 125°C Storage Temperature Range................... –65°C to 125°C Lead Temperatu re (Soldering, 10 sec) ............... 300°C PIN CONFIGURATION TOP VIEW SHDN/RT TOP VIEW 10 ITH 1 SHDN/RT SYNC/MODE SGND SW PGND 9 VFB SYNC/MODE 2 SGND 3 SW 4 7 SVIN PGND 5 6 PVIN 11 8 PGOOD 10 9 8 7 6 1 2 3 4 5 ITH VFB PGOOD SVIN PVIN MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 120°C/W, θJC = 10°C/W DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W, θJC = 3°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3411AEDD#PBF LTC3411AEDD#TRPBF LAJM 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3411AIDD#PBF LTC3411AIDD#TRPBF LAJM 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3411AEMS#PBF LTC3411AEMS#TRPBF LTAJK 10-Lead Plastic MSOP –40°C to 125°C LTC3411AIMS#PBF LTC3411AIMS#TRPBF LTAJK 10-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 3.6V, RT = 125k unless otherwise specified. (Note 2) SYMBOL PARAMETER CONDITIONS VIN Operating Voltage Range IFB Feedback Pin Input Current (Note 3) VFB Feedback Voltage (Note 3) ΔVLINEREG Reference Voltage Line Regulation VIN = 2.5V to 5.5V ΔVLOADREG Output Voltage Load Regulation ITH = 0.55V to 0.9V gm(EA) Error Amplifier Transconductance ITH Pin Load = ±5μA (Note 3) MIN ● ● ● TYP 2.5 0.784 MAX UNITS 5.5 V ±0.1 μA 0.8 0.816 V 0.04 0.2 %/V 0.02 0.2 % 300 μS 3411afa 2 LTC3411A ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 3.6V, RT = 125k unless otherwise specified. (Note 2) SYMBOL PARAMETER IS fOSC Input DC Supply Current (Note 4) Active Mode Sleep Mode Shutdown Shutdown Threshold High Active Oscillator Resistor Oscillator Frequency MIN TYP MAX 2.25 Synchronization Frequency RT = 125k (Note 7) (Note 7) 330 40 0.1 VIN – 0.6 125k 2.5 450 60 1 VIN – 0.4 1M 2.8 4 4 fSYNC ILIM Peak Switch Current Limit VFB = 0.5V 1.6 2.1 2.6 A RDS(ON) Top Switch On-Resistance MS Package DD Package (Note 6) MS Package DD Package (Note 6) VIN = 5.5V, VSHDN/RT = 5.5V, VSW = 0V or 5.5V VIN Ramping Down 0.15 0.15 0.13 0.13 0.01 0.18 0.16 1 Ω Ω Ω Ω μA 1.8 2.1 2.4 V –5 5 –7 7 –10 10 15 –12 12 30 % % % % Ω VSHDN/RT Bottom Switch On-Resistance ISW(LKG) Switch Leakage Current VUVLO Undervoltage Lockout Threshold PGOOD Power Good Threshold Power Bad Threshold RPGOOD tSOFT-START VSYNC/MODE = 3.6V, VFB = 0.75V VSYNC/MODE = 3.6V, VFB = 0.84V VSHDN/RT = 3.6V 0.4 V FB Ramping Up from 0.68V to 0.8V VFB Ramping Down from 0.92V to 0.8V VFB Ramping Down from 0.8V to 0.68V VFB Ramping Up from 0.8V to 0.9V Power Good Pull-Down On-Resistance VFB Step from 0V to 0.8V VFB Step from 0.8V to 0V PGOOD Blanking VSYNC-MODE CONDITIONS Pulse Skip Force Continous Burst 10% to 90% of Regulation Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3411AE is guaranteed to meet performance specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3411AI is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: The LTC3411A is tested in a feedback loop which servos VFB to the midpoint for the error amplifier (VITH = 0.7V). Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. 40 105 0.93 VIN – 0.75 0.5 0.63 VIN – 1.05 0.8 1.0 UNITS μA μA μA V Ω MHz MHz MHz μs μs V V V ms Note 5: TJ is calculated from the ambient TA and power dissipation PD according to the following formulas: LTC3411AEDD: TJ = TA + (PD • 43°C/W) LTC3411AEMS: TJ = TA + (PD • 120°C/W) Note 6: For the DD package, switch on-resistance is sampled at wafer level measurements and assured by design, characterization and correlation with statistical process controls. Note 7: 4MHz operation is guaranteed by design but not production tested and is subject to duty cycle limitations (see Applications Information). Note 8: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 3411afa 3 LTC3411A TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 3.6V, fO = 1MHz, unless otherwise noted. Efficiency vs Input Voltage Efficiency vs Output Current IOUT = 100mA IOUT = 10mA 90 IOUT = 1.25A 70 EFFICIENCY (%) EFFICIENCY (%) 80 IOUT = 1mA 60 50 100 100 90 90 80 80 70 70 EFFICIENCY (%) 100 60 50 40 VIN = 2.7V VIN = 3.6V VIN = 4.2V 20 40 10 VOUT = 1.8V 4.5 4.0 3.5 INPUT VOLTAGE(V) 3.0 VOUT = 1.8V 0 0.1 5.5 5.0 1 100 1000 10 OUTPUT CURRENT (mA) Efficiency vs Output Current 10 0 0.1 10000 Efficiency vs Frequency FORCED CONTINUOUS 40 30 20 2.2μH 92 91 1μH 0 0.1 1 10 100 1000 OUTPUT CURRENT (mA) Burst Mode OPERATION 0.25 PULSE SKIP 0.00 –0.25 VOUT = 1.8V ILOAD = 400mA VOUT = 1.8V 88 0 10000 0.50 FORCED CONTINUOUS 89 VOUT = 1.8V 3 2 FREQUENCY (MHz) 1 3411A G04 –0.50 4 0 5 200 400 600 800 1000 1200 1400 OUTPUT CURRENT(mA) 3411A G06 3411A G05 Reference Voltage vs Temperature Line Regulation Frequency Variation vs Temperature 815 0.6 10000 0.75 90 10 10 100 1000 OUTPUT CURRENT (mA) 4.7μH VOUT ERROR (%) EFFICIENCY (%) EFFICIENCY (%) 50 1 Load Regulation 93 60 VOUT = 1.5V 1.00 94 PULSE SKIP VIN = 2.7V VIN = 3.6V VIN = 4.2V 3411A G03 80 70 40 20 95 Burst Mode OPERATION 90 50 3411A G02 3411A G01 100 60 30 30 IOUT = 0.1mA 30 2.5 Efficiency vs Output Current 6 VIN = 3.6V 0.2 0.0 –0.2 –0.4 –0.6 2.5 4.5 4.0 3.5 INPUT VOLTAGE(V) 5.0 805 800 795 790 VOUT = 1.8V ILOAD = 400mA 3.0 810 FREQUENCY VARIATION (%) REFERENCE VOLTAGE (mV) VOUT ERROR (%) 0.4 5.5 3411A G07 785 –50 4 2 0 –2 –4 –25 50 25 75 0 TEMPERATURE(°C) 100 125 3411A G08 –6 –50 –25 50 25 75 0 TEMPERATURE(°C) 100 125 3411A G09 3411afa 4 LTC3411A TYPICAL PERFORMANCE CHARACTERISTICS otherwise noted. Frequency Variation vs VIN RDS(ON) vs Input Voltage 6 4 FREQUENCY VARIATION (%) TA = 25°C, VIN = 3.6V, fO = 1MHz, unless RDS(ON) vs Temperature 0.25 0.30 0.20 0.25 0 –2 RDS(ON) (Ω) RDS(ON) (Ω) 2 0.15 0.10 0.20 0.15 0.10 –4 0.05 –6 –8 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 0.0 2.5 5.5 3.0 4.5 4.0 3.5 INPUT VOLTAGE (V) 5.0 Dynamic Supply Current vs Input Voltage 0.0 –50 5.5 PULSE SKIP Burst Mode OPERATION 0.1 0.01 VOUT = 1.8V ILOAD = 0A 0.001 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 100 FORCED CONTINUOUS 10 2000 1 PULSE SKIP Burst Mode OPERATION 0.1 0.01 MAIN SWITCH 1500 1000 SYNCHRONOUS SWITCH 500 VOUT = 1.8V ILOAD = 0A 0.001 –50 0 –25 0 25 50 75 TEMPERATURE (°C) 3411A G13 100 125 0 1 4 3 2 INPUT VOLTAGE(V) 3411A G14 5 6 3411A G15 Burst Mode Operation Switch Leakage vs Temperature 125 Switch Leakage vs Input Voltage SWITCH LEAKAGE (pA) DYNAMIC SUPPLY CURRENT (mA) 1 50 25 75 0 TEMPERATURE (°C) 2500 100 FORCED CONTINUOUS –25 3411A G12 Dynamic Supply Current vs Temperature 100 10 MAIN SWITCH SYNCHRONOUS SWITCH 3411A G11 3411A G10 DYNAMIC SUPPLY CURRENT (mA) 0.05 MAIN SWITCH SYNCHRONOUS SWITCH Pulse Skippng Mode 600 SW 2V/DIV SW 2V/DIV 300 VOUT 50mV/DIV AC COUPLED VOUT 50mV/DIV AC COUPLED 200 IL 200mA/DIV IL 200mA/DIV SWITCH LEAKAGE (nA) 500 400 MAIN SWITCH SYNCHRONOUS SWITCH 100 0 –50 4μs/DIV –25 50 25 75 0 TEMPERATURE (°C) 100 125 VIN = 3.6V VOUT = 1.8V ILOAD = 50mA 3411A G17 4μs/DIV 3411A G18 VIN = 3.6V VOUT = 1.8V ILOAD = 5mA 3411A G16 3411afa 5 LTC3411A TYPICAL PERFORMANCE CHARACTERISTICS otherwise noted. Forced Continuous Mode TA = 25°C, VIN = 3.6V fO = 1MHz, unless Start-Up from Shutdown SW 2V/DIV VOUT 50mV/DIV AC COUPLED IL 200mA/DIV SHDN/RT 2V/DIV SHDN/RT 2V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV IL 1A/DIV 3411A G19 2μs/DIV Start-Up from Shutdown 200μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 80mA Start-Up from Shutdown with a Prebiased Output (Forced Continuous Mode) 3411A G24 Load Step VOUT 100mV/DIV AC COUPLED IL 500mA/DIV IL 1A/DIV IL 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV 40μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 0A to 1.25A Burst Mode OPERATION 3411A G23 VOUT Short to VIN (Forced Continuous Mode) VOUT Short to Ground Load Step 40μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 50mA to 1.25A Burst Mode OPERATION Load Step VOUT 100mV/DIV AC COUPLED 3411A G22 3411A G21 VIN = 3.6V VOUT = 1.8V ILOAD = 1.25A VOUT 1V/DIV 200μs/DIV VIN = 3.6V PREBIASED VOUT = 3V, VOUT = 1.8V ILOAD = 0A 200μs/DIV 3411A G20 VIN = 3.6V VOUT = 1.8V ILOAD = 0A VOUT 1V/DIV VOUT 100mV/DIV AC COUPLED VOUT 1V/DIV IL 1A/DIV IL 2A/DIV IL 500mA/DIV ILOAD 1A/DIV 40μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 250mA to 1.25A Burst Mode OPERATION 40μs/DIV 3411A G25 VIN = 3.6V VOUT = 1.8V ILOAD = 0A 3411A G26 40μs/DIV 3411A G27 VIN = 3.6V VOUT = 1.8V ILOAD = 0A 3411afa 6 LTC3411A PIN FUNCTIONS SHDN/RT (Pin 1): Combination Shutdown and Timing Resistor Pin. The oscillator frequency is programmed by connecting a resistor from this pin to ground. Forcing this pin to SVIN causes the device to be shut down. In shutdown all functions are disabled. PGND (Pin 5): Main Power Ground Pin. Connect to the (–) terminal of COUT, and (–) terminal of CIN. PVIN (Pin 6): Main Supply Pin. Must be closely decoupled to PGND. SVIN (Pin 7): The Signal Power Pin. All active circuitry is powered from this pin. Must be closely decoupled to SGND. SVIN must be greater than or equal to PVIN. SYNC/MODE (Pin 2): Combination Mode Selection and Oscillator Synchronization Pin. This pin controls the operation of the device. When tied to SVIN or SGND, Burst Mode operation or pulse skipping mode is selected, respectively. If this pin is held at half of SVIN, the forced continuous mode is selected. The oscillation frequency can be synchronized to an external oscillator applied to this pin. When synchronized to an external clock pulse skip mode is selected. PGOOD (Pin 8): The Power Good Pin. This common drain logic output is pulled to SGND when the output voltage is not within ±7% of regulation. VFB (Pin 9): Receives the feedback voltage from the external resistive divider across the output. Nominal voltage for this pin is 0.8V. SGND (Pin 3): The Signal Ground Pin. All small-signal components and compensation components should be connected to this ground (see Board Layout Considerations). ITH (Pin 10): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0.4V to 1.4V. SW (Pin 4): The Switch Node Connection to the Inductor. This pin swings from PVIN to PGND. PIN NAME 1 SHDN/RT 2 SYNC/MODE 3 SGND Exposed Pad (Pin 11): Power Ground. Must be soldered to electrical ground on PCB. DESCRIPTION MIN NOMINAL (V) TYP MAX MIN MAX Shutdown/Timing Resistor –0.3 0.8 SVIN –0.3 SVIN + 0.3 SVIN –0.3 SVIN + 0.3 PVIN –0.3 PVIN + 0.3 5.5 –0.3 SVIN + 0.3 Mode Select/Sychronization Pin 0 Signal Ground Switch Node ABSOLUTE MAX (V) 0 4 SW 5 PGND Main Power Ground 0 6 PVIN Main Power Supply –0.3 Signal Power Supply 0 2.5 5.5 –0.3 6 Power Good Pin 0 SVIN –0.3 6 VFB Output Feedback Pin 0 1.0 –0.3 SVIN + 0.3 ITH Error Amplifier Compensation and Run Pin 0 1.5 –0.3 SVIN + 0.3 7 SVIN 8 PGOOD 9 10 0.8 3411afa 7 LTC3411A BLOCK DIAGRAM SVIN SGND ITH PVIN 7 3 10 6 0.8V PMOS CURRENT COMPARATOR ITH LIMIT VOLTAGE REFERENCE + BCLAMP + – – VFB 9 ERROR AMPLIFIER VB 0.74V + – – + BURST COMPARATOR SLOPE COMPENSATION OSCILLATOR 4 SW + 0.86V LOGIC – + PGOOD 8 NMOS COMPARATOR – – REVERSE COMPARATOR 1 2 SHDN/RT SYNC/MODE + 5 PGND 3411A BD 3411afa 8 LTC3411A OPERATION The LTC3411A uses a constant frequency, current mode architecture. The operating frequency is determined by the value of the RT resistor or can be synchronized to an external oscillator. To suit a variety of applications, the selectable MODE pin allows the user to trade-off noise for efficiency. The output voltage is set by an external divider returned to the VFB pin. An error amplifier compares the divided output voltage with the reference voltage of 0.8V and adjusts the peak inductor current accordingly. Overvoltage and undervoltage comparators will pull the PGOOD output low if the output voltage is not within ±7% of its regulated value. A tripping delay of 40μs and untripping delay of 105μs ensures PGOOD will not glitch due to transient spikes on VOUT. Main Control Loop During normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle. Current flows through this switch into the inductor and the load, increasing until the peak inductor current reaches the limit set by the voltage on the ITH pin. Then the top switch is turned off, the bottom switch is turned on, and the energy stored in the inductor forces the current to flow through the bottom switch and the inductor, out into the load until the next clock cycle. The peak inductor current is controlled by the voltage on the ITH pin, which is the output of the error amplifier. The output is developed by the error amplifier comparing the feedback voltage, VFB, to the 0.8V reference voltage. When the load current increases, the output voltage and VFB decrease slightly. This decrease in VFB causes the error amplifier to increase the ITH voltage until the average inductor current matches the new load current. The main control loop is shut down by pulling the SHDN/RT pin to SVIN, resetting the internal soft-start. Re-enabling the main control loop by releasing the SHDN/RT pin activates the internal soft-start, which slowly ramps the output voltage over approximately 0.8ms until it reaches regulation. switch from continuous operation to the selected mode when the load current is low. To optimize efficiency, the Burst Mode operation can be selected. When the load is relatively light, the LTC3411A automatically switches into Burst Mode operation in which the PMOS switch operates intermittently based on load demand. By running cycles periodically, the switching losses which are dominated by the gate charge losses of the power MOSFETs are minimized. The main control loop is interrupted when the output voltage reaches the desired regulated value. The burst comparator trips when ITH is below approximately 0.5V, shutting off the switch and reducing the power. The output capacitor and the inductor supply the power to the load until ITH rises above approximately 0.5V, turning on the switch and the main control loop which starts another cycle. For lower output voltage ripple at low currents, pulse skipping mode can be used. In this mode, the LTC3411A continues to switch at a constant frequency down to very low currents, where it will eventually begin skipping pulses. Finally, in forced continuous mode, the inductor current is constantly cycled which creates a fixed output voltage ripple at all output current levels. This feature is desirable in telecommunications since the noise is at a constant frequency and is thus, easy to filter out. Another advantage of this mode is that the regulator is capable of both sourcing current into a load and sinking current from the output. Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. In dropout, the PMOS switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drop across the internal P-channel MOSFET and the inductor. Low Supply Operation Low Current Operation Three modes are available to control the operation of the LTC3411A at low currents. All three modes automatically The LTC3411A incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 2.1V to prevent unstable operation. 3411afa 9 LTC3411A APPLICATIONS INFORMATION A general LTC3411A application circuit is shown in Figure 4. External component selection is driven by the load requirement, and begins with the selection of the inductor L1. Once L1 is chosen, CIN and COUT can be selected. Operating Frequency Selection of the operating frequency is a trade-off between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency, fO, of the LTC3411A is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: A reasonable starting point for setting ripple current is ΔIL = 0.4 • IOUT(MAX), where IOUT(MAX) is 1.25A. The largest ripple current ΔIL occurs at the maximum input voltage. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: V VOUT L = OUT • 1 fO • IL V IN(MAX) The inductor value will also have an effect on Burst Mode operation. The transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. 5000 RT = 5 × 107 (f –1.6508 (kΩ), O) TA = 25°C 4500 The maximum usable operating frequency is limited by the minimum on-time and the duty cycle. This can be calculated as: V fO(MAX) ≈ 6.67 • OUT (MHz) VIN(MAX) The minimum frequency is internally set at around 200kHz. FREQUENCY (kHz) 4000 where fO is in kHz, or can be selected using Figure 1. 3500 3000 2500 2000 1500 1000 500 0 0 400 800 1200 RT (kΩ) 1600 3411A F01 Inductor Selection The operating frequency, fO, has a direct effect on the inductor value, which in turn influences the inductor ripple current ΔIL: V IL = OUT fO • L V • 1 OUT V IN The inductor ripple current decreases with larger inductance or frequency, and increases with higher VIN or VOUT. Accepting larger values of ΔIL allows the use of lower inductances, but results in higher output ripple voltage, greater core loss and lower output capability. Figure 1. Frequency vs RT Inductor Core Selection Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on what the LTC3411A requires to operate. Table 1 3411afa 10 LTC3411A APPLICATIONS INFORMATION shows some typical surface mount inductors that work well in LTC3411A applications. Table 1. Representative Surface Mount Inductors MANUFACTURER PART NUMBER MAX DC VALUE CURRENT DCR HEIGHT Toko A914BYW-1R2M=P3: D52LC 1.2μH 2.15A 44mΩ A960AW-1R2M=P3: D518LC 1.2μH 1.8A 46mΩ 1.8mm DB3015C-1068AS-1R0N 1.0μH 2.1A 43mΩ 1.5mm DB3018C-1069AS-1R0N 1.0μH 2.1A 45mΩ 1.8mm DB3020C-1070AS-1R0N 1.0μH 2.1A 47mΩ 2mm A914BYW-2R2M-D52LC 2.2μH 2.05A 49mΩ 2mm A915AY-2ROM-D53LC 3.3A 22mΩ 3mm Coilcraft Sumida 2.0μH 2mm LPO1704-122ML 1.2μH 2.1A 80mΩ 1mm D01608C-222 2.2μH 2.3A 70mΩ 3mm LP01704-222M 2.2μH 2.4A 120mΩ 1mm CR32-1R0 1.0μH 2.1A 72mΩ CR5D11-1R0 1.0μH 2.2A 40mΩ 1.2mm CDRH3D14-1R2 1.2μH 2.2A 36mΩ 1.5mm CDRH4D18C/LD-1R1 1.1μH 2.1A 24mΩ CDRH4D28C/LD-1R0 1.0μH 3.0A 17.5mΩ 3mm 2mm CDRH4D28C-1R1 1.1μH 3.8A CDRH4D28-1R2 1.2μH 2.56A 23.6mΩ 3mm CDRH6D12-1R0 1.0μH 2.80A 37.5mΩ 1.5mm CDRH4D282R2 2.2μH 2.04A 23mΩ CDC5D232R2 2.2μH 2.16A 30mΩ 2.5mm Taiyo Yuden NPO3SB1ROM 22mΩ 3mm 3mm 3mm 1.0μH 2.6A 27mΩ 1.8mm N06DB2R2M 2.2μH 3.2A 29mΩ 3.2mm N05DB2R2M 2.2μH 2.9A 32mΩ 2.8mm Murata LQN6C2R2M04 2.2μH 3.2A 24mΩ 5mm FDK MIPW3226DORGM 0.9μH 1.4A 80mΩ 1mm Catch Diode Selection Although unnecessary in most applications, a small improvement in efficiency can be obtained in a few applications by including the optional diode D1 shown in Figure 4, which conducts when the synchronous switch is off. When using Burst Mode operation or pulse skip mode, the synchronous switch is turned off at a low current and the remaining current will be carried by the optional diode. It is important to adequately specify the diode peak current and average power dissipation so as not to exceed the diode ratings. The main problem with Schottky diodes is that their parasitic capacitance reduces the efficiency, usually negating the possible benefits for LTC3411A circuits. Another problem that a Schottky diode can introduce is higher leakage current at high temperatures, which could reduce the low current efficiency. Remember to keep lead lengths short and observe proper grounding (see Board Layout Considerations) to avoid ringing and increased dissipation when using a catch diode. Input Capacitor (CIN) Selection In continuous mode, the input current of the converter is a square wave with a duty cycle of approximately VOUT/VIN. To prevent large voltage transients, a low equivalent series resistance (ESR) input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: IRMS ≈ IMAX VOUT (VIN − VOUT ) VIN where the maximum average output current IMAX equals the peak current minus half the peak-to-peak ripple current, IMAX = ILIM – ΔIL /2. This formula has a maximum at VIN = 2VOUT, where IRMS ≅ IOUT/2. This simple worst case is commonly used to design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet the size or height requirements of the design. An additional 0.1μF to 1μF ceramic capacitor is also recommended on VIN for high frequency decoupling, when not using an all ceramic capacitor solution. Output Capacitor (COUT) Selection The selection of COUT is driven by the required ESR to minimize voltage ripple and load step transients. Typically, once the ESR requirement is satisfied, the capacitance 3411afa 11 LTC3411A APPLICATIONS INFORMATION is adequate for filtering. The output ripple (ΔVOUT) is determined by: 1 VOUT IL ESR + 8fO COUT where fO = operating frequency, COUT = output capacitance and ΔIL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. With ΔIL = 0.4 • IOUT(MAX) the output ripple will be less than 100mV at maximum VIN, a minimum COUT value of 10μF and fO = 1MHz with: ESRCOUT < 150mΩ Once the ESR requirements for COUT have been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement, except for an all ceramic solution. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any aluminum electrolytic at a somewhat higher price. Special polymer capacitors, such as Sanyo POSCAP, offer very low ESR, but have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but it has a larger ESR and it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and is often used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have the lowest ESR and cost but also have the lowest capacitance density, a high voltage and temperature coefficient and exhibit audible piezoelectric effects. In addition, the high Q of ceramic capacitors along with trace inductance can lead to significant ringing. Other capacitor types include the Panasonic specialty polymer (SP) capacitors. In most cases, 0.1μF to 1μF of ceramic capacitors should also be placed close to the LTC3411A in parallel with the main capacitors for high frequency decoupling. Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3411A’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about 2 to 3 times the linear drop of the first cycle. Thus, a good place to start is with the output capacitor value of approximately: COUT ≈ 2.5 ΔIOUT fO • VDROOP More capacitance may be required depending on the duty cycle and load step requirements. 3411afa 12 LTC3411A APPLICATIONS INFORMATION In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 10μF ceramic capacitor is usually enough for these conditions. Setting the Output Voltage The LTC3411A develops a 0.8V reference voltage between the feedback pin, VFB, and the signal ground as shown in Figure 4. The output voltage is set by a resistive divider according to the following formula: R2 VOUT 0.8V 1+ R1 Keeping the current small (<5μA) in these resistors maximizes efficiency, but making them too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. To improve the frequency response, a feed-forward capacitor CF may also be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. Shutdown and Soft-Start The SHDN/RT pin is a dual purpose pin that sets the oscillator frequency and provides a means to shut down the LTC3411A. This pin can be interfaced with control logic in several ways, as shown in Figure 2 and Figure 3. In both configurations, Run = “0” shuts down the LTC3411A and Run = “1” activates the LTC3411A. of how to switch from force continuous mode to pulse skipping mode when RUN goes low. The parasitic drain capacitance of a large transistor coupled with a large pull up resistor results in large RC constants. As RUN goes low, the transistor drain charges up slowly, gradually decreasing the oscillator frequency of the part. This leads to large inductor current ripples translating into large output voltage ripples. In some cases, the output voltage could rise up to dangerous levels. When activating the LTC3411A, an internal soft-start slowly ramps the output voltage up until regulation. Soft-start prevents surge currents from VIN by gradually ramping the output voltage up during start-up. The output will ramp from zero to full scale over a time period of approximately 0.7ms. This prevents the LTC3411A from having to quickly charge the output capacitor and thus supplying an excessive amount of instantaneous current. The LTC3411A can start into a back-biased output in forced continuous operation. When the output is pre-biased at either a higher or lower value than the regulated output voltage, the LTC3411A will sink or source current as needed to bring the output back into regulation. However, during soft-start the regulator will always start in pulse skipping mode ignoring the mode selected with the SYNC/MODE SHDN/RT SVIN RT 100k RUN 3411A F03 Care must be taken when using Figure 3 to shut down the part in force continuous mode. The pull up resistor should be as small as the application would allow and the pull down transistor should be as small as possible to minimize its parasitic drain capacitance. If possible, always shut down the part while in pulse skipping mode or Burst Mode operation. Figure 4 shows an example SHDN/RT Figure 3. SHDN/RT Pin Activated with a Switch SHDN/RT RT 0V OFF ON SVIN 1M 3V 100k RT SYNC/MODE 100k RUN 3411A F02 3411A F04 Figure 2. SHDN/RT Pin Activated with a Logic Input Figure 4. Automatic Mode Change Circuit 3411afa 13 LTC3411A APPLICATIONS INFORMATION pin. This prevents the output from discharging to below the regulation point when soft-starting. Mode Selection and Frequency Synchronization The SYNC/MODE pin is a multipurpose pin which provides mode selection and frequency synchronization. Connecting this pin to VIN enables Burst Mode operation, which provides the best low current efficiency at the cost of a higher output voltage ripple. When this pin is connected to ground, pulse skipping operation is selected which provides the lowest output voltage and current ripple at the cost of low current efficiency. Applying a voltage that is half the value of the input voltage results in forced continuous mode, which creates a fixed output ripple and is capable of sinking up to 0.4A. Since the switching noise is constant in this mode, it is also the easiest to filter out. The LTC3411A can also be synchronized to an external clock signal by the SYNC/MODE pin. The internal oscillator frequency should be set to ±20% of the external clock frequency to ensure adequate slope compensation, since slope compensation is derived from the internal oscillator. During synchronization, the mode is set to pulse skipping and the top switch turn on is synchronized to the falling edge of the external clock. Checking Transient Response The OPTI-LOOP® compensation allows the transient response to be optimized for a wide range of loads and output capacitors. The availability of the ITH pin not only allows VIN + C6 The ITH external components shown in the circuit on the front page of this data sheet will provide an adequate starting point for most applications. The series R-C filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its OPTI-LOOP is a registered trademark of Linear Technology Corporation. R5 R6 CIN SVIN PVIN PGOOD C8 PGND optimization of the control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time and settling time at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. L1 PGOOD SW PGND SGND SYNC/MODE ITH SGND RC CITH + D1 OPTIONAL LTC3411A VOUT COUT C5 CF VFB SGND PGND R2 SHDN/RT RT CC PGND PGND R1 3411A F05 SGND SGND GND SGND SGND Figure 5. LTC3411A General Schematic 3411afa 14 LTC3411A APPLICATIONS INFORMATION steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The gain of the loop increases with R and the bandwidth of the loop increases with decreasing C. If R is increased by the same factor that C is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, a feedforward capacitor CF can be added to improve the high frequency response, as shown in Figure 5. Capacitor CF provides phase lead by creating a high frequency zero with R2 which improves the phase margin. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Linear Technology Application Note 76. Although a buck regulator is capable of providing the full output current in dropout, it should be noted that as the input voltage VIN drops toward VOUT, the load step capability does decrease due to the decreasing voltage across the inductor. Applications that require large load step capability near dropout should use a different topology such as SEPIC, Zeta or single inductor, positive buck/boost. 1 VIN = 3.6V fO = 1MHz POWER LOSS (W) 0.1 0.01 0.001 0.0001 0.1 VOUT = 1.2V VOUT = 1.5V = 1.8V VOUTVOUT = 1.2V - 1.8V 1 10 100 1000 LOAD CURRENT (mA) 10000 3411A F06 Figure 6. Power Loss vs Load Currrent In some applications, a more severe transient can be caused by switching in loads with large (>1μF) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A Hot Swap™ controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3411A circuits: 1) VIN current, 2) switching losses, 3) I2R losses, 4) other losses. 1) The VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. VIN current results in a small (<0.1%) loss that increases with VIN, even at no load. 2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC bias current. In continuous mode, IGATECHG = fO(QT + QB), where QT and QB are the gate charges of the internal top and bottom MOSFET switches. The gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. Hot Swap is a trademark of Linear Technology Corporation. 3411afa 15 LTC3411A APPLICATIONS INFORMATION 3) I2R Losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the internal top and bottom switches. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses: I2R losses = IOUT2(RSW + RL) 4) Other “hidden” losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. Other losses including diode conduction losses during dead-time and inductor core losses which generally account for less than 2% total additional loss. Thermal Considerations In a majority of applications, the LTC3411A does not dissipate much heat due to its high efficiency. However, in applications where the LTC3411A is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3411A from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD • θJA where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TRISE + TAMBIENT As an example, consider the case when the LTC3411A is in dropout at an input voltage of 3.3V with a load current of 1A. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the P-channel switch is 0.15Ω. Therefore, power dissipated by the part is: PD = I2 • RDS(ON) = 150mW The MS10 package junction-to-ambient thermal resistance, θJA, will be in the range of 100°C/W to 120°C/W. Therefore, the junction temperature of the regulator operating in a 70°C ambient temperature is approximately: TJ = 0.15 • 120 + 70 = 88°C Remembering that the above junction temperature is obtained from an RDS(ON) at 25°C, we might recalculate the junction temperature based on a higher RDS(ON) since it increases with temperature. However, we can safely assume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125°C. Design Example As a design example, consider using the LTC3411A in a portable application with a Li-Ion battery. The battery provides a VIN = 2.5V to 4.2V. The load requires a maximum of 1.25A in active mode and 10mA in standby mode. The output voltage is VOUT = 2.5V. Since the load still needs power in standby, Burst Mode operation is selected for good low load efficiency. First, calculate the timing resistor for 1MHz operation: RT = 5 × 107 (103)–1.6508 = 557.9k Use a standard value of 549k. Next, calculate the inductor value for about 40% ripple current at maximum VIN: L= 2.5V 2.5V • 1 = 2μH 1MHz • 500mA 4.2V Choosing the closest standard inductor value from a vendor of 2.2μH, results in a maximum ripple current of: IL = 2.5V 1MHz • 2.2μ 2.5V • 1 = 460mA 4.2V 3411afa 16 LTC3411A APPLICATIONS INFORMATION For cost reasons, a ceramic capacitor will be used. COUT selection is then based on load step droop instead of ESR requirements. For a 5% output droop: the LTC3411A. These items are also illustrated graphically in the layout diagram of Figure 7. Check the following in your layout: 1.25A = 25μF 1MHz • (5% • 2.5V) 1. Does the capacitor CIN connect to the power VIN (Pin 6) and power GND (Pin 5) as close as possible? This capacitor provides the AC current to the internal power MOSFETs and their drivers. COUT ≈ 2.5 The closest standard value is 22μF. Since the output impedance of a Li-Ion battery is very low, CIN is typically 10μF. In noisy environments, decoupling SVIN from PVIN with an R6/C8 filter of 1Ω/0.1μF may help, but is typically not needed. 2. Are the COUT and L1 closely connected? The (–) plate of COUT returns current to PGND and the (–) plate of CIN. 3. The resistor divider, R1 and R2, must be connected between the (+) plate of COUT and a ground line terminated near SGND (Pin 3). The feedback signal VFB should be routed away from noisy components and traces, such as the SW line (Pin 4), and its trace should be minimized. The output voltage can now be programmed by choosing the values of R1 and R2. To maintain high efficiency, the current in these resistors should be kept small. Choosing 2μA with the 0.8V feedback voltage makes R1~400k. A close standard 1% resistor value is 412k. Then R2 is 887k. 4. Keep sensitive components away from the SW pin. The input capacitor CIN, the compensation capacitor CC and CITH and all the resistors R1, R2, RT, and RC should be routed away from the SW trace and the inductor L1. The SW pin pad should be kept as small as possible. The compensation should be optimized for these components by examining the load step response but a good place to start for the LTC3411A is with a 12.1kΩ and 680pF filter. The output capacitor may need to be increased depending on the actual undershoot during a load step. 5. A ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the SGND pin at one point which is then connected to the PGND pin. The PGOOD pin is a common drain output and requires a pullup resistor. A 100k resistor is used for adequate speed. The circuit on page 1 of this data sheet shows the complete schematic for this design example. 6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to one of the input supplies: PVIN, PGND, SVIN or SGND. Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of CIN VIN PVIN PGND SVIN SW LTC3411A SGND R5 PGOOD C4 R2 R1 COUT L1 VOUT VIN PGOOD VFB SYNC/MODE ITH SHDN/RT PS RC CC CITH BM RT 3411A F07 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 7. LTC3411A Layout Diagram (See Board Layout Checklist) 3411afa 17 LTC3411A TYPICAL APPLICATIONS General Purpose Buck Regulator Using Ceramic Capacitors VIN 2.5V TO 5.5V C1 10μF PGND PVIN SVIN RS1 1M BM PGOOD LTC3411A SYNC/MODE FC PS RS2 1M ITH R5 100k PGOOD L1 2.2μH VOUT 1.2V/1.5V/1.8V AT 1.25A SW R2 442k VFB SHDN/RT 1.8V SGND 1.5V 1.2V PGND R3 12.1k R4 549k C3 680pF C2 22μF C4 22pF R1A 357k R1B 511k R1C 887k 3411A TA02a SGND SGND GND SGND PGND NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE C1, C2: TAIYO YUDEN JMK325BJ226MM L1: TOKO A914BYW-2R2M (D52LC SERIES) Efficiency vs Output Current 100 90 Burst Mode OPERATION VOUT 100mV/DIV AC COUPLED EFFICIENCY (%) 80 70 PULSE SKIP IL 1A/DIV 60 50 40 ILOAD 1A/DIV FORCED CONTINUOUS 30 20 VIN = 3.6V VOUT = 1.2V fO = 1MHz 10 0 0.1 1 10 100 1000 OUTPUT CURRENT (mA) 40μs/DIV VIN = 3.6V VOUT = 1.2V ILOAD = 100mA TO 1.25A Burst Mode OPERATION 10000 3411A TA02c 3411A TA02b VOUT 100mV/DIV AC COUPLED IL 1A/DIV ILOAD 1A/DIV 40μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 100mA TO 1.25A PULSE SKIPPING MODE 3411A TA02d 3411afa 18 LTC3411A PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) R = 0.115 TYP 6 0.38 ± 0.10 10 0.675 ±0.05 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 3.00 ±0.10 (4 SIDES) PACKAGE OUTLINE 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) (DD) DFN 1103 5 0.200 REF 0.25 ± 0.05 1 0.25 ± 0.05 0.50 BSC 0.75 ±0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) 2.38 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev E) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 10 9 8 7 6 0.497 ± 0.076 (.0196 ± .003) REF 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) 0.254 (.010) DETAIL “A” 0° – 6° TYP GAUGE PLANE 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 0.53 ± 0.152 (.021 ± .006) 0.86 (.034) REF 1.10 (.043) MAX DETAIL “A” 0.18 (.007) SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.1016 ± 0.0508 (.004 ± .002) MSOP (MS) 0307 REV E NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 3411afa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC3411A TYPICAL APPLICATION 1mm Height, 2MHz, Li-Ion to 1.8V Converter VIN 2.5V TO 4.2V R5 100k C1 10μF PVIN PGOOD SVIN SW LTC3411A PGOOD L1 0.9μH C4 22pF C2 10μF ×2 SYNC/MODE ITH R3 13.3k SGND PGND C3 470pF VFB SHDN/RT R4 178k R1 698k VOUT 1.8V AT 1.25A R2 887k C1, C2: TAIYO YUDEN JMK107BJ106MA L1: FDK MIPW3226DORGM 3411A TA04a Efficiency vs Output Current 100 90 EFFICIENCY (%) 80 VOUT 100mV/DIV AC COUPLED VOUT 100mV/DIV AC COUPLED IL 1A/DIV IL 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV 70 60 50 40 30 20 10 0 0.1 VOUT = 1.8V fO = 2MHz 1 VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 100 1000 OUTPUT CURRENT (mA) 40μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 50mA TO 1.25A 10000 3411A TA04c 40μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 250mA TO 1.25A 3411A TA04d 3411A TA04b RELATED PARTS PART NUMBER DESCRIPTION LTC3406A/LTC3406AB 600mA (IOUT ), 1.5MHz Synchronous Step-Down DC/DC Converters COMMENTS 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA, ISD < 1μA, ThinSOT™ 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, LTC3407A/LTC3407A-2 Dual 600mA/800mA (IOUT ), 1.5MHz/2.25MHz Synchronous Step-Down DC/DC Converters IQ = 40μA, ISD < 1μA, MS10E, DFN 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, LTC3410/LTC3410B 300mA (IOUT ), 2.25MHz Synchronous Step-Down DC/DC Converters IQ = 26μA, ISD < 1μA, SC70 96% Efficiency, VIN: 2.6V to 5.5V, VOUT(MIN) = 0.8V, LTC3411 1.25A (IOUT ), 4MHz Synchronous Step-Down DC/DC Converter IQ = 60μA, ISD < 1μA, MS10, 3mm × 3mm DFN 96% Efficiency, VIN: 2.6V to 5.5V, VOUT(MIN) = 0.8V, LTC3412A 2.5A (IOUT ), 4MHz Synchronous Step-Down DC/DC Converter IQ = 62μA, ISD < 1μA, TSSOP16E, 4mm × 4mm QFN LTC3531/LTC3531-3 200mA (IOUT ), 1.5MHz Synchronous Buck-Boost DC/DC Converters 95% Efficiency, VIN: 1.8V to 5.5V, VOUT(MIN) = 2V to 5V, IQ = 16μA, ISD < 1μA, ThinSOT, DFN LTC3531-3.3 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN) = 2.4V to LTC3532 500mA (IOUT ), 2MHz Synchronous Buck-Boost DC/DC Converter 5.25V, IQ = 35μA, ISD < 1μA, MS10, DFN LTC3542 500mA (IOUT ), 2.25MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 26μA, ISD < 1μA, 2mm × 2mm DFN LTC3544/LTC3544B Quad 300mA + 2× 200mA + 100mA, 2.25MHz Synchronous 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 70μA, ISD < 1μA, 3mm × 3mm QFN Step-Down DC/DC Converter LTC3547/LTC3547B Dual 300mA, 2.25MHz Synchronous Step-Down DC/DC Converters 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD < 1μA, 2mm × 3mm DFN 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, LTC3548/LTC3548-1 Dual 400mA/800mA, (IOUT ), 2.25MHz Synchronous Step-Down DC/DC Converters IQ = 40μA, ISD < 1μA, MS10E, DFN LTC3548-2 LTC3560 800mA (IOUT ), 2.25MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 16μA, ISD < 1μA, ThinSOT ThinSOT is a trademark of Linear Technology Corporation. 3411afa 20 Linear Technology Corporation LT 0908 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008