LINER LTC4265CDE

LTC4265
IEEE 802.3at High Power PD
Interface Controller with
2-Event Classification Recognition
FEATURES
DESCRIPTION
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The LTC®4265 is a 3rd generation Powered Device (PD)
Interface controller intended for IEEE 802.3at high power
Power-over-Ethernet (PoE) applications up to 25.5W. By
supporting 1-event and 2-event classification signaling as
defined by IEEE 802.3, the LTC4265 can be used in a wide
range of product configurations. A 100V MOSFET isolates
the DC/DC converter during detection and classification,
and provides 100mA inrush current for a smooth powerup transition. The LTC4265 also includes complementary
power good outputs, an on-board signature resistor,
undervoltage/overvoltage lockout and comprehensive
thermal protection. All Linear Technology PD solutions
include a shutdown pin with signature corrupt to provide
flexible auxiliary power options.
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IEEE 802.3af/at Powered Device (PD) Controller
IEEE 802.3at 2-event Classification Signaling
Programmable Classification Current
Flexible Auxiliary Power Support Using SHDN Pin
Rugged 100V Onboard MOSFET with 100mA Inrush
Current Limit.
Complementary Power Good Outputs
Onboard Signature Resistor
Comprehensive Thermal Protection
Undervoltage and Overvoltage Lockout
12-Lead, 4mm × 3mm DFN Package
APPLICATIONS
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802.11n Access Points
High Power VoIP Video Phones
RFID Reader Systems
PTZ Security Cameras and Surveillance Equipment
The LTC4265 PD interface controller can be used along
with a variety of DC/DC converter products to provide a
complete, cost effective power solution for high power
PD applications.
The LTC4265 is available in the space-saving low profile
(4mm × 3mm) DFN package and is drop-in compatible
with the LTC4264.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Turn-On vs Time
54V FROM
DATA PAIR
54V FROM
SPARE PAIR
TO AUX
~
LTC4265
GND
0.1μF
~
–
~
+
RCLASS PWRGD
RCLASS
PWRGD
SHDN
~
–
CLOAD = 100μF
GND – VIN
50V/DIV
+
VIN
T2PSE
VOUT
5μF
MIN
+
V+
SWITCHING
POWER
SUPPLY
RUN
RTN
+
3.3V
TO LOGIC
–
TO LOGIC
4265 TA01a
GND – VOUT
50V/DIV
PWRGD – VOUT
50V/DIV
IPD
100mA/DIV
TIME
25ms/DIV
4265 TA01b
4265f
1
LTC4265
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2, 3)
GND Voltage ............................................ –0.3V to 100V
VOUT Voltage ........................–0.3V to 100V (and ≤ GND)
VOUT Pull-Up Current ..................................................1A
SHDN ....................................................... –0.3V to 100V
RCLASS, Voltage ............................................ –0.3V to 7V
RCLASS Current.......................................................50mA
PWRGD Voltage (Note 4)
Low Impedance Source .....VOUT – 0.3V to VOUT +11V
Pull-Up Current ....................................................5mA
PWRGD, T2PSE Voltage........................... –0.3V to 100V
PWRGD, T2PSE Pull-Up Current ............................10mA
Junction Temperature ........................................... 125°C
Operating Ambient Temperature Range
LTC4265C ................................................ 0°C to 70°C
LTC4265I.............................................. –40°C to 85°C
TOP VIEW
SHDN
1
12 GND
T2PSE
2
11 NC
RCLASS
3
13
10 PWRGD
NC
4
9
PWRGD
VIN
5
8
VOUT
VIN
6
7
VOUT
DE PACKAGE
12-LEAD (4mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) TO BE SOLDERED TO PCB HEAT SINK
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4265CDE#PBF
LTC4265CDE#TRPBF
4265
12-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC4265IDE#PBF
LTC4265IDE#TRPBF
4265
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4265f
2
LTC4265
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
Operating Input Voltage
Signature Range
Classification Range
Turn-On Voltage
Undervoltage Lock Out
Overvoltage Lock Out
At GND Pin (Note 5)
MIN
TYP
MAX
UNITS
60
9.8
21
37.2
V
V
V
V
V
V
l
l
l
l
1.5
12.5
ON/UVLO Hysteresis Window
l
4.1
V
Signature/Class Hysteresis Window
l
1.4
V
State Machine Reset for 2-event Classification
l
2.57
Supply Current at 60V
Measured at GND Pin
Class 0 Current
30.0
71
5.40
V
l
1.35
mA
GND = 17.5V, No RCLASS Resistor
l
0.40
mA
Signature Resistance
1.5V ≤ GND ≤ 9.8V (Note 6)
l
26
kΩ
Invalid Signature Resistance, SHDN Invoked
1.5V ≤ GND ≤ 9.8V, VSHDN = 3V (Note 6)
l
11
kΩ
l
11
kΩ
Reset Threshold
SUPPLY CURRENT
SIGNATURE
Invalid Signature Resistance During Mark Event (Notes 6, 7)
23.25
CLASSIFICATION
Class Accuracy
10mA < ICLASS < 40mA, 12.5V < GND < 21V (Note 8, 9)
l
±3.5
%
Classification Stability Time
GND Pin Step to 17.5V, RCLASS = 30.9, ICLASS Within
3.5% of Ideal Value (Notes 8, 9)
l
1
ms
GND = 54, VOUT = 3V
l
100
180
mA
Power FET On Resistance
Tested at 600mA into VOUT, GND = 54V
l
0.70
1.0
Ω
Power FET Leakage Current at VOUT
GND = SHDN = VOUT = 57V
l
1
μA
NORMAL OPERATION
Inrush Current
60
DIGITAL INTERFACE
SHDN Input High Level Voltage
l
SHDN Input Low Level Voltage
l
SHDN Input Resistance
GND = 9.8V, SHDN = 9.65V
l
PWRGD, T2PSE Voltage Output Low
Tested at 1mA, GND = 54V. For T2PSE, Must Complete
2-event Classification to See Active Low.
l
PWRGD, T2PSE Leakage Current
Pin Voltage Pulled 57V, GND = VIN = 0
PWRGD Voltage Output Low
3
V
0.45
100
V
kΩ
0.15
V
l
1
μA
Tested at 0.5mA, GND = 52V, VOUT = 48V, Output Voltage
is with Respect to VOUT
l
0.4
V
PWRGD Voltage Clamp
Tested at 2mA, VOUT = 0V, Voltage with Respect to VOUT
l
16.5
V
PWRGD Leakage Current
VPWRGD = 11V, VOUT = VIN = 0V, GND = 54V
l
1
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All voltages are with respect to VIN pin unless otherwise noted.
Note 3: Pins with 100V absolute maximum guaranteed for T ≥ 0ºC, otherwise 90V.
Note 4: PWRGD voltage clamps at 14V with respect to VOUT.
Note 5: Input voltage specifications are defined with respect to LTC4265
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
12
Note 6: Signature resistance is measured via the ΔV/ΔI method with a
minimum ΔV of 1V. The LTC4265 signature resistance accounts for the
additional series resistance in the input diode bridge.
Note 7: An invalid signature after the 1st classification event is mandated
by IEEE 802.3at standard. See Applications Information.
Note 8: Class accuracy is with respect to the ideal current defined as
1.237/RCLASS and does not include variations in RCLASS resistance.
Note 9: This parameter is assured by design and wafer level testing.
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LTC4265
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
Input Current vs Input Voltage
50
TA = 25°C
INPUT CURRENT (mA)
INPUT CURRENT (mA)
TA = 25°C
0.3
0.2
30
CLASS 3
20
CLASS 2
CLASS 1
0.1
10
0
0
CLASS 1 OPERATION
CLASS 4
40
0.4
Input Current vs Input Voltage
11.0
INPUT CURRENT (mA)
0.5
10.5
85°C
–40°C
10.0
CLASS 0
0
2
4
6
GND VOLTAGE (V)
10
8
0
50
20
30
40
GND VOLTAGE (V)
(RISING)
10
4265 G01
9.5
60
12
14
18
16
GND VOLTAGE (V)
20
4265 G03
4265 G02
Signature Resistance
vs Input Voltage
22
Class Operation vs Time
On Resistance vs Temperature
RESISTANCE = $V = V2 – V1
$I I2 – I1
27 DIODES: HD01
TA = 25°C
IEEE UPPER LIMIT
TA = 25°C
INPUT
VOLTAGE
10V/DIV
1.0
26
RESISTANCE (Ω)
SIGNATURE RESISTANCE (kΩ)
28
LTC4265 + 2 DIODES
25
CLASS
CURRENT
10mA/DIV
24
LTC4265 ONLY
IEEE LOWER LIMIT
3
4
TIME (10μs/DIV)
9
10
7
5
8
6
GND VOLTAGE (V)
0.6
0.4
23
22
V1: 1
V2: 2
0.8
0.2
–50
4265 G05
75
0
25
50
–25
JUNCTION TEMPERATURE (°C)
4265 G06
4265 G04
PWRGD, T2PSE Output Low
Voltage vs Current
0.8
Active High PWRGD
Output Low Voltage vs Current
1.0
TA = 25°C
TA = 25°C
GND – VOUT = 4V
110
CURRENT (mA)
PWRGD (V)
VPWRGD (V)
VT2PSE (V)
0.2
0
Inrush Current vs Input Voltage
115
0.8
0.6
0.4
0.6
0.4
0.2
0
2
6
4
CURRENT (mA)
8
10
4265 G07
100
105
100
95
90
0
0
0.5
1
1.5
CURRENT (mA)
2
4265 G08
85
40
45
50
55
GND VOLTAGE (V)
60
4265 G09
4265f
4
LTC4265
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary
power application. Drive SHDN high to disable LTC4265
operation and corrupt the signature resistance. If unused,
tie SHDN to VIN.
VOUT (Pins 7, 8): Output Voltage Negative Rail. Connects
VOUT to VIN through an internal power MOSFET. Pins 7
and 8 must be electrically tied together at the package.
T2PSE (Pin 2): Type-2 PSE Indicator, Open-Drain. Low
impedance indicates the presence of a Type-2 PSE.
PWRGD (Pin 9): Power Good Output, Open Collector.
High impedance signals power-up completion. PWRGD
is referenced to VOUT and features a 14V clamp.
RCLASS (Pin 3): Class Select Input. Connect a resistor
between RCLASS and VIN to set the classification load
current. (See Table 2.)
PWRGD (Pin 10): Complementary Power Good Output,
Open-Drain. Low impedance signals power up completion.
PWRGD is referenced to VIN.
NC (Pin 4, 11): No Connect.
GND (Pin 12): Input Voltage, Positive Rail. This pin is
connected to the PD positive rail.
VIN (Pins 5, 6): Input Voltage, Negative Rail. Pins 5 and 6
must be electrically tied together at the package.
Exposed Pad (Pin 13): Tie to VIN and PCB heat sink.
BLOCK DIAGRAM
SHDN 1
12 GND
REF
+
CLASSIFICATION
CURRENT LOAD
T2PSE 2
–
EN
25k
14k
11 NC
RCLASS 3
NC 4
10 PWRGD
CONTROL
CIRCUITS
VIN 5
9
PWRGD
8
VOUT
VIN 6
EXPOSED PAD 13
BOLD LINE INDICATES
HIGH CURRENT PATH
7
VOUT
4265 BD
4265f
5
LTC4265
APPLICATIONS INFORMATION
OVERVIEW
50
Power over Ethernet (PoE) continues to gain popularity
as more products are taking advantage of having DC
power and high speed data available from a single RJ45
connector. As PoE continues to grow in the marketplace,
Powered Device (PD) equipment vendors are running into
the 12.95W power limit established by the IEEE 802.3af
standard.
GND (V)
40
30
ON
UVLO
20
10
CLASSIFICATION
DETECTION V2
DETECTION V1
GND – VOUT (V)
50
The IEE802.3at standard establishes a higher power allocation for Power-over-Ethernet while maintaining backwards
compatibility with the existing IEEE802.3af systems. Power
Sourcing Equipments (PSE) and Powered Devices are
distinguished as Type-1 complying with the IEEE 802.3af
power levels, or Type-2 complying with the IEEE 802.3at
power levels. The maximum available power of a Type-2
PD is 25.5W.
TIME
dV = INRUSH
dt
C1
40
30
UVLO
ON
UVLO
20
T = RLOAD C1
10
TIME
GND – PWRGD (V)
TIME
The IEEE802.3at standard also establishes a new method of
acquiring power classification from a PD and communicating the presence of a Type-2 PSE. A Type-2 PSE has the
option of acquiring PD power classification by performing
2-event classification (Layer 1) or by communicating with
the PD over the data line (Layer 2). In turn, a Type-2 PD
must be able to recognize both layers of communications
and identify a Type-2 PSE.
–10
POWER
BAD
–20
PWRGD
TRACKS
GND
–30
–40
POWER
GOOD
PWRGD – VOUT (V)
–50
POWER
BAD
PWRGD
TRACKS
GND
PWRGD TRACKS
VIN
20
POWER
BAD
10
POWER
GOOD
POWER
BAD
IN DETECTION
RANGE
TIME
The LTC4265 is specifically designed to support the front
end of a PD that must operate under the IEEE802.3at
standard. In particular, the LTC4265 provides the T2PSE
indicator bit which recognizes 2-event classification. This
indicator bit may be used to alert the LTC4265 output load
that a Type-2 PSE is present. With an internal signature
resistor, classification circuitry, inrush control, and thermal shutdown, the LTC4265 is a complete PD Interface
solution capable of supporting in the next generation PD
applications.
LOAD, ILOAD
PD CURRENT
INRUSH
CLASSIFICATION
TIME
DETECTION I2
DETECTION I1
I1 =
V1 – 2 DIODE DROPS
V2 – 2 DIODE DROPS
I2 =
25kΩ
25kΩ
ICLASS DEPENDENT ON RCLASS SELECTION
INRUSH = 100mA
ILOAD =
VIN
RLOAD
GND
MODES OF OPERATION
The LTC4265 has several modes of operation depending on
the input voltage applied between the GND and VIN pins.
Figure 1 presents an illustration of voltage and current
waveforms the LTC4265 may encounter with the various
modes of operation summarized in Table 1.
LTC4265
IIN
PSE
RCLASS GND
PWRGD
RCLASS
RLOAD
C1
VOUT
PWRGD
VIN
VOUT
4265 F01
Figure 1. Output Voltage, PWRGD, PWRGD and
PD Current as a Function of Input Voltage
4265f
6
LTC4265
APPLICATIONS INFORMATION
These modes satisfy the requirements defined in the IEEE
802.3af/at specification.
Table 1. LTC4265 Modes of Operation as a Function
of Input Voltage
GND (V)
LTC4265 MODES OF OPERATION
0V to 1.4V
Inactive (Reset After 1st Classification Event)
1.5V to 9.8V
(5.4V to 9.8V)
25k Signature Resistor Detection Before 1st
Classification Event (Mark, 11k Signature
Corrupt After 1st Classification Event)
DETECTION
12.5V to ON/UVLO* Classification Load Current Active
ON/UVLO* to 60V
Inrush and Power Applied To PD Load
>71V
Overvoltage Lockout, 4265 Operations are Disabled
*ON/UVLO includes hysteresis. Rising input threshold, 37.2V Max.
Falling input threshold, 30V Min.
INPUT DIODE BRIDGE
In the IEEE 802.3af/at standard, the modes of operation
reference the input voltage at the PD’s RJ45 connector.
Since the PD must handle power received in either polarity
from either the data or the spare pair, input diode bridges
BR1 and BR2 are connected between the RJ45 connector
and the LTC4265 (Figure 2).
RJ45
1
2
3
POWERED
DEVICE (PD)
INPUT
6
TX+
The input diode bridge introduces a voltage drop that
affects the range for each mode of operation. The LTC4265
compensates for these voltage drops so that a PD built with
the LTC4265 meets the IEEE 802.3af/at-established voltage
ranges. Note that the Electrical Specifications reference
with respect to the LTC4265 package pins.
During detection, the PSE looks for a 25k signature resistor which identifies the device as a PD. The PSE will apply
two voltages in the range of 2.8V to 10V and measures
the corresponding currents. Figure 1 shows the detection
voltages V1 and V2 and the corresponding PD current. The
PSE calculates the signature resistance using the ΔV/ΔI
measurement technique.
The LTC4265 presents its precision, temperature-compensated 25k resistor between the GND and VIN pins, alerting
the PSE that a PD is present and requests power to be
applied. The LTC4265 signature resistor also compensates
for the additional series resistance introduced by the input
diode bridge. Thus a PD built with the LTC4265 conforms
to the IEEE 802.3af/at detection specifications.
T1
BR1
TX–
RX+
TO PHY
RX–
GND
4
SPARE+
5
7
8
BR2
0.1μF
100V
LTC4265
D3
VIN
SPARE–
4265 F02
Figure 2. PD Front End Using Diode Bridges on Main and Spare Inputs
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7
LTC4265
APPLICATIONS INFORMATION
SIGNATURE CORRUPT OPTION
In some designs that include an auxiliary power option,
it is necessary to prevent a PD from being detected by a
PSE. The LTC4265 signature resistance can be corrupted
with the SHDN pin (Figure 3). Taking the SHDN pin high
will reduce the signature resistor below 11k which is an
invalid signature per the IEEE 802.3af/at specification, and
alerts the PSE not to apply power. Invoking the SHDN pin
also ceases operation for classification and disconnects
the LTC4265 load from the PD input. If this feature is not
used, connect SHDN to VIN.
LTC4265
TO
PSE
GND
14k
25k SIGNATURE
RESISTOR
SHDN
VIN
4265 F03
TO AUX
Figure 3. 25k Signature Resistor with Disable
CLASSIFICATION
Classification provides a method for more efficient power
allocation by allowing the PSE to identify a PD power classification. Class 0 is included in the IEEE specification for
PDs that don’t support classification. Class 1-3 partitions
PDs into 3 distinct power ranges. Class 4 includes the new
power range under IEEE802.3at (See Table 2).
During classification probing, the PSE presents a fixed
voltage between 15.5V and 20.5V to the PD (Figure 2).
The LTC4265 asserts a load current representing the PD
power classification. The classification load current is
programmed with a resistor RCLASS that is chosen from
Table 2.
Table 2. Summary of Power Classifications and LTC4265
RCLASS Resistor Selection
CLASS
USAGE
MAXIMUM
POWER LEVELS
AT INPUT OF PD
(W)
NOMINAL
CLASSIFICATION
LOAD CURRENT
(mA)
LTC4265
RCLASS
RESISTOR
(Ω, 1%)
0
Default
0.44 to 12.95
< 0.4
Open
1
Optional
0.44 to 3.84
10.5
124
2
Optional
3.84 to 6.49
18.5
69.8
3
Optional
6.49 to 12.95
28
45.3
4
Optional
12.95 to 25.5
40
30.9
2-EVENT CLASSIFICATION AND THE T2PSE PIN
A Type-2 PSE may declare the availability of high power by
performing 2-event classification (Layer 1) or by communicating over the high speed data line (Layer 2). A Type-2
PD must recognize both layers of communication. Since
Layer 2 communications takes place directly between the
PSE and the LTC4265 load, the LTC4265 concerns itself
only with recognizing 2-event classification.
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LTC4265
APPLICATIONS INFORMATION
GND (V)
40
1st CLASS
2nd CLASS
30
ON
UVLO
20
10
DETECTION V1
DETECTION V2
1st MARK 2nd MARK
INRUSH
PD CURRENT
The PSE repeats this sequence, signaling the 2nd Classification and 2nd mark event occurrence. This alerts the
LTC4265 that a Type-2 PSE is present. The Type-2 PSE
then applies power to the PD and the LTC4265 charges
up the reservoir capacitor C1 with a controlled inrush current. When C1 is fully charged, and the LTC4265 declares
power good, the T2PSE pin presents an active low signal,
or low impedance output with respect to VIN. The T2PSE
output becomes inactive when the LTC4265 input voltage
falls outside the normal operating range.
50
LOAD, ILOAD
1st CLASS
2nd CLASS
40mA
TIME
DETECTION V1
DETECTION V2
50
GND – VOUT (V)
In 2-event classification, a Type-2 PSE probes for power
classification twice. Figure 4 presents an example of a
2-event classification. The 1st classification event occurs
when the PSE presents an input voltage between 14.5V to
20.5V and the LTC4265 presents a class 4 load current.
The PSE then drops the input voltage into the mark voltage range of 6.9V to 10V, signaling the 1st mark event.
The PD in the mark voltage range presents a load current
between 0.25mA to 4mA.
40
1st MARK 2nd MARK
dV = INRUSH
dt
C1
30
UVLO
ON
UVLO
20
T = RLOAD C1
10
SIGNATURE CORRUPT DURING MARK
TIME
GND – T2PSE (V)
As a member of the IEEE802.3at working group, Linear
notes that it is possible for a Type-2 PD to receive a
false indication of a 2-event classification if a PSE port
is pre-charged to a voltage above the detection voltage
range before the first detection cycle. The IEEE working
group modified the standard to prevent this possibility by
requiring a Type-2 PD to corrupt the signature resistance
during the mark event, alerting the PSE not to apply power.
The LTC4265 conforms to this standard by internally
corrupting the signature resistance. This also discharges
the port before the PSE begins the next detection cycle.
TIME
–10
–20
–30
–40
TRACKS
VIN
–50
INRUSH = 100mA
ILOAD =
RCLASS = 30.9Ω
VIN
RLOAD
GND
LTC4265
IIN
PSE
RCLASS GND
RCLASS
RLOAD
VOUT
C1
T2PSE
VIN
VOUT
4265 F04
Figure 4. VOUT, T2PSE, and PD Current
as a Result of 2-event Classification
4265f
9
LTC4265
APPLICATIONS INFORMATION
PD STABILITY DURING CLASSIFICATION
Classification presents a challenging stability problem due
to the wide range of possible classification load current.
The onset of the classification load current introduces a
voltage drop across the cable and increases the forward
voltage of the input diode bridge. This may cause the PD
to oscillate between detection and classification with the
onset and removal of the classification load current.
The LTC4265 prevents this oscillation by introducing a
voltage hysteresis window between the detection and classification ranges. The hysteresis window accommodates
the voltage changes a PD encounters at the onset of the
classification load current, thus providing a trouble-free
transition between detection and classification modes.
The LTC4265 also maintains a positive I-V slope throughout
the classification ranges up to the ON voltage. In the event
a PSE overshoots beyond the classification voltage range,
the available load current aids in returning the PD back
into the classification voltage range. (The PD input may
otherwise be “trapped” by a reverse-biased diode bridge
and the voltage held by the 0.1μF capacitor.)
characteristic that is independent of the PSE behavior.
This ensures a PD using the LTC4265 interoperability
with any PSE.
UNDERVOLTAGE LOCKOUT
The IEEE 802.3af/at specification for the PD dictates a
maximum turn-on voltage of 42V and a minimum turn-off
voltage of 30V. This specification provides an adequate
voltage to begin PD operation, and to discontinue PD operation when the input voltage is too low. In addition, this
specification allows PD designs to incorporate an on-off
hysteresis window to prevent start-up oscillations.
The LTC4265 features an ON-undervoltage lockout (UVLO)
hysteresis window (See Figure 5) that conforms with the
IEEE 802.3af/at specifications and accommodates the
voltage drop in the cable and input diode bridge at the
onset of the inrush current.
LTC4265
TO
PSE
To control the power-on surge currents in the system, the
LTC4265 provides a fixed inrush current, allowing C1 to
ramp up to the line voltage in a controlled manner.
The LTC4265 keeps the PD inrush current below the
PSE current limit to provide a well-controlled power-up
C1
5μF
MIN
+
PD
LOAD
UNDERVOLTAGE
OVERVOLTAGE
LOCKOUT
CIRCUIT
INRUSH CURRENT
Once the PSE detects and optionally classifies the PD, the
PSE then applies powers on the PD. When the LTC4265
input voltage rises above the ON voltage threshold,
LTC4265 connects VOUT to VIN through the internal power
MOSFET.
GND
VOUT
VIN
INPUT
LTC4265
VOLTAGE
POWER MOSFET
0V TO ON*
OFF
>ON*
ON
<UVLO*
OFF
>OVLO
OFF
*INCLUDES ON-UVLO HYSTERESIS
ON THRESHOLD ≅ 36.1V
UVLO THRESHOLD ≅ 30.7V
OVLO THRESHOLD ≅ 71.0V
4265 F05
CURRENT-LIMITED
TURN ON
Figure 5. LTC4265 Undervoltage and Overvoltage Lockout
4265f
10
LTC4265
APPLICATIONS INFORMATION
Once C1 is fully charged, the LTC4265 turns on is internal
MOSFET and passes power to the PD load. The LTC4265
continues to power the PD load as long as the input voltage does not fall below the UVLO threshold. When the
LTC4265 input voltage falls below the UVLO threshold, the
PD load is disconnected, and classification mode resumes.
C1 discharges through the LTC4265 circuitry.
PWRGD PIN WHEN SHDN IS INVOKED
In PD applications where an auxiliary power supply invokes
the SHDN feature, the PWRGD pin becomes high impedance. This prevents the PWRGD pin that is connected to
the “Run” pin of the DC/DC converter from interfering
with the DC/DC converter operations when powered by
an auxiliary power supply.
COMPLEMENTARY POWERGOOD
When LTC4265 fully charges the load capacitor (C1), power
good is declared and the LTC4265 load can safely begin
operation. The LTC4265 provides complementary power
good signals that remain active during normal operation
and are de-asserted when the input voltage falls below
the UVLO threshold, when the input voltage exceeds the
over-voltage lockout (OVLO) threshold, or in the event of
a thermal shutdown. See Figure 6.
The PWRGD pin features an open collector output referenced to VOUT which can interface directly with the “Run”
pin of a DC/DC converter product. When power good is
declared and active, the PWRGD pin is high impedance
with respect to VOUT. An internal 14V clamp protects the
DC/DC converter from an excessive voltage.
The active low PWRGD pin connects to an internal, open
drain MOSFET referenced to VIN and can interface directly
to the shutdown pin of a DC/DC converter product. When
power good is declared and active, the PWRGD pin is low
impedance with respect to VIN.
LTC4265
10 PWRGD
OVLO
ON
UVLO
TSD
CONTROL
CIRCUIT
9
PWRGD
VIN 5
8
VOUT
VIN 6
7
VOUT
BOLD LINE INDICATES HIGH CURRENT PATH
INRUSH COMPLETE
ON < GND < OVLO
AND NOT IN THERMAL SHUTDOWN
POWER
NOT
GOOD
POWER
GOOD
GND < UVLO
GND > OVLO
OR THERMAL SHUTDOWN
4265 F06
Figure 6. LTC4265 Power Good Functional and State Diagram
4265f
11
LTC4265
APPLICATIONS INFORMATION
OVERVOLTAGE LOCKOUT
The LTC4265 includes an overvoltage lockout (OVLO)
feature (Figure 5) which protects the LTC4265 and its load
from an overvoltage event. If the input voltage exceeds the
OVLO threshold, the LTC4265 discontinues PD operation.
Normal operations resume when the input voltage falls
below the OVLO threshold and when C1 is charged up.
The LTC4265 includes a Thermal Protection feature which
protects the LTC4265 from excessive heating. If the
LTC4265 junction temperature exceeds the over-temperature threshold, the LTC4265 discontinues PD operations
and power-good becomes inactive. Normal operation
resumes when the junction temperature falls below the
over-temperature threshold and when C1 is charged up.
THERMAL PROTECTION
EXTERNAL INTERFACE AND COMPONENT SELECTION
The IEEE 802.3af/at specification requires a PD to withstand
any applied voltage from 0V to 57V indefinitely. However,
there are several possible scenarios where a PD may
encounter excessive heating.
Transformer
During classification, excessive heating may occur if the
PSE exceeds the 75ms probing time limit. At turn-on, when
the load capacitor begins to charge, the instantaneous
power dissipated by the PD Interface can be large before
it reaches the line voltage. And if the PD experiences a
fast input positive voltage step in its operational mode
(for example, from 37V to 57V), the instantaneous power
dissipated by the PD Interface can be large.
RJ45
1
2
3
6
4
TX+
8
The increased current levels in a Type-2 PD over a Type-1
increase the current imbalance in the magnetics which
can interfere with data transmission. In addition, proper
termination is also required around the transformer to
provide correct impedance matching and to avoid radiated
and conducted emissions. Transformer vendors such as
14 T1 1
TX–
RX+
RX–
12
3
13
10
2
5
11
4
9
6
BR1
HD01
TO PHY
COILCRAFT
ETHI - 230LD
SPARE+
5
7
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer. For PDs, the
isolation transformer must also include a center tap on
the RJ45 connector side (See Figure 7).
SPARE–
GND
BR2
HD01
C14
0.1μF
100V
D3
SMAJ58A
TVS
LTC4265
VIN
VOUT
C1
VOUT
4265 F07
Figure 7. PD Front-End with Isolation Transformer, Diode Bridges,
Capacitors, and a Transient Voltage Suppressor (TVS).
4265f
12
LTC4265
APPLICATIONS INFORMATION
Bel Fuse, Coilcraft, Halo, Pulse, and Tyco (Table 4) can
assist in selecting an appropriate isolation transformer
and proper termination methods.
Table 4. Power-over-Ethernet Transformer Vendors
VENDOR
CONTACT INFORMATION
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
Coilcraft Inc.
Halo Electronics
Pulse Engineering
1102 Silver Lake Road
Gary, IL 60013
Tel: 847-639-6400
www.coilcraft.com
1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
www.haloelectronics.com
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
www.pulseeng.com
Tyco Electronics
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
www.circuitprotection.com
Input Diode Bridge
Figure 2 shows how two diode bridges are typically connected in a PD application. One bridge is dedicated to the
data pair while the other bridge is dedicated to the spare
pair. The LTC4265 supports the use of either silicon or
Schottky input diode bridges. However, there are tradeoffs
in the choice of diode bridges.
An input diode bridge must exceed the maximum current
the PD application will encounter at the temperature the
PD will operate. Diode bridge vendors typically call out
the operating current at room temperature, but derate the
maximum current with increasing temperature. Consult
the diode bridge vendors for the operating current derating curve.
A silicon diode bridge can consume over 4% of the available
power in some PD applications. Using Schottky diodes can
help reduce the power loss with a lower forward voltage.
A Schottky bridge may not be suitable for some high
temperature PD application. The leakage current has a
voltage dependency that can reduce the perceived signature
resistance. In addition, the IEEE 802.3af/at specification
mandates the leakage back-feeding through the unused
bridge cannot generate more than 2.8V across a 100k
resistor when a PD is powered with 57V.
Sharing Input Diode Bridges
At higher temperatures, a PD design may be forced to
consider larger bridges in a bigger package because the
maximum operating current for the input diode bridge is
drastically de-rated. The larger package may not be acceptable in some space-limited environments.
One solution to consider is to reconnect the diode bridges
so that only one of the four diodes conducts current in
each package. This configuration extends the maximum
operating current while maintaining a smaller package
profiles. Figure 7 shows how to reconnect the two diode
bridges. Consult the diode bridge vendors for the de-rating
curve when only one of four diodes is in operation.
4265f
13
LTC4265
APPLICATIONS INFORMATION
Input Capacitor
Transient Voltage Suppressor
This occurs when the PSE voltage drops quickly. The input
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
The LTC4265 specifies an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can
routinely see excessive peak voltages. To protect the
LTC4265, install a transient voltage suppressor (D3) between the input diode bridge and the LTC4265 as shown
in Figure 7.
The load capacitor can store significant energy when fully
charged. The PD design must ensure that this energy is
not inadvertently dissipated in the LTC4265. For example,
if the GND pin shorts to VIN while the capacitor is charged,
current will flow through the parasitic body diode of the
internal MOSFET and may cause permanent damage to
the LTC4265.
Classification Resistor (RCLASS)
Power Good Interface
The RCLASS resistor sets the classification load current,
corresponding to the PD power classification. Select the
value of RCLASS from Table 2 and connect the resistor
between the RCLASS and VIN pins as shown in Figure 4,
or float the RCLASS pin if the classification load current is
not required. The resistor tolerance must be 1% or better
to avoid degrading the overall accuracy of the classification circuit.
The LTC4265 provides complementary power good signals to simplify the DC/DC converter interface. Using the
power good signal to delay converter operation until the
load capacitor is fully charged is highly recommended to
ensure trouble free start up.
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1μF capacitor (C14 in Figure 7) is used to
meet this AC impedance requirement.
Load Capacitor
The IEEE 802.3af/at specification requires that the PD
maintains a minimum load capacitance of 5μF and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
Figure 8 presents examples of power good interface circuits. The active high PWRGD pin has an open collector
transistor referenced to VOUT while the active low PWRGD
pin has a high voltage, open-drain MOSFET referenced
to VIN. The designer can choose either signal to enable
the DC/DC converter. When using PWRGD, diode D9 and
resistor RS protects the converter shutdown pin from
excessive reverse voltage.
4265f
14
LTC4265
APPLICATIONS INFORMATION
Figure 9 shows two interface options using the T2PSE
pin and the opto-isolator. The T2PSE pin is active low and
connects to an opt-isolater to communicate across the
DC/DC converter isolation barrier. The pull up resistor RP
is sized according to the requirements of the opto-isolator
operating current, the pull-down capability of the T2PSE
pin, and the choice of V+. V+ for example can come from
the PoE supply rail (which the LTC4265 GND is tied to), or
from the voltage source that supplies power to the DC/DC
converter. Option 1 has the advantage of not drawing power
unless T2PSE is declared active.
ACTIVE-HIGH ENABLE
GND
PD
LOAD
LTC4265
TO
PSE
PWRGD
–54V
VIN
RUN
VOUT
ACTIVE-LOW ENABLE
GND
RS
10k
LTC4265
TO
PSE
R9
100k
PWRGD
–54V
PD
LOAD
SHDN
D9
5.1V
MMBZ5231B
GND
V+
VOUT
VIN
TO
PSE
RP
LTC4265
ACTIVE-LOW ENABLE
TO PD LOAD
–54V
GND
LTC4265
TO
PSE
R10
100k
RS
10k
PWRGD
VIN
T2PSE
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
Q1
FMMT2222
D9
MMBD4148
–54V
VIN
VOUT
V+
PD
LOAD
V+
GND
4265 F08
LTC4265
T2PSE
TO
PSE
Figure 8. Power Good Interface Examples
RP
TO PD LOAD
–54V
VIN
VOUT
4265 F09
T2PSE Interface
When a 2-event Classification sequence successfully
completes, the LTC4265 recognizes this sequence, and
provides an indicator bit, declaring the presence of a
Type-2 PSE. The open drain output provides the option
to use this signal to communicate to the LTC4265 load,
or to leave the pin unconnected.
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
Figure 9. T2PSE Interface Examples
4265f
15
LTC4265
APPLICATIONS INFORMATION
Shutdown Interface
To corrupt the signature resistance, the SHDN pin can be
driven high with respect to VIN or connected to GND. If
unused, connect SHDN directly to VIN.
PD applications may also opt for a seamless transition
— that is, without power disruption — between PoE and
auxiliary power.
Exposed Pad
The most common auxiliary power option injects power
between the LTC4265 and the DC/DC converter. Figure 10
presents an example of this application.
The LTC4265 uses a thermally enhanced DFN12 package
that includes an Exposed Pad. The exposed may be electrically connected to VIN and must connect to a printed
circuit board heat sink.
In this example, the auxiliary port injects 48V onto the line
via diode D1. The components surrounding the SHDN pin
are selected so that the LTC4265 disconnects power to the
output when the auxiliary supply reaches 36V.
Auxiliary Power Source
This configuration is an auxiliary-dominant configuration.
That is, the auxiliary power source supplies the power even
if PoE power is already present. This configuration also
provides a seamless transition from PoE to auxiliary power
when auxiliary power is applied, however, the removal of
auxiliary power to PoE power is not seamless.
In some applications, it is desirable to power the PD from
an auxiliary power source such as a wall adapter.
Auxiliary power can be injected into an LTC4265-based PD
at the input of the LTC4265, the output of the LTC4265, or
even the output of the DC/DC converter. In addition, some
PD application may desire auxiliary supply dominance
or may be configured for PoE dominance. Furthermore,
RJ45
1
2
3
6
TX+
Contact Linear Technology applications support for detail
information on implementing a custom auxiliary power
supply.
T1
TVS
+
TX–
RX+
TO PHY
0.1μF
100V
C1
BR1
–
RX–
PD
LOAD
36V
GND
100k
4
SPARE+
+
10k
5
7
8
LTC4265
BR2
SPARE–
–
ISOLATED
WALL
TRANSFORMER
SHDN
10k
VIN
VOUT
+
D1
–
4265 F10
Figure 10. Auxiliary Power Dominant PD Interface
4265f
16
LTC4265
APPLICATIONS INFORMATION
IEEE 802.3at SYSTEM POWER-UP REQUIREMENT
LAYOUT CONSIDERATION FOR THE LTC4265
Under the IEEE 802.3at standard, a PD must operate under
12.95 Watts in accordance with IEEE 802.3af standards
until it recognizes a Type-2 PSE. Initializing PD operation
in 12.95-Watt mode eliminates interoperability issue in
case a Type-2 PD is connects to a Type-1 PSE. Once the
PD recognizes a Type-2 PSE, the IEEE 802.3at standard
requires the PD to wait 80ms in 12.95W operation before
25.5W operation can commence.
The LTC4265 is relatively immune to layout problems.
Here are some recommendations.
MAINTAIN POWER SIGNATURE
In an IEEE 802.3af/at system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically draw
at least 10mA and also have an AC impedance less than
26.25k in parallel with 0.05μF. If one of these conditions
is not met, the PSE may disconnect power to the PD.
Avoid excessive parasitic capacitance on the RCLASS pin
and place resistor RCLASS close to the LTC4265.
Connect the LTC4265 exposed pad to a PC board heat
sink. Make the heat sink as large as possible.
Place the input capacitor and transient voltage suppressor (C14 and D3 in Figure 7) as close to the LTC4265 as
possible.
If using the SHDN pin for auxiliary power application,
separate the SHDN pin from other high voltage connections, like GND and VOUT, to avoid leakage and capacitive
coupling shutting down the LTC4265.
4265f
17
–54V FROM
SPARE PAIR
–54V FROM
DATA PAIR
B1100 s 8 PLCS
30.9Ω
3.01k
29.4k
VCC
30k
100k
4265 TA02a
11.6
11.9
12.0
12.1
12.2
12.3
12.4
77
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (A)
33pF
0.1μF
11.7
38.3k
10k
51k
4.7nF
1nF
SG
•
1
8
•
1μF
100Ω
2.2nF
2kV
•
LTV357TA
GND
25mΩ
47pF
150Ω
•
PA2467NL
4
FDS3572
2.2nF
BAT54
15Ω
MMBT3906 MMBT3904
PE-68386
•
5
15Ω
470pF
2kV
4265 TA02b
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (A)
42V 48V 57V
Output Regulation vs Load Current
VC
GND
SENSE–
SENSE+
FDS2582
79
42V
48V 57V
EXCLUDING BRIDGES
1.8k
PG
OSC SFST CCMP
LT3825
ENDLY
SG
SG
15μF
16V
PGDLY
tON SYNC RCMP
UVLO
FB
12k
20Ω
BAS21
1μF
100V
Efficiency vs Load Current
14k
10μF
100V
11.8
VOUT
383k
+
4.7μH
81
83
85
87
89
91
93
T2PSE
SHDN
VIN
SMAJ58A
LTC4265
GND
RCLASS
0.1μF
100V
GND
OUTPUT (V)
18
EFFICIENCY (%)
High Efficiency 12V Isolated Power Supply
(Contact LTC for 3.3V and 5V Power Supply Applications)
10k
1μF
16V
+
47μF
16V
12V
2A
T2P
(TO MICROCONTROLLER)
4265 TA02
20k
10μF
16V
0.33μH
LTC4265
APPLICATIONS INFORMATION
4265f
LTC4265
PACKAGE DESCRIPTION
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev C)
0.70 p0.05
3.60 p0.05
2.20 p0.05
3.30 p0.05
1.70 p 0.05
PACKAGE OUTLINE
0.25 p 0.05
0.50 BSC
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 p0.10
(2 SIDES)
7
R = 0.115
TYP
0.40 p 0.10
12
R = 0.05
TYP
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
3.00 p0.10
(2 SIDES)
3.30 p0.10
1.70 p 0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
0.75 p0.05
6
0.25 p 0.05
1
(UE12/DE12) DFN 0806 REV D
0.50 BSC
2.50 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4265f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC4265
TYPICAL APPLICATION
PoE-Based Self-Driven Synchronous Forward Power Supply
1mH
DO1608C-105
BAS516
PA2431NL
•
18V
PDZ18B
GND
•
10μH
+
2.2μF
100V
10μF
100V
B1100 s 8 PLCS
•
4.7nF
250V
33k
VCC
–54V
FROM
DATA
PAIR
10k
BAS516
133Ω
50mΩ
237k
SOUT
VIN
OUT
LTC4265
SMAJ58A
30.9Ω
0.1μF
100V
OC
ISENSE
GND
COMP
LT1952
RCLASS
SHDN
VIN
1nF
FDS2582
FDS8880
BAS516
10.0k
Efficiency vs Load Current
5.1Ω
2.2nF
2kV
2k
33k
VCC
22k
4.7nF
PS2801-1-L
BC857BF
SS_MAXDC
PGND
1nF
5.1Ω FDS8880
10nF
VREF
VOUT
T2PSE
5V
5A
220μF
6.3V
PSLVOJ227M(12)
1.5k
FB
SD_VSEC
+
5.1Ω
IRF6217
0.1μF
10μF
16V
–54V
FROM
SPARE
PAIR
6.8μH
PG0702.682
BAS516
GND BLANK
DELAY
1.2k
22.1k
11.3k
0.1μF
ROSC
TLV431A
82k
332k
100pF
158k
158k
95
GND
51k
90
3.65k
0.22μF
5V
20k
EFFICIENCY (%)
T2P (TO MICROCONTROLLER)
85
80
PS22801-1-L
4265 TA03a
75
42V
50V
57V
70
65
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
LOAD (A)
4265 TA03b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1952
LT1952-1
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Adjustable Switching Frequency, Programmable Undervoltage Lockout,
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Autonomous Operation or I2C Control
LTC4259A-1
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with AC Disconnect
AC or DC Disconnect IEEE-Compliant PD Detection and Classification,
Autonomous Operation or I2C Control
LTC4263/LTC4263-1 Single IEEE 802.3af Power over Ethernet Controller
Internal Switch, Autonomous Operation or I2C Control. 15.4W or 30W.
LTC4264
High Power PD Interface Controller with 750mA
Current Limit
750mA Internal Switch, Programmable Classification Current Limit
with disable, Complementary Power Good
LTC4267
LTC4267-1
LTC4267-3
IEEE 802.3af PD Interface with Integrated Switching
Regulator
100V 400mA Internal Switch, Programmable Classification, 200KHz
or 300KHz Constant Frequency PWM, Interface and Switcher Optimized
for IEEE-Compliant PD System.
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High Power PD with Synchronous No Opto Flyback
Controller
750mA Internal Switch, Programmable Class, Current Limit, Synchronous
Programmable Switching Frequency and UVLO, High Efficiency
ThinSOT is a trademark of Linear Technology Corporation.
4265f
20 Linear Technology Corporation
LT 1208 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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© LINEAR TECHNOLOGY CORPORATION 2008