LTC6903/LTC6904
1kHz - 68MHz Serial
Port Programmable Oscillator
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DESCRIPTIO
FEATURES
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The LTC®6903/LTC6904 are low power self contained
digital frequency sources providing a precision frequency
from 1kHz to 68MHz, set through a serial port. The
LTC6903/LTC6904 require no external components other
than a power supply bypass capacitor, and they operate
over a single wide supply range of 2.7V to 5.5V.
1kHz to 68MHz Square Wave Output
0.5% (Typ) Initial Frequency Accuracy
Frequency Error <1.1% Over All Settings
10ppm/°C Typical Frequency Drift Over
Temperature
0.1% Resolution
1.7mA Typical Supply Current (f < 1MHz, VS = 2.7V)
2.7V to 5.5V Single Supply Operation
Jitter <0.4% Typical 1kHz to 8MHz
Easy to Use SPI (LTC6903) or I2C (LTC6904) Serial
Interface
Output Enable Pin
–40°C to 125°C Operation
MS8 Package
The LTC6903/LTC6904 feature a proprietary feedback
loop that linearizes the relationship between digital control
setting and frequency, resulting in a very simple frequency
setting equation:
2078(Hz)
f = 2OCT •
;1kHz < f < 68MHz
DAC
2 –
1024
Where OCT is a 4-bit digital code and DAC is a 10-bit digital
code.
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APPLICATIO S
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The LTC6903 is controlled by a convenient SPI compatible
serial interface. The LTC6904 uses an industry standard
I2C compatible interface.
Precision Digitally Controlled Oscillator
Power Management
Direct Digital Frequency Synthesis (DDS)
Replacement
Replacement for DAC and VCO
Switched Capacitor Filter Clock
, LTC and LT are registered trademarks of Linear Technology Corporation.
U.S. Patent Numbers 6342817 and 6614313.
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TYPICAL APPLICATIO
LTC6903 Frequency Error
Distribution
A Microcontroller Controlling Its Clock
40
VS = 3V
TA = 25°C
f = 1039Hz
443
30 UNITS
TESTED
5V
5V
0.1µF
GND
OSC1/CLKIN
OSC2/CLKOUT
MCLR/VP–P RC5/SDO
SDI
VDD
VSS
VSS
RC3/SCK/SCL
RC2/CCP1
V+
OE
LTC6903
UNITS
10k
MICROCONTROLLER
10Ω
SCK
CLK
SEN
CLK
1µF
20
10
0.01µF
PIC16F73
POWER-UP CLOCK
FREQUENCY IS 1039Hz
6903 TA01
0
–1.0
0
0.5
–0.5
FREQUENCY ERROR (%)
1.0
6903 TA01b
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LTC6903/LTC6904
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Total Supply Voltage (V+ to GND) .............................. 6V
Maximum Voltage on any Pin
........................... (GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V)
Output Short Circuit Duration (Note 2) ............ Indefinite
Operating Temperature Range (Note 3)
LTC6903CMS8/LTC6904CMS8 ........... –40°C to 85°C
LTC6903IMS8/LTC6904IMS8 ............. –40°C to 85°C
LTC6903HMS8/LTC6904HMS8 ......... –40°C to 125°C
Specified Temperature Range (Note 4)
LTC6903CMS8/LTC6904CMS8 ........... –40°C to 85°C
LTC6903IMS8/LTC6904IMS8 ............. –40°C to 85°C
LTC6903HMS8/LTC6904HMS8 ......... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10sec)................... 300°C
ORDER PART
NUMBER
LTC6903CMS8
LTC6903IMS8
LTC6903HMS8
LTC6904CMS8
LTC6904IMS8
LTC6904HMS8
TOP VIEW
GND
SDI
SCK
SEN/ADR*
1
2
3
4
8
7
6
5
V+
OE
CLK
CLK
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 200°C/W
MS8 PART MARKING*
LTABN
LTAES
* SEN (LTC6903)
ADR (LTC6904)
*The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V + = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
∆fi
∆f
Initial Frequency Accuracy
Total Frequency Accuracy (Note 7)
f = 1.039kHz, V + = 3V, CLOAD = 5pF
Single Output Active:
Over All Settings, V + = 2.7V, CLOAD = 5pF
Over All Settings, V + = 5.5V, CLOAD = 5pF
LTC6903CMS8, LTC6904CMS8:
Over All Settings, V + = 2.7V, CLOAD = 5pF
Over All Settings, V + = 5.5V, CLOAD = 5pF
LTC6903HMS8, LTC6903IMS8,
LTC6904HMS8, LTC6904IMS8:
Over All Settings, V + = 2.7V, CLOAD = 5pF
Over All Settings, V + = 5.5V, CLOAD = 5pF
MIN
TYP
MAX
UNITS
±0.75
%
0.5
0.5
1.1
1.6
%
%
●
●
0.5
0.5
1.65
2
%
%
●
●
0.5
0.5
1.9
2.2
%
%
fMAX
Maximum Operating Frequency
68
MHz
fMIN
Minimum Operating Frequency
1.039
kHz
∆f/∆T
Frequency Drift Over Temperature
∆f/∆V
Frequency Drift Over Supply
Long Term Frequency Stability
Timing Jitter
(See Graph)
10
1.039kHz to 8.5MHz
1.039kHz to 68MHz
Duty Cycle
1.039kHz to 1MHz
1.039kHz to 68MHz
ROUT
Output Resistance
CLK, CLK Pins, V + = 2.7V
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
ppm/°C
0.05
%/V
300
0.4
1
ppm/√kHr
%
%
●
49
50
50
51
%
%
45
Ω
V + = 5.5V, 4mA Load
V + = 2.7V, 4mA Load
●
●
4.8
2
5.3
2.3
V
V
V + = 5.5V, 1mA Load
V + = 2.7V, 1mA Load
●
●
5.2
2.3
5.45
2.55
V
V
V + = 5.5V, 4mA Load
V + = 2.7V, 4mA Load
●
●
0.15
0.25
0.3
0.45
V
V
V + = 5.5V, 1mA Load
V + = 2.7V, 1mA Load
●
●
0.05
0.05
0.15
0.2
V
V
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LTC6903/LTC6904
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V + = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
tr
Output Rise Time (10% - 90%)
V + = 5.5V, RLOAD = ∞, CLOAD = 5pF
V + = 2.7V, RLOAD = ∞, CLOAD = 5pF
MIN
TYP
1
1
MAX
UNITS
ns
ns
tf
Output Fall Time (10% - 90%)
V + = 5.5V, RLOAD = ∞, CLOAD = 5pF
V + = 2.7V, RLOAD = ∞, CLOAD = 5pF
1
1
ns
ns
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POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. V + = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VS
Supply Voltage
Applied Between V + and GND
●
MIN
IS, SHDN
V+ Supply Current, Shutdown
VS = 2.7V
VS = 5.5V
●
●
IS, DC
V+ Supply Current, Single Output
Enabled
f = 68MHz, 5pF Load, V+ = 2.7V
f < 1MHz, V+ = 2.7V
f = 68MHz, 5pF Load, V+ = 5.5V
f < 1MHz, V+ = 5.5V
●
●
●
●
TYP
MAX
UNITS
5.5
V
0.25
0.6
0.6
2.2
mA
mA
3.6
1.7
7
1.9
7
3.1
15
4.5
mA
mA
mA
mA
2.7
SERIAL PORT ELECTRICAL CHARACTERISTICS+
The ● denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. V = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
Min High Level Input Voltage
SEN, SCK, SDI Pins
●
VIL
Max Low Level Input Voltage
SEN, SCK, SDI Pins
●
IIN
Digital Input Leakage
SEN, SCK, SDI Pins
●
TYP
MAX
0.67 V+
0.33 V+
UNITS
V
V
10
µA
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TI I G CHARACTERISTICS +The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. V = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
LTC6903 (Notes 5, 6)
MIN
TYP
MAX
UNITS
fSCK
Serial Port Clock Frequency
●
20
MHz
tCKHI
Min Clock High Time
●
25
ns
tCKLO
Min Clock Low Time
●
25
ns
tsu
Min Setup Time - SDI to SCK
●
10
ns
thLD
Min Hold Time - SCK to SDI
●
10
ns
tLCH
Min Latch Time - SEN to SEN
●
400
ns
tFCK
Min First Clock - SEN to SCK
●
20
ns
100
kHz
µs
µs
µs
µs
LTC6904 (Notes 5, 6)
fSMB
SMBus Operating Frequency
tBUF
Bus Free Time Between Stop and Start Condition
tHD, STA
Hold Time After (Repeated) Start Condition
tSU, STA
Repeated Start Condition Setup Time
tSU, STO
Stop Condition Setup Time
●
●
●
●
●
10
4.7
4.0
4.7
4.0
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LTC6903/LTC6904
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TI I G CHARACTERISTICS +The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. V = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
MIN
LTC6904 (Notes 5, 6)
tHD, DAT
Data Hold Time
tSU, DAT
Data Setup Time
tLOW
Clock Low Period
tHIGH
Clock High Period
tf
Clock, Data Fall Time
tr
Clock, Data Rise Time
●
●
●
●
TYP
300
250
4.7
4.0
●
●
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: A heatsink may be required to keep the junction temperature
below the absolute maximum when the output is shorted indefinitely.
Note 3: The LTC6903CMS8, LTC6904CMS8, LTC6903IMS8, and
LTC6904IMS8 are guaranteed functional over the operating temperature
range of –40°C to 85°C. The LTC6903HMS8 and LTC6904HMS8 are
guaranteed functional over the extended operating temperature range of
–40°C to 125°C.
Note 4: The LTC6903CMS8 and LTC6904CMS8 are guaranteed to meet
the specified performance limits over the 0°C to 70°C temperature range
MAX
UNITS
50
300
1000
ns
ns
µs
µs
ns
ns
and are designed, characterized and expected to meet the specified
performance from –40°C to 85°C but are not tested or QA sampled at
these temperatures. The LTC6903IMS8 and LTC6904IMS8 are guaranteed
to meet the specified performance limits over the –40°C to 85°C
temperature range. The LTC6903HMS8 and LTC6904HMS8 are
guaranteed to meet the specified performance limits over the –40°C to
125°C temperature range.
Note 5: All values are referenced to VIH and VIL levels.
Note 6: Guaranteed by design and not subject to test.
Note 7: Parts with tighter frequency accuracy are available. Consult LTC
Marketing for details.
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TYPICAL PERFOR A CE CHARACTERISTICS
Differential Nonlinearity
Frequency vs Temperature
1.0
0.8
0.8
0.08
0.6
0.06
0.4
0.04
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
FREQUENCY (%)
1.0
0.10
DIFFERENTIAL NONLINEARITY (LSB)
INTEGRAL NONLINEARITY (LSB)
Integral Nonlinearity
0.2
0
–0.2
200
400
600
DAC SETTING
800
1000
6903 G01
0
–0.02
–0.4
–0.04
–0.6
–0.06
–0.8
–0.08
–1.0
0
0.02
0
200
400
600
DAC SETTING
800
1000
6903 G01
–0.10
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
100 120
6903 G03
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LTC6903/LTC6904
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Output
Frequency
Peak-to-Peak Jitter vs Frequency
10
Output Resistance vs Supply
Voltage
10
V+ = 3V
60
50
1
0.1
OUTPUT RESISTANCE (Ω)
8
SUPPLY CURRENT (mA)
PEAK-TO-PEAK JITTER (%)
9
7
6
5
4
V+ = 5V
3
V+ = 3V
2
40
30
20
10
1
0.01
0.1
1
10
FREQUENCY (MHz)
100
0
0.001
0.01
0.1
1
FREQUENCY (MHz)
10
6903 G04
100
0
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
6903 G05
6903 G06
Output Waveform at 20MHz
Output Waveform at 68MHz
Output Spectrum at 20MHz
5.5
20
0.5V/DIV
10dB/DIV
0.5V/DIV
0
CL = 10pF
V+ = 3V
–80
15MHz
20MHz
5ns/DIV
3468 G08
CL = 10pF
V+ = 3V
10ns/DIV
3468 G09
25MHz
6903 G07
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PI FU CTIO S
GND (Pin 1): Negative Power Supply (Ground). Should be
tied directly to a ground plane for best performance.
CLK (Pin 5): Auxiliary Clock Output. Frequency set by
serial port.
SDI ( Pin 2 ): Serial Data Input. Data for serial transfer is
presented on this pin.
CLK (Pin 6): Main Clock Output. Frequency set by serial
port.
SCK (Pin 3): Serial Port Clock. Input, positive edge triggered. Clocks serial data in on rising edge.
OE (Pin 7): Asynchronous Output Enable. CLK and CLK are
set LOW when this pin is LOW.
SEN (Pin 4): Serial Port Enable (6903 Only). Input, active
LOW. Initiates serial transaction when brought LOW,
finalizes transaction when brought HIGH after 16 clocks.
V+ (Pin 8): Positive Power Supply. This supply must be
kept free from noise and ripple. It should be bypassed
directly to a ground plane with a quality 0.1µF capacitor.
Additional bypass may be necessary for operation at high
frequency or under larger loads.
ADR (Pin 4): Serial Port Address (6904 Only). Sets the I2C
serial port address.
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LTC6903/LTC6904
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BLOCK DIAGRA
V+
OE
CLK
8
7
6
CLK
5
+
+
–
MASTER
OSCILLATOR
A1
ISET
–
fMO = 68MHz • kΩ
VSET
PROGRAMMABLE
DIVIDER
ISET
V + – VSET
DAC
OCT
SERIAL PORT
1
2
3
GND
SDI
SCK
4
6903 BD
SEN (LTC6903)
ADR (LTC6904)
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THEORY OF OPERATIO
The LTC6903/LTC6904 contain an internal feedback loop
which controls a high frequency square wave VCO operating between 34MHz and 68MHz. The internal feedback
loop frequency is set over an octave by a 10-bit resistor
DAC. The VCO tracks the internal feedback loop frequency
and the output frequency of the VCO is divided by one of
sixteen possible powers of two.
frequency ranges is very low because of the high output
divisor.
The higher frequency settings will display some deterministic jitter from coupling between the control loop and the
output. This shows up in the frequency spectrum as spurs
separated from the fundamental frequency by 1MHz to
2MHz.
Higher VCO frequencies and lower output divider settings
can result in higher output jitter. Random jitter at the lower
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APPLICATIO S I FOR ATIO
Frequency Setting Information
The frequency output of the LTC6903/LTC6904 is determined by the following equation:
f = 2OCT •
2078(Hz)
DAC
2 –
1024
where DAC is the integer value from 0-1023 represented
by the serial port register bits DAC[9:0] and OCT is the
integer value from 0-15 represented by the serial port
register bits OCT [3:0].
Use the following two steps to choose binary numbers
“OCT” and “DAC” in order to set frequency “f”:
1) Use Table 1 to Choose “OCT” or use the following
formula, rounding down to the integer value less than or
equal to the result.
f
OCT = 3.322 log
1039
2) Choose “DAC” by the following formula, rounding DAC
to the nearest integer:
DAC = 2048 –
2078(Hz) • 2(10 + OCT)
f
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LTC6903/LTC6904
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APPLICATIO S I FOR ATIO
Table 1. Output Frequency Range vs OCT Setting
(Frequency Resolution 0.001 • f)
f≥
f<
OCT
34.05MHz
68.03MHz
15
17.02MHz
34.01MHz
14
8.511MHz
17.01MHz
13
4.256MHz
8.503MHz
12
2.128MHz
4.252MHz
11
1.064MHz
2.126MHz
10
532kHz
1063kHz
9
266kHz
531.4kHz
8
133kHz
265.7kHz
7
66.5kHz
132.9kHz
6
33.25kHz
66.43kHz
5
16.62kHz
33.22kHz
4
8.312kHz
16.61kHz
3
4.156kHz
8.304kHz
2
2.078kHz
4.152kHz
1
1.039kHz
2.076kHz
0
For example, to set a frequency of 6.5MHz, first look at
Table 1 to find an OCT value. 6.5MHz falls between
4.25MHz and 8.5MHz yielding an OCT value of 12 or 1100.
Substituting the OCT value of 12 and the desired frequency
of 6.5MHz into the previous equation results in:
2078(Hz) • 2(10 +12)
DAC = 2048 –
= 707.113
6.5e6(Hz)
Rounding 707.113 to the nearest integer yields a DAC
value of 707 (or a 10-bit digital word of 1011000011.)
clock frequency. This helps to minimize jitter and subharmonics at the output of the device. In the highest
frequency ranges, the division ratio is reduced, which will
result in greater cycle-to-cycle jitter as well as spurs at the
internal sampling frequency. Because the internal control
loop runs at 1MHz to 2MHz without regard to the output
frequency, output spurs separated from the set frequency
by 1MHz to 2MHz may be observed. These spurs are
characteristically more than 30dB below the level of the set
frequency.
Frequency Settling
When frequency settings change, the settling time and
shape differ depending on which bits are changed. Changing only the OCT bits will result in an instantaneous change
in frequency for OCT values below 10. Values of 10 and
above may take up to 100µs to settle due to the action of
internal power conservation circuitry.
Changing the DAC bits will result in a smooth transition
between the frequencies, occupying at most 100µs, with
little overshoot.
Changing both the OCT and DAC bits simultaneously may
result in considerable excursion beyond the frequencies
requested before settling.
It should be noted that changing the DAC bits at the lower
frequency ranges will result in a seemingly instantaneous
frequency change because the settling time depends on
the internal loop frequency rather than the set frequency.
Power Supply Bypass
When power is first applied to the LTC6903/LTC6904, all
register values are automatically reset to 0. This results in
an output frequency of 1.039kHz with both outputs active.
In order to obtain the accuracies represented in this
datasheet, it is necessary to provide excellent bypass on
the power supply. Adequate bypass is a 1µF capacitor in
parallel with a 0.01µF capacitor connected within a few
millimeters of the power supply leads.
Output Spectrum
Monotonicity and Linearity
In most frequency ranges, the output of the LTC6903/
LTC6904 is generated as a division of the higher internal
The DAC in the LTC6903/LTC6904 is guaranteed to be
10-bit monotonic. Nonlinearity of the DAC is less than 1%.
Power Up State
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LTC6903/LTC6904
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APPLICATIO S I FOR ATIO
Additionally, the LTC6903/LTC6904 is guaranteed to be
monotonic when switching between octaves with the OCT
setting bits. For example, the frequency output with a DAC
setting of “1111111111” and an OCT setting of “1100” will
always be lower than the frequency output with a DAC
setting of “0000000000” and an OCT setting of “1101”.
Linearity at these transition points is typically around
3␣ LSBs.
Output Control
The CLK and CLK outputs of the LTC6903/LTC6904 are
individually controllable through the serial port as
described in Table 2 below. The low power mode may also
be accessed through these control bits. It is preferred that
unused outputs be disabled in order to reduce power
dissipation and improve accuracy.
Disabling an unused output will improve accuracy of
operation at frequencies above 1MHz. An unused output
running with no load typically degrades frequency accuracy up to 0.2% at 68MHz. An unused output running into
a 5pF load typically degrades frequency accuracy up to
0.5% at 68MHz.
Output Loading and Accuracy
Improper loading of the outputs of the LTC6903/LTC6904,
especially with poor power supply bypassing, will result in
accuracy problems. At low frequencies, capacitive loading
of the output is not a concern. At frequencies above 1MHz,
attention should be paid to minimize the capacitive load on
the CLK and CLK pins.
Table 2. Output Configuration
The LTC6903/LTC6904 is designed to drive up to 5pF on
each output with no degradation in accuracy. 5pF is
equivalent to one to two HC series logic inputs. A standard
10x oscilloscope probe usually presents between 10pF
and 15pF of capacitive load.
CNF1
CNF0
CLK
CLK
0
0
0
ON
CLK + 180°
1
OFF
ON
1
0
ON
OFF
1
1
Powered-Down*
*Powered-Down: When in this mode, the chip is in a low power state and will require approximately 100µs
to recover. This is not the same effect as the OE pin, which is fast, but uses more power supply current.
It is strongly suggested that a high speed buffer is used
when driving more than one or two logic inputs, when
driving a line more than 5 centimeters in length, or a
capacitive load greater than 5pF.
Serial Port Bitmap (LTC6903/LTC6904)
(All serial port register bits default LOW at power up)
Table 3
D15
D14
D13
D12
D11
D10
D9
D8
OCT3
OCT2
OCT1
OCT0
DAC9
DAC8
DAC7
DAC6
D7
D6
D5
D4
D3
D2
D1
D0
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
CNF1
CNF0
Timing Diagram (LTC6903)
SEN
SCK
SDI
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
6903 TD01
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LTC6903/LTC6904
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APPLICATIO S I FOR ATIO
Serial Port Register Description
Writing Data (LTC6903 Only)
OCT[3:0] - Frequency Divider Setting. (See Frequency
Setting Section)
When the SEN line is brought LOW, serial data presented
on the SDI input is clocked in on the rising edges of SCK
until SEN is brought HIGH. On every eighth rising edge of
SCK, the preceding 8-bits of data are clocked into the
internal register. It is therefore possible to clock in only the
8 {D15 - D8} most significant bits of data rather than
completing an entire transfer.
DAC[9:0] - Master Oscillator Frequency Setting. (See
Frequency Setting Section)
CNF[1:0] - Output Configuration - This controls outputs
CLK and CLK according to Table 2.
The serial data transfer starts with the most significant bit
and ends with the least significant bit of the data, as shown
in the timing diagram.
LTC6903 SPI Compatible Interface
A serial data transfer is composed of sixteen (16) bits of
data labeled D15 through D0. D15 is the first bit of data
presented in each transaction. All serial port register bits
are set LOW on power-up.
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TI I G DIAGRA S
Timing Diagram (LTC6904)
SDA
tSU, STA
tSU, DAT
tLOW
tBUF
tSU, STO
tHD, STA
tHD, DAT
6903 TD02
SCL
tHIGH
tHD, STA
tr
tf
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Typical LTC6904 Input Waveform—Programming Frequency to 68MHz (ADR Pin Set LOW)
ADDRESS
OCT3 OCT2 OCT1 OCT0 DAC9 DAC8 DAC7 DAC6
0
0
1
0
1
1
ADR
WR
DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 CNF1 CNF0
SDA
0
0
1
0
1
1
1
0
ACK
1
1
1
1
1
1
1
1
ACK
1
1
1
1
1
1
0
0
ACK
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
START
STOP
6903 TD03
69034fa
9
LTC6903/LTC6904
U
TYPICAL APPLICATIO S
LTC6904 I2C Interface
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
line during the Acknowledge clock pulse so that it remains
a stable LOW during the HIGH period of this clock pulse.
The LTC6904 communicates with a host (master) using
the standard I2C 2-wire interface. The Timing Diagram
shows the timing relationship of the signals on the bus.
The two bus lines, SDA and SCL, must be high when the
bus is not in use. External pull-up resistors or current
sources, such as the LTC1694 SMBus Accelerator, are
required on these lines. If the I2C interface is not driven
with a standard I2C compatible device, care must be taken
to ensure that the SDA line is released during the ACK
cycle to prevent bus contention.
Write Word Protocol
The master initiates communication with the LTC6904
with a START condition and a 7-bit address followed by the
Write Bit (Wr) = 0. The LTC6904 acknowledges and the
master delivers the most significant data byte. Again the
LTC6904 acknowledges and the data is latched into the
most significant data byte input register. The master then
delivers the least significant data byte. The LTC6904
acknowledges once more and latches the data into the
least significant data byte input register. Lastly, the master
terminates the communication with a STOP condition.
The LTC6904 is a receive-only (slave) device. The master
can communicate with the LTC6904 using the Write Word
protocols as explained later.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA
from high to low while SCL is high.
Slave Address
The LTC6904 can respond to one of two 7-bit addresses.
The first 6 bits (MSBs) have been factory programmed to
001011. The address pin, ADR (Pin 4) is programmed by
the user and determines the LSB of the slave address, as
shown in the table below:
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another SMBus device.
ADR (Pin 4)
LTC6904 Address
Acknowledge
0
0010111
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
1
0010110
Write Word Protocol Used by the LTC6904
1
7
1
1
8
1
8
1
1
S
Slave Address
Wr
A
MS Data Byte
A
LS Data Byte
A
P
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition
6903 AI01
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10
LTC6903/LTC6904
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.42 ± 0.038
(.0165 ± .0015)
TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.65
(.0256)
BSC
8
7 6 5
0.52
(.0205)
REF
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
1
2 3
4
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.127 ± 0.076
(.005 ± .003)
MSOP (MS8) 0204
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
69034fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC6903/LTC6904
U
TYPICAL APPLICATIO
Wide Range Time Interval Generator (1.97 Seconds to 4 Microseconds)
1
fCLK
< TRIGGER PULSE WIDTH < OUTPUT PULSE WIDTH
+
V
4
TRIG
2
V+
3
C2
0.1µF
1
V+
GND
D
PS
Q
U4
CLK R
1
8
Q
5
6
74HC74-A
PHILIPS SEMICONDUCTOR
C1
0.1µF
2
SDI
3
SCK
4
SEN
SDI
OE
U6
LTC6903
7
V+
16
SCK
CLK
SEN
CLK
6
10
fCLK
CLK
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
5
11
MR
8
V+
C3
0.1µF
9
7
6
5
3
2
4
13
12
14
15
1
10
16
4
3
2
1
15
14
13
12
11
10
9
7
74HC4040
PHILIPS
SEMICONDUCTOR
D0
D1
D2
D3
D4
D5
D6
D7
S0
S1
S2
OE
OUTPUT 2n
PULSE = f
CLK
WIDTH
Y
Y
12
6
11
5
QOUT
D
PS
Q
U5
CLK R
Q
9
8
VOUT
VOUT
13
V+
U1
74HC74-B
PHILIPS
SEMICONDUCTOR
8
74HC251
PHILIPS
SEMICONDUCTOR
6903 TA02
S0
S1
S2
MUX SELECT ADDRESS LINES
MUX Inputs
S2
S1
S0
n
Output
Pulsewidth
0
1
0
0
0
1
0
0
0
4
5
6
16/fCLK
32/fCLK
64/fCLK
1
0
1
0
1
0
0
1
0
1
1
1
7
8
9
10
128/fCLK
256/fCLK
512/fCLK
1024/fCLK
1
1
1
11
2048/fCLK
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1799
1kHz to 30MHz ThinSOT™ Oscillator
Single Output, Higher Frequency Operation
LTC6900
1kHz to 20MHz ThinSOT Oscillator
Single Output, Lower Power
LTC6902
Multiphase Oscillator with Spread Spectrum Modulation
2, 3 or 4-Phase Outputs
ThinSOT is a trademark of Linear Technology Corporation
69034fa
12
Linear Technology Corporation
LT/TP 0404 1K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003