INTEGRATED CIRCUITS LVT22V10 3V high speed, universal PLD device Product specification Supersedes data of 1996 Mar 12 IC13 Data Handbook 1998 Feb 10 Philips Semiconductors Product specification 3V high speed, universal PLD device FEATURES LVT22V10 PIN CONFIGURATIONS • Fastest 3V PLD • Supports 3/5V mixed systems • Low ground bounce (<1.1V worst case) • Live insertion/extraction permitted • Bus-hold data inputs eliminate the need for external pull-up D and N Packages I0/CLK 1 24 VCC I1 2 23 F9 I2 3 22 F8 I3 4 21 F7 I4 5 20 F6 I5 6 19 F5 I6 7 18 F4 I7 8 17 F3 I8 9 16 F2 resistors to hold unused inputs • Metastable hardened device • High output drive capability: 32mA/–16mA • Varied product term distribution with up to 16 product terms per output for complex functions • Programmable output polarity • Available in 300 mil-wide 24-pin Plastic Small Outline Package • Design support provided for third party CAD development and programming hardware I9 10 15 F1 I10 11 14 F0 GND 12 13 I11 N = Plastic Dual In-Line Package (300mil-wide) D = Plastic Small Outline Large (300mil-wide) Package DESCRIPTION A Package (standard) The LVT22V10 is a versatile PAL device fabricated on the Philips BiCMOS QUBiC process. The QUBiC process produces very high speed 3V devices (7.5ns) which have excellent noise characteristics. Ground bounce of an output held low while the remaining 9 outputs switch from high to low is typically less than 0.7V. VCC bounce of an output held high while the remaining 9 outputs switch from low to high is typically less than 1.0V. The LVT22V10 was designed to support mixed 3/5V systems. The inputs are capable of handling 7V while the outputs can be pulled up to 7V. I2 I1 4 3 CLK/ I0 NC VCC F9 F8 2 1 28 27 26 I3 5 25 F7 I4 6 24 F6 I5 7 23 F5 NC 8 22 NC I6 9 21 F4 GND 10 20 F3 I8 11 The designer can interface directly from 5V outputs (CMOS full rail or totem pole) to a 3V LVT input. A 3V LVT output can drive a 5V TTL input directly, or in the case of a CMOS input, the LVT output can interface with the use of an external pull-up resistor. Finally, no external pull-up resistors are needed on unused input pins due to a bus-hold data structure designed into the LVT input. 19 F2 14 15 16 17 18 12 13 I9 I10 GND NC I11 F0 F1 A = Plastic Leaded Chip Carrier A Package (evolutionary) The LVT22V10 has been designed with high drive outputs (32mA sink and 16mA source currents), which allows for direct connection to a backplane bus. This feature eliminates the need for additional, standalone bus drivers, which are traditionally required to boost the drive of a standard PLDs. The LVT22V10 outputs are designed to support Live Insertion/Extraction into powered up systems. The output is specially designed so that during VCC ramp, the output remains 3-Stated until VCC 2.1V. At that time the outputs become fully functional depending upon device inputs. (See DC Electrical Characteristics, Symbol IPU/PD, Page 5). In addition when an LVT22V10 output is tied to a 5V bus, no bus current is loaded. I2 I1 4 3 CLK/ I0 VCC VCC F9 F8 2 1 28 27 26 I3 5 25 F7 I4 6 24 F6 I5 7 23 F5 GND 8 22 GND I6 9 21 F4 I7 10 20 F3 I8 11 The LVT22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. 19 F2 14 15 16 17 18 12 13 I9 I10 GND GND I11 F0 F1 A = Plastic Leaded Chip Carrier This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an “Output Macro Cell” (OMC) which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. SP00436 PAL is a registered trademark of Advanced Micro Devices, Inc. 1998 Feb 10 2 853-1759 18947 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 ORDERING INFORMATION PACKAGES ORDER CODE DWG NUMBER 24-Pin Plastic DIP (300mil) LVT22V10-7N (8.0ns device) SOT222-1 28-Pin PLCC (standard pinout) LVT22V10B7A (7.5ns device) SOT261-3 28-Pin PLCC (evolutionary pinout) LVT22V10-7A (7.5ns device) SOT261-3 24-Pin Plastic SOL LVT22V10-7D (8.0ns device) SOT137-1 PIN LABEL DESCRIPTIONS SYMBOL THERMAL RATINGS DESCRIPTION TEMPERATURE I1 – I11 Dedicated Input Maximum junction 150°C F0 – F9 Macro Cell Input/Output Maximum ambient 75°C Clock Input/Dedicated Input Allowable thermal rise ambient to junction 75°C CLK/I0 VCC Supply Voltage GND Ground NC OPERATING RANGES RATINGS No Connection SYMBOL PARAMETER UNIT VCC Supply voltage Tamb Operating free-air temperature MIN MAX +3.0 +3.6 VDC 0 +75 °C ABSOLUTE MAXIMUM RATINGS1 SYMBOL RATINGS PARAMETER MIN MAX UNIT VCC Supply voltage2 –0.5 +4.6 VDC VIN Input voltage2 –0.5 7 VDC VOUT Output voltage3 –0.5 5.5 VDC IIN Input currents –30 +30 mA IOUT Output currents +100 mA Tstg Storage temperature range +150 °C –65 NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. 2. Except in programming mode. 3. Outputs can be pulled up to 7V via external pull-up resistor. 1998 Feb 10 3 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 TEST CIRCUIT AND WAVEFORMS 6.0V VCC OPEN VIN RL VOUT PULSE GENERATOR GND tW 90% NEGATIVE PULSE 90% VM VM 10% 10% D.U.T. RT 0V CL tTHL (tF) RL tTLH (tR) tTLH (tR) POSITIVE PULSE tPLH/tPHL Open tPLZ/tPZL 6V tPHZ/tPZH GND VM VM 10% tW 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. LVT RT = Termination resistance should be equal to ZOUT of pulse generators. 1998 Feb 10 AMP (V) 90% 10% SWITCH POSITION SWITCH tTHL (tF) 90% Test Circuit for 3-State Outputs TEST AMP (V) Amplitude Rep. Rate tW tR tF 3.0V 10MHz 500ns 2.5ns 2.5ns SP00385 4 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 DC ELECTRICAL CHARACTERISTICS Over operating ranges. SYMBOL PARAMETER LIMITS TEST CONDITIONS1 MIN MAX UNIT Input voltage VIL Low VCC = MIN VIH High VCC = MAX VI Clamp 0.8 V 2.0 VCC = MIN, IIN = –18mA V –1.2 V Output voltage VCC = MIN to MAX, VI = VIH or VIL VOH High-level output voltage VCC = MIN MIN, VI = VIH or VIL VCC = MIN to MAX, VI = VIH or VIL VOL Low-level output voltage VCC = MIN MIN, VI = VIH or VIL IOH = –100 µA VCC–0.2 V IOH = –16mA 2.0 V IOH = –5.5 mA 2.4 V IOL = 100µA 0.2 V IOL = 32 mA 0.5 V IOL = 16 mA 0.4 V Input current IIL Low VCC = MAX, VIN = 0.0V –10 µA IIH High VCC = MAX, VIN = VCC 10 µA II Max input current VCC = MAX, VIN = 5.5V 10 µA II Pin 1 (program) VCC = MAX, VIN = 5.5V 20 µA IBHL Bus hold low sustaining current2 VCC = 3V, VI = 0.8V 75 µA IBHH Bus hold high sustaining current3 VCC = 3V, VI = 2V –75 µA IBHLO Bus hold low overdrive current4, 9 VCC = 3.6V 500 µA VCC = 3.6V –500 µA IBHHO Bus hold high overdrive current5, 9 Output current IOFF Output off current IEX Current into an output in high state when VO > VCC IPU/PD Power-up/down 3-State output current8 VCC = 0V, VI or VO = 0 to 4.5V ±10 µA VO = 5.5V, VCC = 3.0V ±100 µA VCC <1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = X 100 µA VIN = VIL or VIH, VOUT = 5.5V 10 µA VIN = VIL or VIH, VOUT =0V –10 µA –30 –220 mA MIN TYP 2.2 2.3 VCC = MAX leakage6 IOZH Output IOZL Output leakage6 ISC Short circuit7 ICC VCC supply current VOUT = 0.5V VCC = 3.6V, Outputs enabled, VI = VCC or GND; IO = 0 Ground/VCC Bounce VOHV Maximum dynamic VOH VOLP Maximum dynamic VOL VCC = 3.0V, 25°C, CL = 50pF (including jig capacitance) VCC = 3.3V,, 25°C,, CL = 50pF (including jig capacitance) 170 mA MAX UNIT V LVT22V10-7 0.7 1.1 V LVT22V10B7 1.0 1.1 V NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. The bus hold circuit can sink at least the minimum low sustaining current at VIL MAX. IBHL should be measured after lowering VIN to GND and then raising it to VIL MAX. 3. The bus hold circuit can source at least the minimum high sustaining current at VIH MIN. IBHL should be measured after raising VIN to VCC and then lowering it to VIH MIN. 4. An external driver must source at least IBHLO to switch this node from low to high. 5. An external driver must sink at least IBHHO to switch this node from high to low. 6. I/O pin leakage is the worst case of IOZX or IIX (where X = H or L). 7. No more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 8. This parameter is valid for any VCC between 0V and 1.2 V with a transition time up to 10 mS. From VCC = 1.2 to VCC = 3.3V ±0.3V a transition time of 100 µS is permitted. X = Don’t care. 9. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where input current may be affected. 1998 Feb 10 5 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 AC ELECTRICAL CHARACTERISTICS Over commercial operating temperature range. SYMBOL LIMITS TEST CONDITIONS1 PARAMETER UNIT MIN Input or feedback to non-registered g output2 PLCC package tPD Input or feedback to non-registered g output2 DIP and SOL packages TYP MAX Active-LOW 7.5 ns Active-HIGH 7.5 ns Active-LOW 8.0 ns Active-HIGH 8.0 ns tS Setup time from input, feedback or SP to Clock tH Hold time tCO Clock to output 5.0 ns tCF Clock to feedback3 3.0 ns tAR Asynchronous Reset to registered output 12.0 ns tARW Asynchronous Reset width 5.0 ns tARR Asynchronous Reset recovery time 5.0 ns tSPR Synchronous Preset recovery time 5.0 ns tWL Width of Clock LOW 3.0 ns tWH Width of Clock HIGH 3.0 ns Maximum frequency; External feedback 1/(tS + tCO)4 95 MHz Maximum frequency; Internal feedback 1/(tS + tCF)4 118 MHz fMAX 5.5 ns 0 ns tEA Input to Output Enable5 8.5 ns tER Disable5 8.5 ns Input to Output Capacitance6 CIN COUT Input Capacitance (Pin 1) VIN = 2.0V Input Capacitance (Others) VIN = 2.0V Output Capacitance VOUT = 2.0V VCC = 3.3V, Tamb = 25°C, f = 1MH 1MHz 6 pF 6 pF 8 pF NOTES: 1. Test Conditions: R1 = 500Ω, R2 =500Ω 2. tPD is tested with switch S1 open and CL = 50pF (including jig capacitance). VIH = 3V, VIL = 0V, VT = 1.5V. 3. Calculated from measured fMAX internal. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.3V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.3V) level with S1 closed. 6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 1998 Feb 10 6 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. PRODUCT FEATURES Low Ground Bounce The Philips Semiconductors BiCMOS QUBiC process results in exceptional noise immunity. Ground bounce is noise that is generated on a non-switching active low output when other outputs on the device switch from high to low. The worst case condition occurs when 9 outputs simultaneously switch from high to low and the tenth output is active low. The ground bounce on this tenth output for Philips LVT22V10 is typically less than 0.7V. Selection is controlled by programmable bit S0 in the Output Macro Cell, and affects both registered and combinatorial outputs. Selection is automatic, based on the design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be Active-HIGH (S0 = 1). Preset/Reset VCC Bounce For initialization, the LVT22V10 has additional Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous Preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the Asynchronous Reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW, independent of the clock. VCC bounce occurs on a non-switching active high output when other outputs are making a low to high transition. This specification is important to consider in 3.3V designs because of the reduced noise margin between VCC and VOH of only 1.3V relative to the traditional 5V system’s noise margin of 3V. The Philips LVT22V10 VCC bounce of an output held high while the remaining 9 outputs switch from low to high is typically less than 1.0V in magnitude. Note that Preset and Reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected. Live Insertion/Extraction Capability There are some inherent problems associated with inserting or extracting an unpowered module from a powered-up, active system. The LVT22V10 outputs have been designed such that any chance of bus contention, glitching or clamping is eliminated. Power-Up Reset All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the LVT22V10 will depend on the programmed output polarity. The VCC rise must be monotonic and the reset delay time is 1–10µs maximum. Detailed information on this feature is provided in an application note AN051: Philips PLDs Support Live Insertion Applications. Security Fuse Bus Hold Input Structure After programming and verification, LVT22V10 designs can be secured by programming the security fuse link. Once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as if every fuse is programmed. Bus Hold is a feature that maintains the input state of the device by incorporating a weak latch into the input structure. This latch maintains the input state until a minimum level of current (called the overdrive current) is supplied to change the input state. This is useful in bus applications where the bus is placed into a high impedance state. The LVT22V10’s inputs, in this high impedance situation, maintain valid logic levels until the bus is actively driven to a new state. Quality and Testability The LVT22V10 offers a very high level of built-in quality. Extra programmable fuses provide a means of verifying performance of all AC and DC parameters. In addition, this verifies programmability and functionality of the device to provide the highest programming and post-programming functional yields. Improved Fuse Verification Circuitry Increases Reliability Philips has developed a new means of testing the integrity of fuses, both blown and intact fuses, which insures that all the fuses have been correctly programmed and that each and every fuse – whether “blown” or “intact” – is at the appropriate and optimal fuse resistance. This dual verify scheme represents a significant improvement over single reference voltage comparisons schemes that have been used for bipolar devices since the late 1980s. Detailed information on this feature is provided in an application note entitled Dual Verify Technique Increases Reliability of PLDs. Technology The BiCMOS LVT22V10 is fabricated with the Philips Semiconductors process known as QUBiC. QUBiC combines an advanced, state-of-the-art 1.0µm (drawn feature size) CMOS process with an ultra fast bipolar process to achieve superior speed and drive capabilities. QUBiC incorporates three layers of Al/Cu interconnects for reduced chip size, and our proven Ti-W fuse technology ensures highest programming yields. Programmable 3-stage Outputs Each output has a 3-Stage output buffer with 3-State control. A product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bidirectional I/O pin, and may be configured as a dedicated input if the buffer is always disabled. Programming Programmable Output Polarity All packages allow Boolean and state equation entry formats, SNAP, ABEL and CUPL also accept, as input, schematic capture format. The LVT22V10 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL CUPL and PALASM 90 design software packages also support the LVT22V10 architecture. The polarity of each macro cell output can be Active-HIGH or Active-LOW, either to match output signal needs or to reduce ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. PALASM is a registered trademark of AMD Corp. 1998 Feb 10 7 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 3. Apply the desired value (VILP/VIHP) to all registered output pins. Leave combinatorial output pins floating. 4. Clock Pin 1 from VILP to VIHP. 5. Remove VILP/VIHP from all registered output pins. 6. Lower pin 2 or 3 to VILP. 7. Enable the output registers according to the programmed pattern. 8. Verify VOL/VOH at all registered output pins. Note that the output pin signal will depend on the output polarity. Output Register Preload The register on the LVT22V10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. The procedure for preloading follows: 1. Raise VCC to 3.3V ± 0.3V. 2. Set pin 2 or 3 to VHH to disable outputs and enable preload. PRELOAD SET-UP LIMITS SYMBOL PARAMETER MIN REC MAX UNIT 9.5 9.5 10 V Low-level input voltage 0 0 0.8 V VIHP High-level input voltage 2.4 3.3 3.6 V tD Delay time 100 200 1000 ns tI/O I/O valid after Pin 2 or 3 drops from VHH to VILP 100 VHH Super-level input voltage VILP ns VHH PINS 2, 3 VILP tD tD REGISTERED OUTPUTS DATA IN tI/O DATA OUT tD tD VIHP VOH VOL VILP VIHP CLOCK tD VILP SP00373 Output Register Preload Waveform 1998 Feb 10 8 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 LVT22V10 TIMING CHARACTERIZATION Normalized tPD vs Temperature (VCC = 3.3V, output capacitance = 50pF, 5 outputs switching) Normalized tCO vs Temperature (VCC = 3.3V, output capacitance = 50pF, 5outputs switching) 1.05 1.10 1.00 Normalized t PD Normalized t CO 1.00 0.95 0.90 0.90 RISE RISE FALL FALL 0.80 0.85 0 25 50 0 75 25 Temperature (°C) 75 Temperature (°C) Normalized tCO vs VCC (temp = 25°C, output capacitance = 50pF, 5 outputs switching) Normalized tPD vs VCC (temp = 25°C, output capacitance = 50pF, 5 outputs switching) 1.20 1.20 1.10 1.10 Normalized t PD Normalized t CO 50 1.00 0.90 1.00 0.90 RISE RISE FALL FALL 0.80 0.80 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 Supply Voltage (V) 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage (V) The timing characterization represents the average values of a representative sample for each parameter. The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design. Philips guarantees the MAX AC CHARACTERIZATION specifications. SP00386 1998 Feb 10 9 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 LVT22V10 TIMING CHARACTERIZATION Delta tCO vs Number of Outputs Switching (VCC = 3.3V, temp = 25°C, output capacitance = 50pF) Delta tPD vs Number of Outputs Switching (VCC = 3.3V, temp = 25°C, output capacitance = 50pF) 100 0.10 0.00 0 –0.10 –100 –0.20 (ns) –0.40 Delta t PD Delta t CO (ps) –0.30 –200 –300 –400 –0.50 –0.60 –0.70 –0.80 –500 –0.90 –600 RISE RISE –1.00 FALL –700 FALL –1.10 1 2 3 4 5 6 7 8 9 10 1 2 3 Number of Outputs Switching 5 6 7 8 9 10 Delta tPD vs Output Capacitance (VCC = 3.3V, temp = 25°C, 5 Outputs Switching) 7.00 6.00 6.00 5.00 5.00 4.00 (ns) 7.00 4.00 3.00 Delta t PD Delta t CO (ns) Delta tCO vs Output Capacitance (VCC = 3.3V, temp = 25°C, 5 Outputs Switching) 3.00 2.00 2.00 1.00 1.00 0.00 0.00 –1.00 RISE –1.00 4 Number of Outputs Switching RISE FALL FALL –2.00 –2.00 10 50 100 200 400 10 Output Capacitance 50 100 200 400 Output Capacitance The timing characterization represents the average values of a representative sample for each parameter. The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design. Philips guarantees the MAX AC CHARACTERIZATION specifications. SP00387 1998 Feb 10 10 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 LOGIC DIAGRAM CLK/I0 1 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 24 VCC 43 AR 0 1 DAR 9 SP Q Q 1 1 0 0 0 1 0 1 23 F9 1 1 0 0 0 1 0 1 22 F8 1 1 0 0 0 1 0 1 21 F7 1 1 0 0 0 1 0 1 20 F6 1 1 0 0 0 1 0 1 19 F5 1 1 0 0 0 1 0 1 18 F4 1 1 0 0 0 1 0 1 17 F3 1 1 0 0 0 1 0 1 16 F2 1 1 0 0 0 1 0 1 15 F1 1 1 0 0 0 1 0 1 14 F0 13 I11 0 1 10 DAR 20 I1 SP Q Q 0 1 2 21 DAR SP 33 I2 Q Q 0 1 3 34 DAR SP Q Q 48 I3 0 1 4 49 DAR SP Q Q 65 I4 0 1 5 66 DAR SP Q Q 82 I5 0 1 6 83 DAR SP Q Q 97 I6 0 1 7 98 DAR SP 110 I7 Q Q 0 1 8 111 DAR 121 I8 SP Q Q 0 1 9 122 DAR 130 SP I9 10 SP 131 I10 11 GND 12 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 NOTE: Programmable connection. 1998 Feb 10 35 36 39 40 Q Q 0 1 43 SP00059 11 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 FUNCTIONAL DIAGRAM CLK/I0 I1 – I11 1 11 PROGRAMMABLE AND ARRAY (44 × 132) 10 12 14 16 16 14 12 10 8 OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 PRESET RESET 8 SP00060A Figure 1. Functional Diagram registered output or combinatorial I/O, Active-HIGH or Active-LOW (see Figure 2). The configuration choice is made according to the user’s design specification and corresponding programming of the configuration bits S0 –S1. Multiplexer controls are connected to ground (0) through a programmable fuse link, selecting the “0” path through the multiplexer. Programming the fuse disconnects the control line from GND and it floats to VCC (1), selecting the “1” path. FUNCTIONAL DESCRIPTION The LVT22V10 allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function. Product terms with all fuses opened assume the logical HIGH state; product terms connected to both True and Complement of any single input assume the logical LOW state. The LVT22V10 has 12 inputs and 10 I/O Macro Cells (Figure 1). The Macro Cell allows one of four potential output configurations, 1998 Feb 10 12 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 OUTPUT MACRO CELL 1 0 1 1 Q 0 0 Q 0 1 AR D CLK SP F S1 S0 OUTPUT CONFIGURATION 0 0 Registered/Active-LOW 0 1 Registered/Active-HIGH 1 0 Combinatorial/Active-LOW 1 1 Combinatorial/Active-HIGH 0 = Unprogrammed fuse 1 = Programmed fuse S1 S0 0 1 SP00375 Figure 2. Output Macro Cell Logic Diagram S0 = 0 S1 = 0 AR D F Q CLK S0 = 0 S1 = 1 F Q SP a. Registered/Active-LOW c. Combinatorial/Active-LOW AR D F Q CLK S0 = 1 S1 = 1 S0 = 1 S1 = 0 F Q SP d. Combinatorial/Active-HIGH b. Registered/Active-HIGH SP00376 Figure 3. Output Macro Cell Configurations Registered Output Configuration Variable Input/Output Pin Ratio Each Macro Cell of the LVT22V10 includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the registered configuration (S1 = 0), the array feedback is from Q of the flip-flop. The LVT22V10 has twelve dedicated input lines, and each Macro Cell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Combinatorial I/O Configuration Any Macro Cell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (S1 = 1). In the combinatorial configuration, the feedback is from the pin. 1998 Feb 10 13 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 metastable event occurs within the flop, the only outward manifestation of the event will be an increased clock-to-Q delay. This delay is a function of the metastability characteristics of the device, defined by τ and TO as described below. Since the outputs never glitch, oscillate, or remain in the linear region, the only metastable failure that can propagate further into the system is when the next flip-flop in the system samples the LVT22V10’s output at precisely the same time it is making a logic transition. By allowing sufficient time for any increased clock-to-Q delay, propagation of metastable failures can be avoided. The following design example illustrates this concept. INTERFACING IN MIXED 3V/5V SYSTEMS 3V Logic Driving 5V Logic The LVT family has outputs that swing virtually between the power supply rails, thereby allowing direct interfacing with TTL switching levels. When interfacing the outputs of any of our 3V logic ICs with standard TTL-level logic inputs (bipolar or CMOS HCT), the output levels from the 3V logic are sufficient to directly drive the 5V logic. When driving CMOS-level devices (such as HC or AC), the output voltage from the 3V logic is insufficient to ensure reliable operation. This problem can be easily resolved by using a pull-up resistor at the interface. Design Example Suppose a designer wants to use the LVT22V10 for synchronizing asynchronous data that is arriving at 2MHz (as measured by a frequency counter), in a 3.3V system that has a clock frequency of 33MHz, at an ambient temperature of 25°C. She has decided that she would like to sample the output of the LVT22V10 15ns after the clock edge to ensure that any clock-to-Q delays that were the result of the LVT22V10 internal metastability resolution circuitry have completed and the outputs have transitioned. The MTBF for this situation can be calculated by using the equation below: 5V Logic Driving 3V Logic Since the LVT ICs do not have protection diodes between their inputs and VCC, the inputs of these devices can therefore withstand higher levels than the supply voltage, and they can be directly connected to 5V CMOS logic outputs. For the LVT family, the combination of low power dissipation with the live insertion feature, bus hold and full 5V input/output capability make this logic ideal for 3.3V backplane interfacing. MTBF = e(t’/τ )/TOFCF1 In this formula, FC is the frequency of the clock, F1 is the average input event frequency, and t’ is the time after the clock pulse that the output is sampled (t’ > TCO). TO and τ are device parameters provided by the semiconductor manufacturer (refer to the following table for the LVT22V10 metastability specifications). TO and τ are derived from tests and can be most nearly be defined as follows: τ is a function of the rate at which a latch in a metastable state resolves that condition. TO is a function of the measurement of the propensity of a latch to enter a metastable state. TO is also a normalization constant, which is a very strong function of the normal propagation delay of the device. INTERFACING 3 VOLT AND 5 VOLT LOGIC FROM 3V to 5V LVT Output 5V to 3V CMOS Rail Totem-Pole Open Drain TO METHOD TTL Inputs Direct CMOS inputs Pull-up LVT Input LVT Input LVT Input Direct Direct Pull-up In this situation the F1 will be twice the data frequency, or 4MHz, because input events consist of both of low and high transitions. Thus, in this case, FC is 33MHz, F1 is 4MHz, τ is 317ps, t’ is 15ns, and TO is 4.27 × 10-3 seconds. Using the above formula the actual MTBF for this situation is 1.26 × 109 seconds or 39 years for the LVT22V10. LVT22V10 METASTABLE HARDENED CHARACTERISTICS Metastable Hardened Characteristics What is metastable hardened? Philips Semiconductors uses the term “metastable hardened” to describe a combination of two characteristic features. The first is a patented Philips circuit that prevents the outputs from glitching, oscillating, or remaining in the linear region under any circumstances, including setup and hold time violations. The second is the flip-flops’ inherent ability of resolving the metastable condition. Philips provides complete data on the LVT22V10’s metastable characteristics Summary The Philips LVT22V10 has on-chip circuitry that completely eliminates any output glitches, oscillations, or other output anomalies associated with metastable conditions. For outputs that are then used to generate clocks, control signals or other asynchronous data this represents an unparalleled level of reliability in a PLD. In addition, a complete set of metastability data is provided, that allows designers the ability to design robust systems where data is synchronously pipelined. With the LVT22V10, any tendency towards internal metastability is resolved by Philips Semiconductors patented circuitry. If a LVT22V10 VALUES FOR τ AND TO VCC 0°C 25°C 75°C τ TO τ TO τ TO 3.0V 829.00ps 1.16E–08 691.00ps 1.09E–07 429.00ps 2.27E–04 3.3V 358.00ps 2.36E–04 317.00ps 4.27E–03 329.00ps 5.75E–03 3.6V 237.00ps 2.66E–01 230.00ps 6.47E–01 250.00ps 1.13E+00 1998 Feb 10 14 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 SWITCHING WAVEFORMS INPUT OR FEEDBACK INPUT OR FEEDBACK VT VT tPD COMBINATORIAL OUTPUT tS tH CLOCK VT VT tCO REGISTERED OUTPUT Combinatorial Output VT Registered Output CLK tS + tCF CLOCK tS LOGIC VT REGISTER tCF Clock to Feedback (fMAX Internal) (See Path at Right) Clock to Feedback INPUT VT tWH tER CLOCK tEA VT VOH – 0.3V OUTPUT VT VOL + 0.3V tWL Clock Width Input to Output Disable/Enable tARW INPUT ASSERTING ASYNCHRONOUS RESET INPUT ASSERTING SYNCHRONOUS PRESET VT tAR REGISTERED OUTPUT VT tS CLOCK VT tARR CLOCK tH tSPR VT VT tCO REGISTERED OUTPUT VT Asynchronous Reset VT Synchronous Preset SP00388 NOTES: 1. VT = 1.5V. 2. Input pulse amplitude 0V to 3.0V. 3. Input rise and fall times 1.5ns max. 1998 Feb 10 15 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 “AND” ARRAY – (I, B) I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B P, D I, B P, D I, B P, D P, D STATE CODE STATE CODE STATE CODE INACTIVE1 O TRUE H COMPLEMENT L STATE DON’T CARE CODE — SP00008 NOTE: 1. This is the initial state. of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. VCC POWER 2.7V tPR REGISTERED ACTIVE-LOW OUTPUT tS CLOCK tWL Power-Up Reset Waveform SP00389 LIMITS SYMBOL PARAMETER tPR Power-up Reset Time tS Input or Feedback Setup Time tWL Clock Width LOW 1998 Feb 10 MIN MAX UNIT 1 µs See AC Electrical Characteristics 16 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 DIP24: plastic dual in-line package; 24 leads (300 mil) 1998 Feb 10 17 SOT222-1 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 PLCC28: plastic leaded chip carrer; 28 leads; pedestal 1998 Feb 10 18 SOT261-3 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 SO24: plastic small outline package; 24 leads; body width 7.5 mm 1998 Feb 10 19 SOT137-1 Philips Semiconductors Product specification 3V high speed, universal PLD device LVT22V10 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 02-98 Document order number: 1998 Feb 10 20 9397 750 03313