STMICROELECTRONICS M24256-BF

M24256-BF M24256-BR
M24256-BW M24256-DR
256 Kbit serial I²C bus EEPROM
with three Chip Enable lines
Features
■
256 Kbit EEPROM addressed through the I2C
bus
■
Supports the I2C bus modes:
– 1 MHz Fast-mode Plus
– 400 kHz Fast mode
– 100 kHz Standard mode
■
Supply voltage ranges:
– 1.7 V to 5.5 V
– 1.8 V to 5.5 V
– 2.5 V to 5.5 V
■
Write Control input
■
Byte and Page Write
■
Random and sequential read modes
■
Self-timed programming cycle
■
Automatic address incrementing
■
Enhanced ESD/latch-up protection
■
More than 1 000 000 write cycles
■
More than 40-year data retention
■
Packages
– ECOPACK® (RoHS compliant)
SO8 (MW)
208 mils width
SO8 (MN)
150 mils width
TSSOP8 (DW)
WLCSP (CS)
UFDFPN8 (MB)
2 × 3 mm (MLP)
March 2010
Doc ID 6757 Rev 21
1/42
www.st.com
1
Contents
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1
3
2/42
2.6.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
Addressing the memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8
Page Write (memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9
Identification Page Write (M24256-DR only) . . . . . . . . . . . . . . . . . . . . . . 17
3.10
Lock Identification Page (M24256-DR only) . . . . . . . . . . . . . . . . . . . . . . . 17
3.11
ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17
3.12
Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19
3.13
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14
Random Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 20
3.15
Current Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 21
3.16
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.17
Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Contents
3.18
Read Identification Page status (locked/unlocked) . . . . . . . . . . . . . . . . . . 22
3.19
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Doc ID 6757 Rev 21
3/42
List of tables
M24256-BF, M24256-BR, M24256-BW, M24256-DR
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
4/42
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code (for memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device select code to access the Identification page (M24256-DR only) . . . . . . . . . . . . . . 11
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC characteristics (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC characteristics (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC characteristics (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SO8W – 8-lead plastic small outline, 208 mils body width, package data . . . . . . . . . . . . . 31
SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 32
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 33
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
WLCSP 0.5 mm pitch, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Available M24256-BR, M24256-BW, M24256-BF products (package,
voltage range, temperature grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Available M24256-DR products (package, voltage range, temperature grade) . . . . . . . . . 37
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C Fast mode (fC = 400 kHz): maximum Rbus value versus
bus parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus
bus parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SO8W – 8-lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . 31
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 32
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 33
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 6757 Rev 21
5/42
Description
1
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Description
The M24256-Bx devices are I2C-compatible electrically erasable programmable memories
(EEPROM). They are organized as 32 Kb × 8 bits.
The M24256-Bx and M24256-DR can decode the type identifier code (1010) in accordance
with the I2C bus definition. The M24256-DR also decodes the type identifier code (1011)
when accessing the identification page.
The device behaves as a slave in the I2C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in Table 2), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Figure 1.
Logic diagram
6##
%%
3$!
-XXX
3#,
7#
633
Table 1.
Signal names
Signal name
6/42
!)G
Function
Direction
E0, E1, E2
Chip Enable
Inputs
SDA
Serial Data
I/O
SCL
Serial Clock
Input
WC
Write Control
Input
VCC
Supply voltage
VSS
Ground
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure 2.
Description
Package connections
E0
E1
E2
VSS
8
7
6
5
1
2
3
4
VCC
WC
SCL
SDA
AI04035e
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Figure 3.
WLCSP connections (top view, marking side, with balls on the underside)
VCC
E1
E0
WC
E2
SDA
SCL
VSS
ai14712
Doc ID 6757 Rev 21
7/42
Signal description
M24256-BF, M24256-BR, M24256-BW, M24256-DR
2
Signal description
2.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 6 indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 6 indicates how
the value of the pull-up resistor can be calculated).
2.3
Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC
or VSS, to establish the device select code. When not connected (left floating), these inputs
are read as Low (0,0,0).
Figure 4.
Device select code
VCC
VCC
M24xxx
M24xxx
Ei
Ei
VSS
VSS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
8/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
2.5
Signal description
VSS ground
VSS is the reference for the VCC supply voltage.
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 8, Table 9 and
Table 10). In order to secure a stable DC supply voltage, it is recommended to decouple the
VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the
VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
2.6.2
Power-up conditions
VCC has to rise continuously from 0 V up to VCC(min) (see Table 8, Table 9 and Table 10),
and the rise time must not vary faster than 1 V/µs.
2.6.3
Device reset
In order to prevent inadvertent write operations during power-up, a power on reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC
reaches an internal reset threshold voltage. This threshold is lower than the minimum VCC
operating voltage defined in Table 8, Table 9 and Table 10.
When VCC passes over the POR threshold, the device is reset and enters the Standby
Power mode. However, the device must not be accessed until VCC reaches a valid and
stable VCC voltage within the specified [VCC(min), VCC(max)] range.
In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops
below the power on reset threshold voltage, the device stops responding to any instruction
sent to it.
2.6.4
Power-down conditions
During power-down (where VCC decreases continuously), the device must be in the Standby
Power mode (mode reached after decoding a Stop condition, assuming that there is no
internal Write cycle in progress).
Doc ID 6757 Rev 21
9/42
Signal description
M24256-BF, M24256-BR, M24256-BW, M24256-DR
I2C Fast mode (fC = 400 kHz): maximum Rbus value versus
bus parasitic capacitance (Cbus)
Figure 5.
Bus line pull-up resistor
(k )
100
10
4 kΩ
When tLOW = 1.3 µs (min value for
fC = 400 kHz), the Rbus × Cbus
time constant must be below the
400 ns time constant line
represented on the left.
R
bu
s ×
C
bu
s =
Here Rbus × Cbus = 120 ns
40
VCC
Rbus
0n
s
I²C bus
master
SCL
M24xxx
SDA
1
30 pF
10
100
Bus line capacitor (pF)
Cbus
1000
ai14796b
Bus line pull-up resistor (k )
Figure 6.
I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus
bus parasitic capacitance (Cbus)
100
VCC
When tLOW = 700 ns
(max possible value for
fC = 1 MHz), the Rbus × Cbus
time constant must be below
the 270 ns time constant line
represented on the left.
R
bus ×
C
bus =
270
10
5
ns
R
bus ×
C
bus =
10
0 ns
Here,
Rbus × Cbus = 150 ns
When tLOW = 400 ns
(min value for fC = 1 MHz),
the Rbus × Cbus time constant
must be below the 100 ns
time constant line represented
on the left.
Rbus
I²C bus
master
SCL
M24xxx
SDA
Cbus
1
10
100
30
Bus line capacitor (pF)
ai14795d
10/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure 7.
Signal description
I2C bus protocol
SCL
SDA
SDA
Input
Start
condition
SCL
1
2
SDA
MSB
SDA
Change
Stop
condition
3
7
8
9
ACK
Start
condition
SCL
1
SDA
MSB
2
3
7
8
9
ACK
Stop
condition
AI00792c
Table 2.
Device select code (for memory array)
Device type identifier(1)
Device select code
Chip Enable address(2)
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 3.
Device select code to access the Identification page (M24256-DR only)
Device type identifier(1)
Device select code
Chip Enable address(2)
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
1
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Doc ID 6757 Rev 21
11/42
Signal description
Table 4.
b15
Table 5.
b7
12/42
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Most significant address byte
b14
b13
b12
b11
b10
b9
b8
b3
b2
b1
b0
Least significant address byte
b6
b5
b4
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
3
Device operation
Device operation
The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always slave in all
communications.
3.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
3.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode. A Stop condition at the end of a Write
instruction triggers the internal Write cycle.
3.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.
3.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.
Doc ID 6757 Rev 21
13/42
Device operation
3.5
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Addressing the memory array
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 6.
Operating modes
RW bit
WC(1)
Bytes
1
X
1
Random Address
Read
0
X
1
X
Sequential Read
1
X
1
Byte Write
0
VIL
1
Start, device select, RW = 0
Page Write
0
VIL
 64
Start, device select, RW = 0
Mode
Current Address
Read
Start, device select, RW = 1
Start, device select, RW = 0, Address
1
re-Start, device select, RW = 1
1. X = VIH or VIL.
14/42
Initial sequence
Doc ID 6757 Rev 21
Similar to Current or Random Address
Read
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure 8.
Device operation
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
Byte addr
ACK
Byte addr
NO ACK
Data in
Stop
Dev sel
Start
Byte Write
ACK
R/W
WC
ACK
Dev sel
Start
Page Write
ACK
Byte addr
ACK
Byte addr
NO ACK
Data in 1
Data in 2
R/W
WC (cont'd)
NO ACK
Data in N
Stop
Page Write
(cont'd)
NO ACK
AI01120d
Doc ID 6757 Rev 21
15/42
Device operation
3.6
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data byte.
Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write
instruction with Write Control (WC) driven High (during a period of time from the Start
condition until the end of the two address bytes) will not modify the memory contents, and
the accompanying data bytes are not acknowledged, as shown in Figure 8.
Each data byte in the memory has a 16-bit (two byte wide) address. The most significant
byte (Table 4) is sent first, followed by the least significant byte (Table 5). Bits b15 to b0 form
the address of the byte in memory.
When the bus master generates a Stop condition immediately after the Ack bit (in the “10th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.
After the Stop condition, the delay tW, and the successful completion of a Write operation,
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
3.7
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven High, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 9.
3.8
Page Write (memory array)
The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided
that they are all located in the same ‘row’ in the memory: that is, the most significant
memory address bits (b15-b6) are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 64 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (the 7 least significant
address bits only) is incremented. The transfer is terminated by the bus master generating a
Stop condition.
16/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
3.9
Device operation
Identification Page Write (M24256-DR only)
The Identification page is written by issuing an ID Write instruction. This instruction uses the
same protocol and format as the Page Write in memory array, except for the following
differences:
●
Device Type Identifier = 1011b
●
MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A5/A0 define the byte address inside the identification page.
If the Identification page is locked, the data bytes transferred during the Identification Page
Write instruction are not acknowledged (NoAck).
3.10
Lock Identification Page (M24256-DR only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
●
Device Type Identifier = 1011b
●
Address bit A10 must be ‘1’; all other address bits are don't care
●
The data byte must be equal to the binary value xxxx xx1x, where x is don't care.
If the Identification Page is locked, the data bytes transferred during the ID Write instruction
are not acknowledged (NoAck).
3.11
ECC (error correction code) and write cycling
The M24256-Bx and M24256-DRdevices offer an ECC (error correction code) logic which
compares each 4-byte word with its six associated ECC EEPROM bits. As a result, if a
single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC
detects it and replaces it by the correct value. The read reliability is therefore much improved
by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes
making up the word. It is therefore recommended to write by word (4 bytes) in order to
benefit from the larger amount of Write cycles.
The M24256-Bx and M24256-DR devices are qualified at 1 million (1 000 000) Write cycles,
using a cycling routine that writes to the device by multiples of 4-bytes.
Doc ID 6757 Rev 21
17/42
Device operation
Figure 9.
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Write mode sequences with WC = 0 (data write enabled)
WC
ACK
ACK
Byte addr
Byte addr
ACK
Data in
Stop
Dev sel
Start
Byte Write
ACK
R/W
WC
ACK
Dev sel
Start
Page Write
ACK
Byte addr
ACK
Byte addr
ACK
Data in 1
Data in 2
R/W
WC (cont'd)
ACK
Data in N
Stop
Page Write
(cont'd)
ACK
AI01106d
18/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Device operation
Figure 10. Write cycle polling flowchart using ACK
Write cycle
in progress
Start condition
Device select
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
Returned
YES
NO
Next
operation is
addressing the
memory
YES
Send Address
and Receive ACK
ReStart
NO
Stop
Start
condition
YES
Data for the
Write operation
Device select
with RW = 1
Continue the
Write operation
Continue the
Random Read operation
AI01847d
3.12
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 16, but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in Figure 10, is:
●
Initial condition: a Write cycle is in progress.
●
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
●
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Doc ID 6757 Rev 21
19/42
Device operation
3.13
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
Figure 11. Read mode sequences
ACK
Data out
Stop
Start
Dev sel
R/W
ACK
Random
Address
Read
Byte addr
Dev sel *
ACK
NO ACK
Data out N
R/W
ACK
ACK
Byte addr
ACK
Byte addr
ACK
Dev sel *
Start
Start
Dev sel *
R/W
ACK
Data out
R/W
ACK
Data out 1
NO ACK
Stop
Start
Dev sel
Sequential
Random
Read
ACK
Byte addr
R/W
ACK
Sequential
Current
Read
ACK
Start
Start
Dev sel *
ACK
Stop
Current
Address
Read
NO ACK
ACK
Data out 1
R/W
NO ACK
Stop
Data out N
AI01105d
3.14
Random Address Read (in memory array)
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 11) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
20/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
3.15
Device operation
Current Address Read (in memory array)
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 11, without acknowledging the byte.
3.16
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 11.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
3.17
Read Identification Page
This instruction uses the same protocol and format as the Random Address Read (in
memory array) instruction. The only differences between the two instructions are that, in the
Read Identification Page instruction:
●
the device type identifier = 1011b
●
MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A5/A0 define the byte address inside the identification page. During a
Read Identification Page instruction, the (A5/A0) address should not exceed 3Fh.
Doc ID 6757 Rev 21
21/42
Device operation
3.18
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Read Identification Page status (locked/unlocked)
The locked/unlocked status of the Identification page can be checked by issuing a specific
truncated instruction consisting of the Identification Page Write instruction followed by one
data byte. The data byte will be acknowledged if the Identification page is unlocked, while it
will not be acknowledged if the Identification page is locked.
Once the acknowledge bit of this data byte is read, it is recommended to generate a Start
condition followed by a Stop condition, so that:
3.19
●
The instruction is truncated and not executed as the Start condition resets the device
internal logic.
●
The device is set to Standby mode by the Stop condition.
Acknowledge in Read mode
For all Read instructions, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this
time, the device terminates the data transfer and switches to its Standby mode.
22/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
4
Initial delivery state
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
5
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Absolute maximum ratings
Symbol
TA
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
Lead temperature during soldering
See
note (1)
°C
VIO
Input or output range
–0.50
6.5
V
VCC
Supply voltage
–0.50
6.5
V
IOL
DC output current (SDA = 0)
5
mA
3000
V
VESD
Electrostatic discharge voltage (human body model)
(2)
–3000
ECOPACK®
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST
7191395 specification, and the European directive on the restriction of the use of certain hazardous
substances in electrical and electronic equipment (RoHS) 2002/95/EC.
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 pF, R1 = 1500 , R2 = 500 )
Doc ID 6757 Rev 21
23/42
DC and AC parameters
6
M24256-BF, M24256-BR, M24256-BW, M24256-DR
DC and AC parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8.
Operating conditions (voltage range W)
Symbol
VCC
TA
Table 9.
Parameter
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 3)
–40
125
°C
Operating conditions (voltage range R)
Symbol
VCC
TA
Table 10.
Parameter
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Min.
Max.
Unit
Supply voltage
1.7
5.5
V
Ambient operating temperature
–40
85
°C
Operating conditions (voltage range F)
Symbol
VCC
TA
Table 11.
Parameter
AC test measurement conditions
Symbol
CL
Parameter
Min.
Load capacitance
Max.
100
Input rise and fall times
pF
50
ns
Input levels
0.2VCC to 0.8VCC
V
Input and output timing reference levels
0.3VCC to 0.7VCC
V
Figure 12. AC test measurement I/O waveform
Input Levels
0.8VCC
Input and Output
Timing Reference Levels
0.7VCC
0.3VCC
0.2VCC
AI00825B
24/42
Unit
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 12.
Input parameters
Parameter(1)
Symbol
DC and AC parameters
Test condition
Min.
Max.
Unit
CIN
Input capacitance (SDA)
8
pF
CIN
Input capacitance (other pins)
6
pF
ZL(2)
Input impedance
(E2, E1, E0, WC)
VIN < 0.3VCC
30
k
ZH(2)
Input impedance
(E2, E1, E0, WC)
VIN > 0.7VCC
500
k
1. Sampled only, not 100% tested.
2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition).
Table 13.
DC characteristics (voltage range W)
Symbol
Parameter
ILI
Input leakage current
(SCL, SDA, E0, E1,
E2)
ILO
Output leakage
current
ICC
ICC0
Test conditions (see Table 8 and
Table 11)
Min.
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
±2
µA
VCC = 2.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
1
mA
VCC = 5.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
2
mA
5(1)
mA
Supply current (Read)
Supply current (Write) During tW, 2.5 V < VCC < 5.5 V
(2),
ICC1
VIL
VIH
VOL
Standby supply
current
Device grade 3
Device not selected
VIN = VSS or VCC, VCC
Device grade 6
= 2.5 V
5
VIN = VSS or VCC, VCC = 5.5 V
5
µA
V
µA
2
Input low voltage
(SCL, SDA, WC)
–0.45
0.3VCC
Input high voltage
(SCL, SDA)
0.7VCC
6.5
Input high voltage
(WC, E0, E1, E2)
0.7VCC VCC+0.6
V
Output low voltage
IOL = 2.1 mA, VCC = 2.5 V
0.4
V
1. Characterized value, not tested in production.
2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Doc ID 6757 Rev 21
25/42
DC and AC parameters
Table 14.
Symbol
M24256-BF, M24256-BR, M24256-BW, M24256-DR
DC characteristics (voltage range R)
Test conditions (in addition to
those in Table 9)
Parameter
ILI
Input leakage current
(E1, E2, SCL, SDA)
ILO
Output leakage current
ICC
ICC0
Min.
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
±2
µA
VCC = 1.8 V, fc= 400 kHz
(rise/fall time < 50 ns)
0.8
mA
VCC = 2.5 V, fc= 400 kHz
(rise/fall time < 50 ns)
1
mA
VCC = 5.0 V, fc= 400 kHz
(rise/fall time < 50 ns)
2
mA
1.8 V < VCC < 5.5 V, fc= 1 MHz(1)
(rise/fall time < 50 ns)
2.5
mA
During tW, 1.8 V < VCC < 5.5 V
5(2)
mA
Device not
VIN = VSS or VCC, VCC = 1.8 V
1
µA
Device not selected(3),
VIN = VSS or VCC, VCC = 2.5 V
2
µA
Device not selected(3),
VIN = VSS or VCC, VCC = 5.5 V
3
µA
V
Supply current (Read)
Supply current (Write)
selected(3),
ICC1
VIL
Standby supply current
Input low voltage
(SCL, SDA, WC)
Input high voltage
(SCL, SDA)
VIH
Input high voltage
(WC, E0, E1, E2)
VOL
Output low voltage
1.8 V  VCC < 2.5 V
–0.45
0.25 VCC
2.5 V  VCC  5.5 V
–0.45
0.3 VCC
1.8 V  VCC < 2.5 V
0.75VCC
6.5
2.5 V  VCC < 5.5 V
0.7VCC
6.5
1.8 V  VCC < 2.5 V
0.75VCC
VCC+0.6
2.5 V  VCC  5.5 V
0.7VCC
VCC+0.6
V
IOL = 1 mA, VCC = 1.8 V
0.2
V
IOL = 2.1 mA, VCC = 2.5 V
0.4
V
IOL = 3.0 mA, VCC = 5.5 V
0.4
V
1. Only for devices operating at fC max = 1 MHz (see Table 17).
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
26/42
V
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 15.
DC characteristics (voltage range F)(1)
Symbol
Test condition (in addition to
those in Table 9)
Parameter
ILI
Input leakage current
(E1, E2, SCL, SDA)
ILO
Output leakage current
ICC
ICC0
DC and AC parameters
Supply current (Read)
Supply current (Write)
Min.
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
±2
µA
VCC = 1.7 V, fc= 400 kHz
(rise/fall time < 50 ns)
0.8
mA
VCC = 2.5 V, fc= 400 kHz
(rise/fall time < 50 ns)
1
mA
VCC = 5.0 V, fc= 400 kHz
(rise/fall time < 50 ns)
2
mA
During tW, 1.7 V < VCC < 5.5 V
5(2)
mA
Device not
VIN = VSS or VCC, VCC = 1.7 V
1
µA
Device not selected(3),
VIN = VSS or VCC, VCC = 2.5 V
2
µA
Device not selected(3),
VIN = VSS or VCC, VCC = 5.5 V
3
µA
selected(3),
ICC1
VIL
Standby supply current
Input low voltage
(SCL, SDA, WC)
Input high voltage
(SCL, SDA)
VIH
Input high voltage
(WC, E0, E1, E2)
VOL
Output low voltage
1.7 V  VCC < 2.5 V
–0.45
0.25 VCC
2.5 V  VCC  5.5 V
–0.45
0.3 VCC
1.7 V  VCC < 2.5 V
0.75VCC
6.5
2.5 V  VCC  5.5 V
0.7VCC
6.5
1.7 V  VCC < 2.5 V
0.75VCC
VCC+0.6
2.5 V  VCC  5.5 V
0.7VCC
VCC+0.6
V
V
V
IOL = 1 mA, VCC = 1.7 V
0.2
V
IOL = 2.1 mA, VCC = 2.5 V
0.4
V
IOL = 3.0 mA, VCC = 5.5 V
0.4
V
1. Preliminary data.
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Doc ID 6757 Rev 21
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DC and AC parameters
Table 16.
M24256-BF, M24256-BR, M24256-BW, M24256-DR
400 kHz AC characteristics
Test conditions specified in Table 8, Table 9, Table 10 and Table 11
Max.(1)
Unit
400
kHz
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
Clock pulse width high
600
ns
tCLCH
tLOW
Clock pulse width low
1300
ns
tQL1QL2
(2)
tXH1XH2
tF
tR
Parameter
Min.(1)
Symbol
SDA (out) fall time
20
(3)
120
ns
Input signal rise time
(4)
(4)
ns
(4)
ns
tXL1XL2
tF
Input signal fall time
(4)
tDXCX
tSU:DAT
Data in set up time
100
ns
tCLDX
tHD:DAT
Data in hold time
0
ns
Data out hold time
100(5)
ns
Clock low to next data valid (access time)
100(5)
tCLQX
tDH
tCLQV(6)(7)
tAA
tCHDL
tSU:STA
Start condition setup time
600
ns
tDLCL
tHD:STA
Start condition hold time
600
ns
tCHDH
tSU:STO
Stop condition set up time
600
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
ns
tW
tWR
Write time
tNS
Pulse width ignored (input filter on SCL and
SDA) - single glitch
900
ns
5
ms
80(8)
ns
1. All values are referred to VIL(max) and VIH(min).
2. Characterized only, not tested in production.
3. With CL = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
5. The new M24xxx-W, M24xxx-R, and M24xxx-BF devices (identified by the process letter K) offer
tCLQX = 100 ns (min) and tCLQV = 100 ns (min), while the current devices (process letter A) offer
tCLQX = 200 ns (min) and tCLQV = 200 ns (min). Both series offer a safe margin compared to the I2C
specification which recommends tCLQV = 0 ns (min).
6. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
7. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 6.
8. The current M24xxx devices (identified by the Process letter A) offer tNS=100 ns (min), the new M24256BR and M24256-DR device (identified by the process letter K) offer tNS=80 ns (min). Both products offer a
safe margin compared to the 50 ns minimum value recommended by the I2C specification.
28/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 17.
DC and AC parameters
1 MHz AC characteristics(1)
Test conditions specified in Table 9 and Table 11
Symbol
Alt.
Min.(2)
Parameter
Max.(2)
Unit
fC
fSCL
Clock frequency
0
1
MHz
tCHCL
tHIGH
Clock pulse width high
300
-
ns
tCLCH
tLOW
Clock pulse width low
400
-
ns
Input signal rise time
(3)
(3)
ns
Input signal fall time
(3)
(3)
ns
120
ns
tXH1XH2
tR
tF
tXL1XL2
(4)
(5)
tF
SDA (out) fall time
20
tDXCX
tSU:DAT
Data in setup time
80
-
ns
tCLDX
tHD:DAT Data in hold time
0
-
ns
Data out hold time
50(6)
-
ns
Clock low to next data valid (access time)
50(6)
500
ns
tQL1QL2
tCLQX
tCLQV(7)(8)
tDH
tAA
tCHDL
tSU:STA
Start condition setup time
250
-
ns
tDLCL
tHD:STA
Start condition hold time
250
-
ns
tCHDH
tSU:STO
Stop condition setup time
250
-
ns
tDHDL
tBUF
Time between Stop condition and next
Start condition
500
-
ns
tW
tWR
Write time
-
5
ms
50(9)
ns
tNS(4)
Pulse width ignored (input filter on SCL and
SDA)
1. Only new M24256-BR and M24256-DR devices identified by the process letter K are qualified at 1 MHz.
2. All values are referred to VIL(max) and VIH(min).
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz, or less than 120 ns when fC < 1 MHz.
4. Characterized only, not tested in production.
5. With CL = 10 pF.
6. The new M24xxx devices (identified by the process letter K) offer tCLQX=100 ns (min) and tCLQV=100 ns
(min) which is an improved value compared to the tCLQX=50 ns (min) and tCLQV=50 ns (min) offered by the
current M24xxx devices (identified with the Process letter A)
7. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
8. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 6.
9. The new M24xxx devices (identified with the process letter K) offer tNS = 80 ns (min) which is an improved
value compared to the current M24xxx devices (identified by the process letter A).
Doc ID 6757 Rev 21
29/42
DC and AC parameters
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure 13. AC waveforms
tXL1XL2
tCHCL
tXH1XH2
tCLCH
SCL
tDLCL
tXL1XL2
SDA In
tCHDL
tCLDX
tXH1XH2
Start
condition
SDA
Input
SDA tDXCH
Change
tCHDH tDHDL
Start
Stop
condition condition
SCL
SDA In
tW
tCHDH
tCHDL
Stop
condition
Write cycle
Start
condition
tCHCL
SCL
tCLQV
SDA Out
tCLQX
Data valid
tQL1QL2
Data valid
AI00795e
30/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
7
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 14. SO8W – 8-lead plastic small outline, 208 mils body width, package outline
A2
A
c
b
CP
e
D
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 18.
SO8W – 8-lead plastic small outline, 208 mils body width, package data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
Min
2.5
Max
0.0984
A1
0
0.25
0
0.0098
A2
1.51
2
0.0594
0.0787
b
0.4
0.35
0.51
0.0157
0.0138
0.0201
c
0.2
0.1
0.35
0.0079
0.0039
0.0138
CP
0.1
0.0039
D
6.05
0.2382
E
5.02
6.22
0.1976
0.2449
E1
7.62
8.89
0.3
0.35
-
-
-
-
k
0°
10°
0°
10°
L
0.5
0.8
0.0197
0.0315
N (number of pins)
8
e
1.27
0.05
8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 6757 Rev 21
31/42
Package mechanical data
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 19.
SO8N – 8-lead plastic small outline, 150 mils body width, package
mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
1.75
Max
0.0689
A1
0.1
A2
1.25
b
0.28
0.48
0.011
0.0189
c
0.17
0.23
0.0067
0.0091
ccc
0.25
0.0039
0.0098
0.0492
0.1
0.0039
D
4.9
4.8
5
0.1929
0.189
0.1969
E
6
5.8
6.2
0.2362
0.2283
0.2441
E1
3.9
3.8
4
0.1535
0.1496
0.1575
e
1.27
-
-
0.05
-
-
h
0.25
0.5
0.0098
0.0197
k
0°
8°
0°
8°
L
0.4
1.27
0.0157
0.05
L1
1.04
0.0409
1. Values in inches are converted from mm and rounded to 4 decimal digits.
32/42
Min
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Package mechanical data
Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 20.
TSSOP8 – 8-lead thin shrink small outline, package mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Min
1.200
A1
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ
1.000
CP
Max
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
0.0394

0°
N
8
8°
8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 6757 Rev 21
33/42
Package mechanical data
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure 17. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, outline
e
D
b
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be
allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering
process.
3. The circle in the top view of the package indicates the position of pin 1.
Table 21.
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.55
0.45
0.6
0.0217
0.0177
0.0236
A1
0.02
0
0.05
0.0008
0
0.002
b
0.25
0.2
0.3
0.0098
0.0079
0.0118
D
2
1.9
2.1
0.0787
0.0748
0.0827
D2
1.6
1.5
1.7
0.063
0.0591
0.0669
E
3
2.9
3.1
0.1181
0.1142
0.122
E2
0.2
0.1
0.3
0.0079
0.0039
0.0118
e
0.5
-
-
0.0197
-
-
L
0.45
0.4
0.5
0.0177
0.0157
0.0197
L1
L3
ddd
(2)
0.15
0.0059
0.3
0.0118
0.08
0.08
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
34/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Package mechanical data
Figure 18. WLCSP, 0.5 mm pitch, package outline
Orientation reference
D
2
3
1
A
e2
e
B
C
E
D
B
G
E
e3
F
e1
A2
A1
A
1. Drawing is not to scale.
Table 22.
WLCSP 0.5 mm pitch, package mechanical data(1)
Inches(2)
Millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.60
0.55
0.65
0.0236
0.0217
0.0256
A1
0.245
0.22
0.27
0.0096
0.0087
0.0106
A2
0.355
0.330
0.380
0.0140
0.0130
0.0150
B
Ø 0.311
Ø 0.0122
D
1.97
1.95
1.99
0.0776
0.0768
0.0783
E
1.785
1.765
1.805
0.0703
0.0695
0.0711
e
0.5
0.0197
e1
0.866
0.0341
e2
0.25
0.0098
e3
0.433
0.0170
F
0.552
0.502
0.602
0.0217
0.0198
0.0237
0.392
0.342
0.442
0.0154
0.0135
0.0174
G
N
(3)
8
8
1. Preliminary data.
2. Values in inches are converted from mm and rounded to 4 decimal digits.
3. N is the total number of terminals.
Doc ID 6757 Rev 21
35/42
Part numbering
M24256-BF, M24256-BR, M24256-BW, M24256-DR
8
Part numbering
Table 23.
Ordering information scheme
Example:
M24256–B
W
MW
6
T
P
/AB
Device type
M24 = I2C serial access EEPROM
Device function
256– = 256 Kbit (32 Kb × 8)
Device family
B: Without Identification page
D: With additional Identification page
Operating voltage
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
F = VCC = 1.7 to 5.5 V
Package
MW = SO8 (208 mils width)
MN = SO8 (150 mils body width)
DW = TSSOP8
MB = UFDFPN8 (MLP8)
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C. Device tested with standard test flow
3 = Automotive: device tested with high reliability certified flow(1)
over –40 to 125 °C
Option
blank = standard packing
T = tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process
/A = F8L process
/AB = F8L process (for device grade 3)
/K = F8H process
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High
Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a
copy.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
36/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 24.
Part numbering
Available M24256-BR, M24256-BW, M24256-BF products (package,
voltage range, temperature grade)
M24256-BW
2.5 V to 5.5 V
M24256-BR
1.8 V to 5.5 V
M24256-BF
1.7 V to 5.5 V
SO8N (MN)
Range 6, Range 3
Range 6
-
SO8W (MW)
Range 6
-
-
TSSOP (DW)
Range 6
Range 6
Range 6
WLCSP (CS)
-
Range 6
-
UFDFPN8 (MB)
-
-
Range 6
Package
Table 25.
Available M24256-DR products (package, voltage range, temperature
grade)
M24256-DR
1.8 V to 5.5 V
Package
SO8N (MN)
Range 6
TSSOP (DW)
Range 6
Doc ID 6757 Rev 21
37/42
Revision history
9
Revision history
Table 26.
Date
Document revision history
Revision
Changes
29-Jan-2001
1.1
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
Write Cycle Polling Flow Chart using ACK illustration updated
LGA8 and SO8(wide) packages added
References to PSDIP8 changed to PDIP8, and Package Mechanical data
updated
10-Apr-2001
1.2
LGA8 Package Mechanical data and illustration updated
SO16 package removed
16-Jul-2001
1.3
LGA8 Package given the designator “LA”
02-Oct-2001
1.4
LGA8 Package mechanical data updated
13-Dec-2001
1.5
Document becomes Preliminary Data
Test conditions for ILI, ILO, ZL and ZH made more precise
VIL and VIH values unified. tNS value changed
12-Jun-2001
1.6
Document promoted to Full Datasheet
22-Oct-2003
2.0
Table of contents, and Pb-free options added. Minor wording changes in
Summary Description, Power-On Reset, Memory Addressing, Write
Operations, Read Operations. VIL(min) improved to –0.45V.
3.0
LGA8 package is Not for New Design. 5V and -S supply ranges, and
Device Grade 5 removed. Absolute Maximum Ratings for VIO(min) and
VCC(min) changed. Soldering temperature information clarified for RoHS
compliant devices. Device grade information clarified. AEC-Q100-002
compliance. VIL specification unified for SDA, SCL and WC
4.0
Initial delivery state is FFh (not necessarily the same as Erased).
LGA package removed, TSSOP8 and SO8N packages added (see
Package mechanical data section and Table 23: Ordering information
scheme).
Voltage range R (1.8V to 5.5V) also offered. Minor wording changes.
ZL Test Conditions modified in Table 12: Input parameters and Note 2
added.
ICC and ICC1 values for VCC = 5.5V added to Table 13: DC characteristics
(voltage range W).
Note added to Table 13: DC characteristics (voltage range W).
Power On Reset paragraph specified.
tW max value modified in Table 16: 400 kHz AC characteristics and note 4
added. Plating technology changed in Table 23: Ordering information
scheme.
Resistance and capacitance renamed in Figure 6.
02-Sep-2004
22-Feb-2005
38/42
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 26.
Date
05-May-2006
16-Oct-2006
02-Jul-2007
16-Oct-2007
Revision history
Document revision history (continued)
Revision
Changes
5
Power On Reset paragraph replaced by Section 2.6: Supply voltage
(VCC). Figure 4: Device select code added.
ECC (error correction code) and write cycling added and specified at 1
Million cycles.
ICC0 added and ICC1 specified over the whole voltage range in Table 13
and Table 14.
PDIP8 package removed. Packages are ECOPACK® compliant. Small
text changes.
6
M24256-BW and M24256-BR part numbers added.
Section 3.11: ECC (error correction code) and write cycling updated.
ICC and ICC1 modified in Table 14: DC characteristics (voltage range R).
tW modified in Table 16: 400 kHz AC characteristics.
SO8Narrow package specifications updated (see Table 19 and
Figure 15). Blank option removed from below Plating technology in
Table 23: Ordering information scheme.
7
Section 2.6: Supply voltage (VCC) modified.
Section 3.11: ECC (error correction code) and write cycling modified.
JEDEC standard and European directive references corrected below
Table 7: Absolute maximum ratings.
Rise/fall time conditions modified for ICC and VIH max modified in
Table 13: DC characteristics (voltage range W) and Table 14: DC
characteristics (voltage range R)
Note 1 removed from Table 13: DC characteristics (voltage range W).
SO8W package specifications modified in Section 7: Package mechanical
data.
Table 24: Available M24256-BR, M24256-BW, M24256-BF products
(package, voltage range, temperature grade) and Table 26: Available
M24512-x products (package, voltage range, temperature grade) added.
8
Section 2.5: VSS ground added. Small text changes.
VIO max changed and Note 1 updated to latest standard revision in
Table 7: Absolute maximum ratings.
Note removed from Table 12: Input parameters.
VIH min and VIL max modified in Table 14: DC characteristics (voltage
range R).
Removed tCH1CH2, tCL1CL2 and tDH1DH2, and added tXL1XL2, tDL1DL2 and
Note 3 in Table 16: 400 kHz AC characteristics.
tXH1XH2, tXL1XL2 and Note 2 added to Table 17: 1 MHz AC characteristics.
Figure 13: AC waveforms modified.
Package mechanical data inch values calculated from mm and rounded to
4 decimal digits (see Section 7: Package mechanical data).
Doc ID 6757 Rev 21
39/42
Revision history
Table 26.
Date
Document revision history (continued)
Revision
Changes
9
1 MHz frequency introduced (M24512-HR root part number).
Section 2.6.3: Device reset modified.
Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus
parasitic capacitance (Cbus) modified, Figure 6: I2C Fast mode Plus (fC =
1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus)
added.
tNS moved from Table 12 to Table 16. ILO test conditions modified in
Table 13.
Table 14: DC characteristics (voltage range R) and Table 17: 1 MHz AC
characteristics modified. Small text changes.
10
Small text changes. M24256-BHR root part number added.
Section 2.6.3: Device reset on page 9 updated.
Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus
bus parasitic capacitance (Cbus) on page 10 updated.
Caution removed in Section 3.11: ECC (error correction code) and write
cycling.
22-Apr-2008
11
M24512-W and M24256-BW offered in the device grade 3 option
(automotive temperature range):
– Table 8: Operating conditions (voltage range W),
– Table 13: DC characteristics (voltage range W),
– /AB Process letters added to Table 23: Ordering information scheme,
– Table 24: Available M24256-BR, M24256-BW, M24256-BF products
(package, voltage range, temperature grade) and
– Table 26: Available M24512-x products (package, voltage range,
temperature grade) updated accordingly).
Small text changes.
22-Dec-2008
12
WLCSP package added (see Figure 3: WLCSP connections (top view,
marking side, with balls on the underside) and Section 7: Package
mechanical data).
13
M24256-BF part number added (VCC = 1.7 V to 5.5 V voltage range
added, see Table 10, Table 15, Table 16 and Table 24).
ICC1 test conditions modified in Table 13: DC characteristics (voltage
range W), Table 14: DC characteristics (voltage range R) and Table 15:
DC characteristics (voltage range F).
14
M24512-DR part number and Identification page feature added.
Command replaced by instruction in the whole document.
UFDFPN8 added.
Figure 6 updated.
Section 2.6.2: Power-up conditions and Section 2.6.3: Device reset
updated.
tCLQX and tCLQV updated in Table 16, Note 5 and Note 8 added.
tCLQX and tCLQV updated in Table 17, Note 6 and Note 9 added.
Section 8: Part numbering updated.
Reference to the SURE program removed in Section 5: Maximum rating.
Previous 1 MHz M24512-HR and M24512-BHR devices replaced by new
M24512-R and M24256-BR (process letter K).
14-Dec-2007
27-Mar-2008
21-Jan-2009
05-Jun-2009
40/42
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 26.
Revision history
Document revision history (continued)
Date
Revision
Changes
16-Jun-2009
15
Part numbers updated in cover page header.
20-Aug-2009
16
IOL added to Table 8: Operating conditions (voltage range W).
Note 1and ICC modified in Table 13: DC characteristics (voltage range W);
Note and ICC modified in Table 14: DC characteristics (voltage range R);
13-Oct-2009
17
Datasheet split to leave only devices with 256 Kbit capacity.
M24256-DR part number added (see Table 25: Available M24256-DR
products (package, voltage range, temperature grade).
Figure 4: Device select code and Figure 5: I2C Fast mode (fC = 400 kHz):
maximum Rbus value versus bus parasitic capacitance (Cbus) updated.
VIO max modified in Table 7: Absolute maximum ratings.
VIH modified in Table 13: DC characteristics (voltage range W), Table 14:
DC characteristics (voltage range R) and Table 15: DC characteristics
(voltage range F).
In Table 16: 400 kHz AC characteristics and Table 17: 1 MHz AC
characteristics:
– tDL1DL2 changed to tQL1QL2
– tCHDX changed to tCHDL
– tXH1XH2 and tXL1XL2 values removed
– Notes modified
Figure 13: AC waveforms modified.
05-Nov-2009
18
Section 3.9: Identification Page Write (M24256-DR only)
corrected.Section 3.17: Read Identification Page clarified.
10-Dec-2009
19
UFDFPN8 package is now offered (see Section 7: Package mechanical
data, Table 23: Ordering information scheme and Table 24: Available
M24256-BR, M24256-BW, M24256-BF products (package, voltage
range, temperature grade).
19-Jan-2010
20
Revision number corrected at bottom of pages.
04-Mar-2010
21
Process description corrected in Table 23: Ordering information scheme.
Doc ID 6757 Rev 21
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M24256-BF, M24256-BR, M24256-BW, M24256-DR
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