STMICROELECTRONICS M41T256YMT7F

M41T256Y
256 Kbit (32K x8) Serial RTC
FEATURES SUMMARY
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5V OPERATING VOLTAGE
SERIAL INTERFACE SUPPORTS
EXTENDED I2C BUS ADDRESSING
(400kHz)
AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY
POWER-FAIL DESELECT VOLTAGES:
– M41T256Y: VCC = 4.5 to 5.5V;
VPFD = 4.2 < VPFD < 4.5V
COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, and YEAR
PROGRAMMABLE SOFTWARE CLOCK
CALIBRATION
32,752 BYTES OF GENERAL PURPOSE
RAM
MICROPROCESSOR POWER-ON RESET
HOLDS MICROPROCESSOR IN RESET
UNTIL SUPPLY VOLTAGE REACHES
STABLE OPERATING LEVEL
AUTOMATIC ADDRESS-INCREMENTING
TAMPER INDICATION CIRCUIT WITH TIMESTAMP
SLEEP MODE FUNCTION
PACKAGING INCLUDES A 44-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT® TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL
June 2004
Figure 1. 44-pin, Hatless SOIC Package
44
1
SO44 (MT)
Figure 2. 44-pin SOIC Package
SNAPHAT (SH)
Crystal/Battery
44
1
SOH44 (MH)
1/27
M41T256Y
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 44-pin, Hatless SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. 44-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3.
Table 1.
Figure 4.
Figure 5.
Figure 6.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
44-pin SOIC Connections (MT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
44-pin SOIC (MH - SNAPHAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Stop data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Tamper Indication Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Tamper Event Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/27
M41T256Y
Preferred Power-on/Battery Attach Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Preferred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Crystal Electrical Characteristics (Externally Supplied) . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18.SOH44 – 44-lead Plastic, Hatless, Small Package Outline. . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. SOH44 – 44-lead Plastic, Hatless, Small Package Mechanical Data . . . . . . . . . . . . . . . 22
Figure 19.SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline . . . . . . . . . . . . . . 23
Table 12. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data . . . . . . 23
Figure 20.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal Outline . . . . . . . . . . . . . . 24
Table 13. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Mechanical Data . . . . . . 24
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. SNAPHAT® Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/27
M41T256Y
SUMMARY DESCRIPTION
The M41T256Y Serial TIMEKEEPER® SRAM is a
low power 256 Kbit static CMOS SRAM organized
as 32K words by 8 bits. A built-in 32.768kHz oscillator (external crystal controlled) and 8 bytes of the
SRAM (see Table 3., page 14) are used for the
clock/calendar function and are configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a
two line, bi-directional I2C interface. The built-in
address register is incremented automatically after each WRITE or READ data byte.
The M41T256Y has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power failure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
lithium button-cell supply when a power failure occurs. Functions available to the user include a
non-volatile, time-of-day clock/calendar, and Power-on Reset. The eight clock address locations
contain the year, month, date, day, hour, minute,
second, and tenths/hundredths of seconds in 24hour BCD format. Corrections for 28, 29 (leap year
- valid until year 2100), 30 and 31 day months are
made automatically. The first clock address loca-
tion (7FF8h) stores the clock software calibration
settings as well as the Write Clock Bit.
The M41T256Y is supplied in a 44-lead SOIC
SNAPHAT® package (MH - which integrates both
crystal and battery in a single SNAPHAT top) or a
44-pin “hatless” SOIC (MT). The 44-pin, 330mil
SOIC provides sockets with gold-plated contacts
at both ends for direct connection to a separate
SNAPHAT housing containing the battery and
crystal. The unique design allows the SNAPHAT
battery/crystal package to be mounted on top of
the SOIC package after the completion of the surface-mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device surface-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion. The 44-pin
SOIC and crystal/battery packages are shipped
separately in plastic, anti-static tubes or in Tape &
Reel form. For the 44-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is
“M4Txx-BR12SH” (see Table 15., page 25).
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium, button-cell battery.
Figure 3. Logic Diagram
Table 1. Signal Names
XI(1)
Oscillator Input
XO(1)
Oscillator Output
FT
Frequency Test (Open drain)
RST
Reset Output (Open drain)
RST
SCL
Serial Clock Input
FT
SDA
Serial Data Input/Output
VCC
Supply Voltage
VBAT(1)
Battery Supply Voltage
VSS
Ground
TP
Tamper Input
VCC VBAT(1)
XI(1)
XO(1)
SCL
M41T256Y
SDA
TP
VSS
AI04754b
Note: 1. For 44-pin SNAPHAT (MT) package only.
4/27
Note: 1. For 44-pin SNAPHAT (MT) package only.
M41T256Y
Figure 4. 44-pin SOIC Connections (MT)
XO
XI
NF
RST
NF
NF
NF
NF
NF
NF
NF
TP
NC
NF
NF
NF
NF
SDA
VSS
VSS
NC
VSS
Figure 5. 44-pin SOIC (MH - SNAPHAT)
VCC
NC
NC
NC
FT
NF
NF
NF
NF
NF
NF
NC
NC
NF
SCL
NC
NF
NF
NF
NF
NF
BAT+
44
1
2
43
3
42
4
41
40
5
39
6
7
38
8
37
36
9
35
10
11 M41T256Y 34
33
12
13
32
14
31
15
30
16
29
17
28
27
18
26
19
20
25
21
24
23
22
NC
NC
NF
RST
NF
NF
NF
NF
NF
NF
NF
TP
NC
NF
NF
NF
NF
SDA
VSS
VSS
NC
VSS
44
1
2
43
3
42
4
41
40
5
39
6
7
38
8
37
36
9
35
10
11 M41T256Y 34
33
12
13
32
14
31
15
30
16
29
17
28
27
18
26
19
20
25
21
24
23
22
AI04755b
VCC
NC
NC
NC
FT
NF
NF
NF
NF
NF
NF
NC
NC
NF
SCL
NC
NF
NF
NF
NF
NF
NC
AI07022
Note: No Function (NF) must be tied to VSS.
Figure 6. Block Diagram
PULL-UP TO
CHIP VCC
REAL TIME CLOCK
CALENDAR
32,752 BYTES
USER RAM
SDA
I2C
INTERFACE
RTC
& CALIBRATION
SCL
TAMPER BIT
32KHz
OSCILLATOR
Crystal
FT(1)
TP
POWER
VCC
VBAT
VBL= 2.5V
COMPARE
VSO = VBAT
COMPARE
BL
VPFD = 4.38V
COMPARE
POR
RST(1)
AI04759
Note: 1. Open drain output
5/27
M41T256Y
OPERATING MODES
The M41T256Y clock operates as a slave device
on the serial bus. Access is obtained by implementing a start condition followed by the correct
slave address (D0h). The 256K bytes contained in
the device can then be accessed sequentially in
the following order:
0-7FEF = General Purpose RAM
7FF0-7FF6 = Reserved
7FF7h = Tenths/Hundredths Register
7FF8h = Control Register
7FF9h = Seconds Register
7FFAh = Minutes Register
7FFBh = Hour Register
7FFCh = Tamper/Day Register
7FFDh = Date Register
7FFEh = Month Register
7FFFh = Year Register
The M41T256Y clock continually monitors VCC for
an out-of tolerance condition. Should VCC fall below VPFD, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from an out-of-tolerance system.
When VCC falls below VSO, the device automatically switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
VCC rises above VSO, the battery is disconnected,
and the power supply is switched to external VCC.
Write protection continues until VCC reaches VPFD
plus tREC.
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
6/27
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The devices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one acknowledge clock pulse. This acknowledge clock pulse is a low level put on the bus by
the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate
an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
M41T256Y
Figure 7. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
(SCL) CLOCK
(SDA) DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI04756
Figure 8. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
1
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
7/27
M41T256Y
Figure 9. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tHD:STA
tF
tR
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
SR
tSU:STO
P
AI00589
Table 2. AC Characteristics
Parameter(1)
Symbol
fSCL
SCL Clock Frequency
tBUF
Time the bus must be free before a new transmission can start
tF
Min
Max
Unit
0
400
kHz
1.3
SDA and SCL Fall Time
tHD:DAT
Data Hold Time
tHD:STA
µs
300
0
µs
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tHIGH
Clock High Period
600
ns
tLOW
Clock Low Period
1.3
µs
tR
tSU:DAT(2)
SDA and SCL Rise Time
300
ns
Data Setup Time
100
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:STO
STOP Condition Setup Time
600
ns
Note: 1. Valid for Ambient Operating Temperature: TA = –25 to 70°C; VCC = 4.5 to 5.5V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
8/27
ns
M41T256Y
READ Mode
In this mode the master reads the M41T256Y
slave after setting the slave address (see Figure
10., page 9). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the byte addresses A(0) and A(1) are written to the on-chip
address pointer (MSB of address byte A(0) is a
“Don’t care”). Next the START condition and slave
address are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an acknowledge bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41T256Y slave transmitter will now
place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the
new byte and the address pointer is incremented
to An+2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure
11., page 10).
Note: Address pointer will wrap around from maximum address to minimum address if consecutive
READ or WRITE cycles are performed.
An alternate READ Mode may also be implemented whereby the master reads the M41T256Y slave
without first writing to the (volatile) address pointer. The first address that is read is the last one
stored in the pointer (see Figure 12., page 10).
Figure 10. Slave Address Location
R/W
START
A
1
LSB
MSB
SLAVE ADDRESS
1
0
1
0
0
0
AI00602
Note: The most significant bit is sent first.
9/27
M41T256Y
S
ACK
ACK
DATA n
ACK
BUS ACTIVITY:
BYTE
ADDRESS (1)
R/W
START
R/W
BYTE
ADDRESS (0)
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 11. READ Mode Sequence
SLAVE
ADDRESS
STOP
SLAVE
ADDRESS
P
NO ACK
DATA n+X
AI04760
ACK
DATA n+X
P
NO ACK
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
BUS ACTIVITY:
10/27
STOP
R/W
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 12. Alternate READ Mode Sequence
AI00895
M41T256Y
WRITE Mode
In this mode the master transmitter transmits to
the M41T256Y slave receiver. Bus protocol is
shown in Figure 13., page 11. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the addressed device that byte addresses A(0) and A(1)
will follow and is to be written to the on-chip address pointer (MSB of address byte A(0) is a
“Don’t care”).
The data byte to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge bit.
The M41T256Y slave receiver will send an acknowledge bit to the master transmitter after it has
received the slave address (see Figure
10., page 9) and again after it has received each
address byte.
STOP
R/W
SLAVE
ADDRESS
DATA n+X
ACK
ACK
BUS ACTIVITY:
DATA n
P
ACK
BYTE
ADDRESS (1)
BYTE
ADDRESS (0)
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 13. WRITE Mode Sequence
AI04761
11/27
M41T256Y
Data Retention Mode
With valid VCC applied, the M41T256Y can be accessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the
M41T256Y will automatically deselect, write protecting itself when VCC falls between VPFD (max)
and VPFD (min). This is accomplished by internally
inhibiting access to the clock registers. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
When VCC falls below the Battery Back-up
Switchover Voltage (VSO), power input is switched
from the VCC pin to the external battery and the
clock registers and SRAM are maintained from the
attached battery supply.
All outputs become high impedance. On power up,
when VCC returns to a nominal value, write protection continues for tREC. The RST signal also remains active during this time (see Figure
17., page 21).
For a further more detailed review of lifetime calculations, please see Application Note AN1012.
Sleep Mode
In order to minimize the battery current draw while
in storage, the M41T256Y provides the user with a
battery “Sleep Mode,” which disconnects the RAM
memory array from the external Lithium battery
normally used to provide non-volatile operation in
the absence of VCC. This can significantly extend
the lifetime of the battery, when non-volatile operation is not needed.
12/27
Note: The Sleep Mode will remove power from the
RAM array only and not affect the data retention of
the TIMEKEEPER Registers (7FF0h through
7FFFh - this includes the Calibration Register).
The Sleep Mode (SLP) Bit located in register
7FF8h (D6), must be set to a '1' by the user while
the device is powered by VCC. This will “arm” the
Sleep Mode latch, but not actually disconnect the
RAM array from power until the next power-down
cycle. This protects the user from immediate data
loss in the event he inadvertently sets the SLP Bit.
Once VCC falls below VSO (VBAT), the Sleep Mode
circuit will be engaged and the RAM array will be
isolated from the battery, resulting in both a lower
battery current, and a loss of RAM data.
Note: Upon initial battery attach or initial power
application without the battery, the state of the
SLP Bit will be undetermined. Therefore, the SLP
Bit should be initialized to '0' by the user.
Additional current reduction can be achieved by
setting the STOP (ST) Bit in register 7FF9h (D7),
turning off the clock oscillator. This combination
will result in the longest possible battery life, but
also loss of time and data. When the device is
again powered-up, the user should first read the
SLP Bit to determine if the device is currently in
Sleep Mode, then reset the bit to '0' in order to disable the Sleep Mode (this will NOT be automatically taken care of during the power-up).
Note: See AN1570, “M41T256Y Sleep Mode
Function” for more information on Sleep Mode and
battery lifetimes.
M41T256Y
CLOCK OPERATION
Year, Month, and Date are contained in the last
three registers of the TIMEKEEPER® Register
Map (see Table 3., page 14). Bits D0 through D2
of the next register contain the Day (day of week).
Finally, there are the registers containing the Seconds, Minutes, and Hours, respectively. The first
clock register is the Control Register (this is described in the Clock Calibration section).
The nine Clock Registers may be read one byte at
a time, or in a sequential block. The Control Register (Address location 7FF8h) may be accessed
independently. Provision has been made to assure that a clock update does not occur while any
of the nine clock addresses are being read. If a
clock address is being read, an update of the clock
registers will be halted. This will prevent a transition of data during the read.
Reading the Clock
The nine byte clock register (see Table
3., page 14) is used to both set the clock and to
read the date and time from the clock, in a binary
coded decimal format. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (7FF9h to
7FFFh). The update will resume either due to a
Stop Condition or when the pointer increments to
a RAM address.
This prevents reading data in transition. The
TIMEKEEPER® cells in the Register Map are only
data registers and not actual clock counters, so
updating the registers can be halted without disturbing the clock itself.
Setting the Clock
Bit D7 of the Control Register (7FF8h) is the Write
Clock Bit. Setting the Write Clock Bit to a '1' will allow the user to write the desired Day, Date, and
Time data in 24-hour BCD format. Resetting the
Write Clock Bit to a '0' then transfers the values of
all time registers (7FF8h-7FFFh) to the actual
clock counters and resets the internal divider (or
clock) chain.
Note: The Tenths/Hundredths of Seconds Register will automatically be reset to zero when the
WRITE Clock Bit is set.
Other register bits such as FT, TEB, and ST may
be written without setting the WC Bit. In such cases, the clock data will be undisturbed and will retain their previous values.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The Stop Bit
(ST) is the most significant bit of the Seconds Register. Setting it to '1' stops the oscillator. Setting it
to '0' restarts the oscillator in approximately one
second.
13/27
M41T256Y
Table 3. TIMEKEEPER® Register Map
Data
Address
D7
7FFFh
D6
D5
D4
D3
D2
10 Years
D0
Function/Range
BCD Format
Year
Year
00-99
Month
Month
01-12
Date: Day of Month
Date
01-31
Tamper/Day
0-1/01-07
Hours (24 Hour Format)
Hours
00-23
7FFEh
0
0
7FFDh
0
0
7FFCh
BL
FT
7FFBh
0
0
7FFAh
0
10 Minutes
Minutes
Minutes
00-59
7FF9h
ST
10 Seconds
Seconds
Seconds
00-59
7FF8h
WC
7FF7h
SLP
0
D1
10M
10 Date
TEB
TB
0
10 Hours
S
Day of Week
Calibration
0.1 Seconds
Control
0.01 Seconds
Seconds
7FF6h
X
X
X
X
X
X
X
X
Reserved
7FF5h
X
X
X
X
X
X
X
X
Reserved
7FF4h
X
X
X
X
X
X
X
X
Reserved
7FF3h
X
X
X
X
X
X
X
X
Reserved
7FF2h
X
X
X
X
X
X
X
X
Reserved
7FF1h
X
X
X
X
X
X
X
X
Reserved
7FF0h
X
X
X
X
X
X
X
X
Reserved
BL = Battery Low Flag (Read only bit)
Keys: S = Sign Bit
TB = Tamper Bit (Read only bit)
FT = Frequency Test Bit
TEB = Tamper Enable Bit
ST = Stop Bit
0 = Must be set to '0'
WC = Write Clock Bit
SLP = Sleep Mode Bit
X = '1' or '0'
Note: 7FF0h through 7FF6h are invalid addresses and when read will return arbitrary data.
14/27
00-99
M41T256Y
Power-on Reset
The M41T256Y continuously monitors VCC. When
VCC falls to the power fail detect trip point, the RST
pulls low (open drain) and remains low on powerup for tREC after VCC passes VPFD (max). The RST
pin is an open drain output and an appropriate
pull-up resistor should be chosen to control rise
time.
Tamper Indication Circuit
The M41T256Y provides an independent input
pin, the Tamper Pin (TP) which can be used to
monitor a signal which can result in the setting of
the Tamper Bit (TB) if the Tamper Enable Bit
(TEB) is set to a '1.'
The Tamper Pin is triggered by being connected to
VCC/VBAT through an external switch. This switch
is normally open in the application, allowing the pin
to be “floating” (internally latched to VSS when TEB
is set). When this switch is closed (connecting the
pin to VCC/VBAT), the Tamper Bit will be immediately set. This allows the user to determine if the
device has been physically moved or tampered
with. The Tamper Bit is a “read only” bit and is reset only by taking the Tamper Pin to ground and
resetting the Tamper Enable Bit to '0.'
This function operates both under normal power,
and in battery back-up. If the switch closes during
a power-down condition, the bit will still be set correctly.
Note: Upon initial battery attach or initial power
application without the battery, the state of TEB
(and TB) will be undetermined. Therefore TEB
must be initialized to a '0.'
Tamper Event Time-Stamp
If a tamper occurs, not only will the Tamper Bit be
set, but the event will also automatically be timestamped. This is accomplished by freezing the
normal update of the clock registers (7FF7h
through 7FFFh) immediately following a tamper
event. Thus, when tampering occurs, the user may
first read the time registers to determine exactly
when the tamper event occurred, then re-enable
the clock update to the current time (and reset the
Tamper Bit, TB) by resetting the Tamper Enable
Bit (TEB).
The time update will then resume, and after either
a Stop Condition or incrementing the address
pointer to a RAM address and back, the clock can
be read to determine the current time.
Note: The Tamper Bit (TB) must always be set to
'0' in order to read the current time.
Calibrating the Clock
The M41T256Y is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The
devices are tested not exceed ±35 ppm (parts per
million) oscillator frequency error at 25oC, which
equates to about ±1.53 minutes per month. When
the Calibration circuit is properly employed, accuracy improves to better than +1/–2 ppm at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 14., page 16). Therefore, the
M41T256Y design employs periodic counter correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure
15., page 16. The number of times pulses which
are blanked (subtracted, negative calibration) or
split (added, positive calibration) depends upon
the value loaded into the five Calibration bits found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register (7FF8h).
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit;
'1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64
minute cycle. The first 62 minutes in the cycle
may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator
cycles. If a binary '1' is loaded into the register,
only the first 2 minutes in the 64 minute cycle will
be modified; if a binary 6 is loaded, the first 12 will
be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
15/27
M41T256Y
Figure 14. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
∆F = K x (T –T )2
O
F
–100
K = –0.036 ppm/°C2 ± 0.006 ppm/°C2
–120
TO = 25°C ± 5°C
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999b
Figure 15. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
16/27
M41T256Y
The FT pin is an open drain output which requires
a pull-up resistor to VCC for proper operation. A
500 to 10k resistor is recommended in order to
control the rise time. The FT Bit is cleared on power-down.
Battery Low Warning
The M41T256Y automatically performs battery
voltage monitoring upon power-up. The Battery
Low (BL) Bit, Bit D7 of Day Register, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL Bit will remain asserted
until completion of battery replacement and subsequent battery low monitoring tests, during the
next power-up sequence.
If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed. The battery may
be replaced while VCC is applied to the device.
The M41T256Y only monitors the battery when a
nominal VCC is applied to the device. Thus applications which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
Preferred Power-on/Battery Attach Defaults
See Table 4, below.
Two methods are available for ascertaining how
much calibration a given M41T256Y may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate reference and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934: TIMEKEEPER
CALIBRATION. This allows the designer to give
the end user the ability to calibrate the clock as the
environment requires, even if the final product is
packaged in a non-user serviceable enclosure.
The designer could provide a simple utility that accesses the Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the
FT pin. The pin will toggle at 512Hz, when the Stop
Bit (ST) is '0,' and the Frequency Test Bit (FT) is
'1.'
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (XX001010) to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency Test output frequency.
Table 4. Preferred Default Values
Condition
WC
TEB(1)
TB(1)
FT
ST(1)
SLP(1)
Battery Attach or Initial Power-up
0
X
X
0
X
X
Power-Cycling (with battery)
0
UC
UC
0
UC
UC
Note: 1. X = Undetermined; UC = Unchanged
17/27
M41T256Y
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 5. Absolute Maximum Ratings
Symbol
TSTG
TSLD(1)
Parameter
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
Value
Unit
SNAPHAT®
–40 to 85
°C
SOIC
–55 to 125
°C
260
°C
–0.3 to VCC + 0.3
V
VIO
Input or Output Voltages
VCC
Supply Voltage
–0.3 to 7.0
V
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
18/27
M41T256Y
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 6. DC and AC Measurement Conditions
Parameter
M41T256Y
VCC Supply Voltage
4.5 to 5.5V
Ambient Operating Temperature
–25 to 70°C
Load Capacitance (CL)
100pF
Input Rise and Fall Times
≤ 50ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing Ref. Voltages
0.3VCC to 0.7VCC
Figure 16. AC Testing Input/Output Waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Table 7. Capacitance
Parameter(1,2)
Symbol
Max
Unit
7
pF
1000
pF
Input / Output Capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
Input Capacitance
CIN
CIO(3)
tLP
Input Capacitance (Tamper Pin)
Min
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
19/27
M41T256Y
Table 8. DC Characteristics
Sym
Test Condition(1)
Parameter
Min
Typ
Max
Unit
1.5
1.9
µA
1.0
1.4
µA
f = 400kHz
1.4
3.0
mA
SCL, SDA = VCC – 0.3V
1.0
2.5
mA
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
TA = 25°C, VCC = 0V, VBAT = 3.0V
Battery Current OSC ON
IBAT
Battery Current OSC OFF
ICC1
Supply Current
ICC2
Supply Current (Standby)
ILI
Input Leakage Current
ILO(2)
Output Leakage Current
VIH
Input High Voltage
0.7VCC
VCC + 0.3
V
VIHB
Input High Voltage in Battery Backup for Tamper Pin
VBAT –
Vdiode
VBAT
V
Input Low Voltage
–0.3
0.3VCC
V
VBAT
Battery Voltage
2.5
3.5
V
VOH
Output High Voltage
VCC + 0.3
V
VIL
VOL
Output Low Voltage
IOL = 3.0mA
0.4
V
Output Low Voltage (Open Drain)(3)
IOL = 10mA
0.4
V
4.50
V
VPFD
Power Fail Deselect
VSO
Battery Back-up Switchover
RSW
Switch Resistance on Tamper Pin
4.20
VBAT
V
Ω
500
Note: 1. Valid for Ambient Operating Temperature: TA = –25 to 70°C; VCC = 4.5 to 5.5V (except where noted).
2. Outputs deselected.
3. For RST and FT pin (Open Drain).
Table 9. Crystal Electrical Characteristics (Externally Supplied)
Symbol
Parameter(1,2)
f0
Resonant Frequency
RS
Series Resistance
CL
Load Capacitance
Typ
Min
Max
32.768
kHz
35
12.5
Unit
kΩ
pF
Note: 1. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S:
1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at [email protected] or http://www.kdsj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T256Y. Circuit board layout considerations for the 32.768kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
20/27
M41T256Y
Figure 17. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tRB
tDR
INPUTS
RECOGNIZED
tREC
DON'T CARE
RECOGNIZED
RST
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI04757
Table 10. Power Down/Up AC Characteristics
Symbol
Parameter(1)
Min
Typ
Max
Unit
tF(2)
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
tFB(3)
VPFD (min) to VSS VCC Fall Time
10
µs
tR
VPFD (min) to VPFD (max) VCC Rise Time
10
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
tREC
Power up Deselect Time
40
tDR
Expected Data Retention Time (OSC On, Sleep Mode
Off)
15(4)
200
ms
YEARS
Note: 1. Valid for Ambient Operating Temperature: TA = –25 to 70°C; VCC = 4.5 to 5.5V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. At 25°C and VCC = 0V, using a BR2330 Li Battery. This drops to 7.2 years when using the M4T32-BR12SH with the oscillator running.
21/27
M41T256Y
PACKAGE MECHANICAL INFORMATION
Figure 18. SOH44 – 44-lead Plastic, Hatless, Small Package Outline
A2
A
C
B
e
CP
D
N
E
H
A1
α
L
1
SOH-C
Note: Drawing is not to scale.
Table 11. SOH44 – 44-lead Plastic, Hatless, Small Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
Max
3.05
0
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.46
0.014
0.018
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
44
e
CP
22/27
Max
0.81
0.032
44
0.10
0.004
M41T256Y
Figure 19. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 12. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.46
0.014
0.018
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
44
e
CP
0.81
0.032
44
0.10
0.004
23/27
M41T256Y
Figure 20. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal Outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 13. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Mechanical Data
mm
inches
Symb
Typ
Min
A
Typ
Min
10.54
Max
0.415
A1
8.00
8.51
0.315
.0335
A2
7.24
8.00
0.285
0.315
A3
24/27
Max
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
.0710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
M41T256Y
PART NUMBERING
Table 14. Ordering Information Scheme
Example:
M41T
256Y
MT
7
E
Device Type
M41T
Supply Voltage and Write Protect Voltage
256Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
Package
MT = 44-lead, Hatless SOIC
MH(1) = SOH44
Temperature Range
7 = –25 to 70°C
Shipping Method
For SO44:
blank = Tubes (Not for New Design - Use E)
E = Lead-free Package (ECO
PACK®), Tubes
F = Lead-free Package (ECO
PACK®), Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
For SOH44:
blank = Tubes (Not for New Design - Use E)
E = Lead-free Package (ECO
PACK®), Tubes
F = Lead-free Package (ECO
PACK®), Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
Note: 1. The SOIC package (SOH44) requires the SNAPHAT® battery package which is ordered separately under the part number “M4TxxBR12SH” in plastic tube or “M4Txx-BR12SHTR” in Tape & Reel form (see Table 15).
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
Table 15. SNAPHAT® Battery Table
Part Number
M4T32-BR12SH
Description
Lithium Battery (120mAh) SNAPHAT
Package
SH
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M41T256Y
REVISION HISTORY
Table 16. Document Revision History
Date
Version
February 2002
1.0
First Issue
26-Apr-02
1.1
Addition of “Tamper Event Time-Stamp” text
31-May-02
1.2
Add Sleep Mode, 44-pin with SNAPHAT package (Figure 2, 5, 19, 20; Table 1, 5, 14, 15,
12, 13)
03-Jul-02
1.3
Modify Crystal Electrical Characteristics table footnotes (Table 9)
12-Jul-02
1.4
Added programmable Sleep Mode information to document (Figure 3, 4, 5, 6; Table 3, 4)
29-Jul-02
1.5
Add “Hatless” to package description (Figure 1, 18 and Table 14, 11)
20-Dec-02
2.0
ICC Characteristics changed (Table 8); Document promoted to “Datasheet”
04-Jan-03
2.1
Add VOL value (Table 8)
26-Mar-03
2.2
Update test condition (Table 10)
15-Jun-04
3.0
Reformatted; add Lead-free information; update characteristics (Figure 14; Table 5, 14)
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Revision Details
M41T256Y
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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