M48T248Y M48T248V 5.0 or 3.3V, 1024K TIMEKEEPER® SRAM with PHANTOM FEATURES SUMMARY ■ 5.0V OR 3.3V OPERATING VOLTAGE ■ REAL TIME CLOCK KEEPS TRACK OF TENTHS/HUNDREDTHS OF SECONDS, SECONDS, MINUTES, HOURS, DAYS, DATE OF THE MONTH, MONTHS, and YEARS ■ AUTOMATIC LEAP YEAR CORRECTION VALID UP TO THE YEAR 2100 ■ AUTOMATIC SWITCH-OVER and DESELECT CIRCUITRY ■ CHOICE OF POWER-FAIL DESELECT VOLTAGES: (VPFD = Power-fail Deselect Voltage): – M48T248Y: 4.25V ≤ VPFD ≤ 4.50V – M48T248V: 2.80V FULL 10% VCC OPERATING RANGE ■ OVER 10 YEARS’ DATA RETENTION IN THE ABSENCE OF POWER ■ WATCH FUNCTION IS TRANSPARENT TO RAM OPERATION ■ 128K x 8 NV SRAM DIRECTLY REPLACES VOLATILE STATIC RAM OR EEPROM Rev. 2.0 32 1 PMDIP32 (PM) ≤ VPFD ≤ 2.97V ■ March 2003 Figure 1. 32-pin, DIP Package 1/24 M48T248Y, M48T248V TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .....4 .....4 .....4 .....5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. Memory READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. Memory WRITE Cycle 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 8. Memory WRITE Cycle 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Memory AC Characteristics, M48T248Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Memory AC Characteristics, M48T248V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PHANTOM CLOCK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10. Comparison Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AM-PM/12/24 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Oscillator and Reset Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/24 M48T248Y, M48T248V Zero Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 10. Phantom Clock Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11. Phantom Clock READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12. Phantom Clock WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 13. Phantom Clock Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. Phantom Clock AC Characteristics (M48T248Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 12. Phantom Clock AC Characteristics (M48T248V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3/24 M48T248Y, M48T248V SUMMARY DESCRIPTION The M48T248Y/V TIMEKEEPER® RAM is a 128Kbit x 8 non-volatile static RAM and real time clock organized as 131,072 words by 8 bits. The special DIP package provides a fully integrated battery back-up memory and real time clock solution. In the event of power instability or absence, a self-contained battery maintains the timekeeping operation and provides power for a CMOS static RAM. Control circuitry monitors VCC and invokes write protection to prevent data corruption in the memory and RTC. The clock keeps track of tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, Figure 2. Logic Diagram and year information. The last day of the month is automatically adjusted for months with less than 31 days, including leap year correction. The clock operates in one of two formats: – a 12-hour mode with an AM/PM indicator; or – a 24-hour mode The M48T248Y/V is a 32-pin (PM) DIP module that integrates the RTC, the battery, and SRAM in one package. The modules are shipped in plastic, anti-static tubes (see Table 14, page 22). Table 1. Signal Names A0–A16 VCC A0-A16 DQ0-D7 WE CE M48T248Y M48T248V OE RST Address Input RST Reset Input CE Chip Enable OE Output Enable Input WE WRITE Enable Input DQ0–DQ7 Data Inputs/Outputs VCC Supply Voltage Input VSS Ground Figure 3. DIP Connections RST VSS AI04661 1 32 VCC A16 2 31 A15 A14 3 30 NC A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 A4 8 M48T248Y M48T248V 26 A9 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE A0 12 21 DQ7 DQ0 13 20 DQ6 DQ5 DQ1 14 19 DQ2 15 18 DQ4 VSS 16 17 DQ3 AI04662 4/24 M48T248Y, M48T248V Figure 4. Block Diagram XO CLOCK/CALENDAR LOGIC 32.768 Hz CRYSTAL XI UPDATE READ CE OE WE TIMEKEEPER REGISTER WRITE CONTROL LOGIC POWER FAIL RST A0–A16 SRAM ACCESS ENABLE SEQUENCE DETECTOR DQ0 I/O BUFFERS DQ0–DQ7 COMPARISON REGISTER DATA INTERNAL VCC VCC POWER-FAIL DETECT LOGIC VBAT AI04238 5/24 M48T248Y, M48T248V MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol TA Parameter Operating Temperature Value Unit 0 to 70 °C TSTG Storage Temperature (VCC, Oscillator Off) –40 to 85 °C TSLD(1) Lead Solder Temperature for 10 seconds 260 °C M48T248Y –0.3 to +7.0 V M48T248V –0.3 to +4.6 V –0.3 to VCC + 0.3 V VCC Supply Voltage (on any pin relative to Ground) VIO Input or Output Voltages IO Output Current 20 mA PD Power Dissipation 1 W Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). CAUTION! Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up Mode. 6/24 M48T248Y, M48T248V DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. DC and AC Measurement Conditions Parameter M48T248Y M48T248V 4.5 to 5.5V 3.0 to 3.6V 0 to 70°C 0 to 70°C Load Capacitance (CL) 100pF 50pF Input Rise and Fall Times ≤ 5ns ≤ 5ns 0 to 3V 0 to 3V 1.5V 1.5V VCC Supply Voltage Ambient Operating Temperature Input Pulse Voltages Input and Output Timing Ref. Voltages Note: Output High Z is defined as the point where data is no longer driven (see Table 3, page 7). Figure 5. AC Testing Load Circuit VCCI 1.1 KΩ DEVICE UNDER TEST 680 Ω CL = 50 pF AI04240 Note: 50pF for M48T248V. Table 4. Capacitance Symbol CIN CIO(3) Parameter(1,2) Min Max Unit Input Capacitance 10 pF Input / Output Capacitance 10 pF Note: 1. Effective capacitance measured with power supply at 5V. Sampled only; not 100% tested. 2. At 25°C, f = 1MHz. 3. Outputs were deselected. 7/24 M48T248Y, M48T248V Table 5. DC Characteristics Sym Parameter Test Condition(1) Min ILI(2) Input Leakage Current ILO M48T248Y M48T248V –70 –85 Typ 0V ≤ VIN ≤ VCC Max Min Typ Unit Max ±1 ±1 µA Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 ±1 µA ICC1 Supply Current 85 50 mA ICC2 Supply Current (TTL Standby) ICC3 VCC Power Supply Current VIL(3) Input Low Voltage –0.3 0.8 VIH(3) Input High Voltage 2.2 VCC + 0.3 VOL Output Low Voltage IOL = 2.0 mA VOH Output High Voltage IOH = –1.0 mA VPFD(3) Power Fail Deselect VSO(3) Battery Back-up Switchover CE = VIH 5 10 5 7 mA CE = VCCI – 0.2 3 5 2 3 mA –0.3 0.6 V 2.2 VCC + 0.3 V 0.4 V 0.4 2.4 4.25 2.4 4.37 VBAT 4.50 2.80 V 2.86 2.97 2.5 Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. RST (Pin 1) has an internal pull-up resistor. 3. All voltages are referenced to Ground. 8/24 V V M48T248Y, M48T248V OPERATION MODES Table 6. Operating Modes VCC Mode Deselect 4.5V to 5.5V or 3.0V to 3.6V WRITE READ READ CE OE WE DQ7-DQ0 Power VIH X X High-Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT Active VIL VIH VIH High-Z Active Deselect VSO to VPFD (min)(1) X X X High-Z CMOS Standby Deselect ≤ VSO(1) X X X High-Z Battery Back-Up Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage 1. See Table 9, page 14 for details. READ A READ cycle executes whenever WRITE Enable (WE) is high and Chip Enable (CE) is low (see Figure 6). The distinct address defined by the 19 address inputs (A0-A18) specifies which of the 512K bytes of data is to be accessed. Valid data will be accessed by the eight data output drivers within the specified Access Time (tACC) after the last address input signal is stable, the CE and OE access times, and their respective parameters are satisfied. When CE tACC and OE tACC are not satisfied, then data access times must be measured from the more recent CE and OE signals, with the limiting parameter being tCO (for CE) or tOE (for OE) instead of address access. WRITE WRITE Mode (see Figure 7, page 10 and Figure 8, page 11) occurs whenever CE and WE signals are low (after address inputs are stable). The most recent falling edge of CE and WE will determine when the WRITE cycle begins (the earlier, rising edge of CE or WE determines cycle termination). All address inputs must be kept stable throughout the WRITE cycle. WE must be high (inactive) for a minimum recovery time (tWR) before a subsequent cycle is initiated. The OE control signal should be kept high (inactive) during the WRITE cycles to avoid bus contention. If CE and OE are low (active), WE will disable the outputs for Output Data WRITE Time (tODW) from its falling edge. Figure 6. Memory READ Cycle tRC ADDRESSES tACC tOH tCO CE tOD tOE OE tCOE tODO tCOE DQ0 - DQ7 DATA OUTPUT VALID AI04230 Note: WE is high for a READ cycle. 9/24 M48T248Y, M48T248V Figure 7. Memory WRITE Cycle 1 tWC ADDRESSES tAW CE tWR tWP WE tOEW tODW HIGH IMPEDANCE DQ0–DQ7 tDH tDS DATA IN STABLE AI04231 Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state. 2. If the CE low transition occurs simultaneously with or later than the WE low transition in WRITE Cycle 1, the output buffers remain in a high impedance state during this period. 3. If the CE high transition occurs simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. 10/24 M48T248Y, M48T248V Figure 8. Memory WRITE Cycle 2 tWC ADDRESSES tAW tWP tWR CE tOEW WE tODW tCOE DQ0–DQ7 tDS tDH DATA IN STABLE AI04232 Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state. 2. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 11/24 M48T248Y, M48T248V Table 7. Memory AC Characteristics, M48T248Y Parameter(1) Symbol M48T248Y–70 Unit Min Max tAVAV tRC READ Cycle Time tAVQV tACC Access Time 70 ns tELQV tCO Chip Enable Low to Output Valid 70 ns tGLQV tOE Output Enable Low to Output Valid 35 ns tELQX tGLQX tCOE Chip Enable or Output Enable Low to Output Transition 5 ns tAXQX tOH Output Hold from Address Change 5 ns tEHQZ tGHQZ tOD(2) tWLQZ tODW(2) tAVAV tWC tWLWH tELEH 70 ns Chip Enable or Output Enable High to Output Hi-Z 25 ns Output Hi-Z from WE 25 ns WRITE Cycle Time 70 ns tWP(3) WE, CE Pulse Width 50 ns tAVEL tAVWL tAW Address Setup Time 0 ns tEHAX tWR1 WRITE Recovery Time 15 ns tWHAX tWR2 Address Hold Time from WE 0 ns tWHQX tOEW Output Active from WE 5 ns tDVEH tDVWH tDS(4) Data Setup Time 30 ns tWHDX tDH1(4) Data Hold Time from WE 0 ns tEHDX tDH2(4) Data Hold Time from CE 10 ns Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. These parameters are sampled with a 5 pF load are not 100% tested. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH and tDS are measured from the earlier of CE or WE going high. 12/24 M48T248Y, M48T248V Table 8. Memory AC Characteristics, M48T248V Parameter(1) Symbol M48T248V–85 Unit Min Max tAVAV tRC READ Cycle Time tAVQV tACC Access Time 85 ns tELQV tCO Chip Enable Low to Output Valid 85 ns tGLQV tOE Output Enable Low to Output Valid 45 ns tELQX tGLQX tCOE Chip Enable or Output Enable Low to Output Transition 5 ns tAXQX tOH Output Hold from Address Change 5 ns tEHQZ tGHQZ tOD(2) tWLQZ tODW(2) tAVAV tWC tWLWH tWP1(3) tELEH 85 ns Chip Enable or Output Enable High to Output Hi-Z 35 ns Output Hi-Z from WE 30 ns WRITE Cycle Time 85 ns WRITE Enable Pulse Width 65 ns tWP2 Chip Enable Pulse Width 75 ns tAVEL tAVWL tAW Address Setup Time 0 ns tEHAX tWR1(4) WRITE Recovery Time 15 ns tWHAX tWR2(4) Address Hold Time from WE 5 ns tWHQX tOEW Output Active from WE 5 ns tDVEH tDVWH tDS(5) Data Setup Time 35 ns tWHDX tDH1(5) Data Hold Time from WE 0 ns tEHDX tDH2(5) Data Hold Time from CE 15 ns Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. These parameters are sampled with a 5 pF load are not 100% tested. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tWR is a function of the latter occurring edge of WE or CE. 5. tDH and tDS are measured from the earlier of CE or WE going high. 13/24 M48T248Y, M48T248V Data Retention Mode Data can be read or written only when VCC is greater than VPFD. When VCC is below VPFD (the point at which write protection occurs), the clock registers and the SRAM are blocked from any access. When VCC falls below the Battery Switch Over threshold (VSO), the device is switched from VCC to battery backup (VBAT). RTC operation and SRAM data are maintained via battery backup until power is stable. All control, data, and address signals must be powered down when VCC is powered down. The lithium power source is designed to provide power for RTC activity as well as RTC and RAM data retention when VCC is absent or unstable. The capability of this source is sufficient to power the device continuously for the life of the equipment into which it has been installed. For specification purposes, life expectancy is ten (10) years at 25°C with the internal oscillator running without VCC. Each unit is shipped with its energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPFD, the energy source is enabled for battery backup operation. The actual life expectancy will be much longer if no battery energy is used (e.g., when VCC is present). Figure 9. Power Down/Up Mode AC Waveforms VCC tF tR VPFD (max) VPFD (min) VSO tFB tREC tPD CE tDR AI04236 Table 9. Power Down/Up Trip Points DC Characteristics Symbol Parameter(1) Min Max Unit VPFD (max) to CE low 1.5 2.5 ms tF VPFD (max) to VPFD (min) VCC Fall Time 300 µs tFB VPFD (min) to VSO VCC Fall Time 10 µs tR VPFD (min) to VPFD (max) VCC Rise Time 0 µs CE High to Power-Fail 0 µs Expected Data Retention Time 10 Years tREC tPD tDR(2) Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. At 25°C, VCC = 0V; the expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator running. 14/24 M48T248Y, M48T248V PHANTOM CLOCK OPERATION Communication with the Phantom Clock is established by pattern recognition of a serial bit-stream of 64 bits which must be matched by executing 64 consecutive WRITE cycles containing the proper data on DQ0. All accesses which occur prior to recognition of the 64-bit pattern are directed to memory. After recognition is established, the next 64 READ or WRITE cycles either extract or update data in the clock while disabling the memory. Data transfer to and from the timekeeping function is accomplished with a serial bit-stream under control of Chip Enable (CE), Output Enable (OE), and WRITE Enable (WE). Initially, a READ cycle using the CE and OE control of the clock starts the pattern recognition sequence by moving the pointer to the first bit of the 64-bit comparison register (see Figure 10, page 16). Next, 64 consecutive WRITE cycles are executed using the CE and WE control of the device. These 64 WRITE cycles are used only to gain access to the clock. Therefore, any address to the memory is acceptable. However, the WRITE cycles generated to gain access to the Phantom Clock are also writing data to a location in the mated RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a Phantom Clock scratch pad. When the first WRITE cycle is executed, it is compared to Bit 1 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next WRITE cycle. If a match is not found, the pointer does not advance and all subsequent WRITE cycles are ignored. If a READ cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 WRITE cycles as described above until all of the bits in the comparison register have been matched. With a correct match for 64-bits, the Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom Clock. 15/24 M48T248Y, M48T248V Figure 10. Comparison Register Definition Hex Value 7 6 5 4 3 2 1 0 BYTE 0 1 1 0 0 0 1 0 1 C5 BYTE 1 0 0 1 1 1 0 1 0 3A BYTE 2 1 0 1 0 0 0 1 1 A3 BYTE 3 0 1 0 1 1 1 0 0 5C BYTE 4 1 1 0 0 0 1 0 1 C5 BYTE 5 0 0 1 1 1 0 1 0 3A BYTE 6 1 0 1 0 0 0 1 1 A3 BYTE 7 0 1 0 1 1 1 0 0 5C AI04262 Note: The odds of this pattern being accidentally duplicated and sending aberrant entries to the RTC is less than 1 in 1019. This pattern is sent to the clock LSB to MSB. 16/24 M48T248Y, M48T248V Clock Register Information Clock information is contained in eight registers of 8 bits, each of which is sequentially accessed one (1) bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the clock registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These READ/WRITE registers are defined in the clock register map (see Table 10). Data contained in the clock registers is in Binary Coded Decimal format (BCD). Reading and writing the registers is always accomplished by stepping through all eight registers, starting with Bit 0 of Register 0 and ending with Bit 7 of Register 7. Clock Accuracy The RTC is guaranteed to keep time accuracy to with ±1 minute per month at 25°C. The clock is factory-tuned with special calibration elements, and does not require additional calibration. Moderate temperature deviation will have a negligible effect in most applications. AM-PM/12/24 Mode Bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. When it is high, the 12hour mode is selected. In the 12-hour mode, Bit 5 is the AM/PM bit with the logic high being “PM.” In the 24-hour mode, Bit 5 is the second 10-hour bit (20-23 hours). Oscillator and Reset Bits Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the reset pin input. When the reset bit is set to logic '1,' the Reset Input pin is ignored. When the reset bit logic is set to '0,' a low input on the reset pin will cause the device to abort data transfer without changing data in the timekeeping registers. Reset operates independently of all other inputs. Bit 5 controls the oscillator. When set to logic '0,' the oscillator turns on and the RTC/calendar begins to increment. Zero Bits Registers 1, 2, 3, 4, 5, and 6 contain one (1) or more bits that will always read logic '0.' When writing to these locations, either a logic '1' or '0' is acceptable. Table 10. Phantom Clock Register Map Register D7 0 D6 D5 D4 D3 0.1 Seconds D2 D1 D0 Function/Range BCD Format 0.01 Seconds Seconds 00-99 1 0 10 Seconds Seconds Seconds 00-59 2 0 10 Minutes Minutes Minutes 00-59 3 12/24 0 10 / A/P Hrs Hours (24 Hour Format) Hours 01-12/ 00-23 4 0 0 OSC RST Day 01-7 5 0 0 Date: Day of the Month Date 01-31 6 0 0 Month Month 01-12 Year Year 00-99 7 10 date 0 10 Years Keys: A/P = AM/PM Bit 12/24 = 12 or 24-hour mode Bit OSC = Oscillator Bit 10M 0 Day of the Week RST = Reset Bit 0 = Must be set to '0' 17/24 M48T248Y, M48T248V Figure 11. Phantom Clock READ Cycle WE tRC tCW tRR tCO CE tOD tOW OE tODO tOE tOEE tCOE DATA OUTPUT VALID Q AI04259 Figure 12. Phantom Clock WRITE Cycle OE tWC tWP tWR WE tWR tCW CE t DH tDH tDS D DATA INPUT STABLE AI04261 Figure 13. Phantom Clock Reset tRST RST AI04235 18/24 M48T248Y, M48T248V Table 11. Phantom Clock AC Characteristics (M48T248Y) Symbol Parameter(1) Min Typ Max Unit tAVAV tRC READ Cycle Time tELQV tCO CE Access Time 55 ns tGLQV tOE OE Access Time 55 ns tELQX tCOE CE to Output Low Z 5 ns tGLQX tOEE OE to Output Low Z 5 ns tEHQZ tOD(2) CE to Output High Z 25 ns tGHQZ tODO(2) OE to Output High Z 25 ns 65 ns tRR READ Recovery 10 ns tAVAV tWC WRITE Cycle Time 65 ns tWLWH tWP(3) WRITE Pulse Width 55 ns tEHAX tWR(4) WRITE Recovery 10 ns tDVEH tDS(5) Data Setup Time 30 ns tWHDX tDH1(5) Data Hold Time from WE 0 ns tEHDX tDH2(5) Data Hold Time from CE 0 ns tELEH tCW CE Pulse Width 55 ns tRST RST Pulse Width 65 ns Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. These parameters are sampled with a 5 pF load and are not 100% tested. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tWR is a function of the latter occurring edge of WE or CE. 5. tDH and tDS are measured from the earlier of CE or WE going high. 19/24 M48T248Y, M48T248V Table 12. Phantom Clock AC Characteristics (M48T248V) Symbol Parameter(1) Min Typ Max Unit tAVAV tRC READ Cycle Time tELQV tCO CE Access Time 85 ns tGLQV tOE OE Access Time 85 ns tELQX tCOE CE to Output Low Z 5 ns tGLQX tOEE OE to Output Low Z 5 ns tEHQZ tOD(2) CE to Output High Z 30 ns tGHQZ tODO(2) OE to Output High Z 30 ns 85 ns tRR READ Recovery 20 ns tAVAV tWC WRITE Cycle Time 85 ns tWLWH tWP(3) WRITE Pulse Width 60 ns tEHAX tWR(4) WRITE Recovery 20 ns tDVEH tDS(5) Data Setup Time 35 ns tWHDX tDH1(5) Data Hold Time from WE 0 ns tEHDX tDH2(5) Data Hold Time from CE 0 ns tELEH tCW CE Pulse Width 65 ns tRST RST Pulse Width 85 ns Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. These parameters are sampled with a 5 pF load and are not 100% tested. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tWR is a function of the latter occurring edge of WE or CE. 5. tDH and tDS are measured from the earlier of CE or WE going high. 20/24 M48T248Y, M48T248V PACKAGE MECHANICAL INFORMATION Figure 14. PMDIP32 – 32-pin Plastic Module DIP, Package Outline A A1 B S L C eA e1 e3 D N E 1 PMDIP Note: Drawing is not to scale. Table 13. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data mm inches Symb Typ Min Max A 9.27 A1 Typ Min Max 9.52 0.365 0.375 0.38 – 0.015 – B 0.43 0.59 0.017 0.023 C 0.20 0.33 0.008 0.013 D 42.42 43.18 1.670 1.700 E 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 e3 34.29 41.91 1.350 1.650 eA 14.99 16.00 0.590 0.630 L 3.05 3.81 0.120 0.150 S 1.91 2.79 0.075 0.110 N 32 32 21/24 M48T248Y, M48T248V PART NUMBERING Table 14. Ordering Information Example Example: M48T 248Y –70 PM 1 TR Device Type M48T Supply Voltage and Write Protect Voltage 248Y = VCC = 4.5 to 5.5V; VPFD = 4.25 to 4.50V 248V = VCC = 3.0 to 3.6V; VPFD = 2.80 to 2.97V Speed –70 = 70ns (M48T248Y) –85 = 85ns (M48T248V) Package PM = PMDIP32 Temperature Range 1 = 0 to 70°C Shipping Method for SOIC blank = Tubes TR = Tape & Reel For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 22/24 M48T248Y, M48T248V REVISION HISTORY Table 15. Document Revision History Date Rev. # Revision Details June 2001 1.0 First Issue 28-Mar-03 2.0 v2.2 template applied; test condition updated (Table 9) 23/24 M48T248Y, M48T248V M48T248, M48T248Y, M48T248V, 48T248, 48T248Y, 48T248V, T248, T248Y, T248V, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Powerfail, Power-fail, Power-fail, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup,5V,5V,5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V Information furnished is believed to be accurate and reliable. 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