M48T512Y M48T512V 3.3V-5V 4 Mbit (512Kb x8) TIMEKEEPER® SRAM ■ INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY, and CRYSTAL ■ BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS ■ AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION ■ WRITE PROTECT VOLTAGES: (VPFD = Power-fail Deselect Voltage) 32 1 – M48T512Y: 4.2V ≤ VPFD ≤ 4.5V – M48T512V: 2.7V ≤ VPFD ≤ 3.0V ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ SOFTWARE CONTROLLED CLOCK CALIBRATION FOR HIGH ACCURACY APPLICATIONS ■ 10 YEARS of DATA RETENTION and CLOCK OPERATION in the ABSENCE OF POWER ■ PIN and FUNCTION COMPATIBLE with INDUSTRY STANDARD 512K X 8 SRAMS ■ SELF-CONTAINED BATTERY and CRYSTAL in DIP PACKAGE DESCRIPTION The M48T512Y/V TIMEKEEPER RAM is a 512Kb x 8 non-volatile static RAM and real time clock organized as 524,288 words by 8 bits. The special DIP package provides a fully integrated battery back-up memory and real time clock solution. PMDIP32 (PM) Module Figure 1. Logic Diagram VCC 19 8 A0-A18 W DQ0-DQ7 M48T512Y M48T512V E Table 1. Signal Names A0-A18 Address Inputs DQ0-DQ7 Data Inputs / Outputs E Chip Enable Input G Output Enable Input W Write Enable Input VCC Supply Voltage VSS Ground December 1999 G VSS AI02262 1/14 M48T512Y, M48T512V Table 2. Absolute Maximum Ratings (1) Symbol TA Value Unit 0 to 70 °C –40 to 85 °C 260 °C –0.3 to VCC +0.3 V M48T512Y –0.3 to 7.0 V M48T512V –0.3 to 4.6 V Ambient Operating Temperature TSTG TSLD Parameter (2) Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds VIO Input or Output Voltages VCC Supply Voltage IO Output Current 20 mA PD Power Dissipation 1 W Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. Figure 2. DIP Connections A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 32 1 31 2 30 3 29 4 28 5 27 6 26 7 8 M48T512Y 25 9 M48T512V 24 23 10 22 11 21 12 20 13 19 14 18 15 17 16 VCC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 AI02263 The M48T512Y/V directly replaces industry standard 512Kb x 8 SRAMs. It also provides the nonvolatility of Flash without any requirement for special write timing or limitations on the number of writes that can be performed. 2/14 The 32 pin 600 mil DIP Hybrid houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single package. Figure 3 illustrates the static memory array and the quartz controlled clock oscillator. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - compliant until the year 2100), 30, and 31 day months are made automatically. Byte 7FFF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The seven clock bytes (7FFFFh-7FFF9h) are not the actual clock counters, they are memory locations consisting of BiPORT™ read/write memory cells within the static RAM array. The M48T512Y/V includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T512Y/V also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When V CC is out of tolerance, the circuit write protects the TIMEKEEPER register data and external SRAM, providing data security in the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored. READ MODE The M48T512Y/V is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The unique address specified by the 19 Address Inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Ac- M48T512Y, M48T512V Table 3. Operating Modes (1) Mode VCC Deselect Write Read 4.5V to 5.5V or 3.0V to 3.6V Read Deselect VSO to VPFD (min) Deselect ≤ VSO (2) (2) E G W DQ0-DQ7 Power VIH X X High Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT Active VIL VIH VIH High Z Active X X X High Z CMOS Standby X X X High Z Battery Back-up Mode Note: 1. X = VIH or VIL. 2. See Table 7 for details. cess Time (tAVQV) after the last address input signal is stable, providing the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access Times (t ELQV) or Output Enable Access Time (t GLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until t AVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold Time (t AXQX) but will go indeterminate until the next Address Access. WRITE MODE The M48T512Y/V is in the Write Mode whenever W (Write Enable) and E (Chip Enable) are low state after the address inputs are stable. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. Table 4. AC Measurement Conditions ≤ 5ns Input Rise and Fall Times Input Pulse Voltages 0 to 3V Input and Output Timing Ref. Voltages 1.5V Note that Output Hi-Z is defined as the point where data is no longer driven. Figure 3. AC Testing Load Circuit 650Ω DEVICE UNDER TEST CL = 100pF CL includes JIG capacitance 1.75V AI01803C 3/14 M48T512Y, M48T512V Figure 4. Block Diagram 8x8 TIMEKEEPER REGISTERS OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL A0-A18 POWER 524,280 x 8 SRAM ARRAY LITHIUM CELL E VOLTAGE SENSE AND SWITCHING CIRCUITRY VCC DATA RETENTION MODE With valid V CC applied, the M48T512Y/V operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high impedance and all inputs are treated as "don't care". Note: A power failure during a write cycle may corrupt data at the current addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the memory will be in a write protected state, provided the V CC fall time is not less than tF. The M48T512Y/V may respond to transient noise spikes on VCC that cross into the deselect window during the time the device is sampling VCC.Therefore, decoupling of the power supply lines is recommended. When V CC drops below VSO, the control circuit switches power to the internal battery, preserving data and powering the clock. The internal energy source will maintain data in the M48T512Y/V for an accumulated period of at least 10 years at room temperature. As system power rises above V SO, the battery is disconnected, and the power supply is 4/14 DQ0-DQ7 W VPFD G VSS AI02384 switched to external VCC. Write protection continues until V CC reaches VPFD (min) plus tER (min). Normal RAM operation can resume tER after V CC exceeds V PFD (max). Refer to Application Note (AN1012) on the ST Web Site for more information on battery life. CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORT TIMEKEEPER cells in the RAM array are only data registers, and not the actual clock counters, updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the Control Register (7FFF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs 1 second after the READ bit is reset to a '0'. M48T512Y, M48T512V Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol CIN CIO (2) Parameter Input Capacitance Input / Output Capacitance Test Condition Min Max Unit VIN = 0V 20 pF VOUT = 0V 20 pF Note: 1. Effective capacitance measured with power supply at 5V (M48T512Y) or 3.3V (M48T512V). Sampled only, not 100% tested. 2. Outputs deselected. Table 6A. DC Characteristics (TA = 0 to 70 °C; VCC = 4.5V to 5.5V) Symbol Parameter ILI (1) Input Leakage Current ILO (1) Output Leakage Current Test Condition Min Max Unit 0V ≤ VIN ≤ VCC ±2 µA 0V ≤ VOUT ≤ VCC ±2 µA Outputs open 115 mA E = VIH 8 mA E = VCC – 0.2V 4 mA ICC Supply Current ICC1 Supply Current (Standby) TTL ICC2 Supply Current (Standby) CMOS VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2.2 VCC + 0.3 V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage IOH = –1mA 2.4 Test Condition Min V Note: 1. Outputs deselected. Table 6B. DC Characteristics (TA = 0 to 70 °C; VCC = 3.0V to 3.6V) Symbol Parameter ILI (1) Input Leakage Current ILO (1) Output Leakage Current Max Unit 0V ≤ VIN ≤ VCC ±2 µA 0V ≤ VOUT ≤ VCC ±2 µA Outputs open 60 mA E = VIH 4 mA E = VCC – 0.2V 3 mA ICC Supply Current ICC1 Supply Current (Standby) TTL ICC2 Supply Current (Standby) CMOS VIL Input Low Voltage –0.3 0.4 V VIH Input High Voltage 2.2 VCC + 0.3 V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage IOH = –1mA 2.2 V Note: 1. Outputs deselected. 5/14 M48T512Y, M48T512V Figure 5. Power Down/Up Mode AC Waveforms tF VCC VPFD (max) VPFD (min) VSO VSS tWP tDR tR tFB INPUTS tER tRB DON'T CARE RECOGNIZED (Including E) RECOGNIZED HIGH-Z OUTPUTS VALID VALID AI02385 Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70 °C) Symbol Parameter VPFD Power-fail Deselect Voltage VSO Battery Back-up Switchover Voltage tDR (2) Min Typ Max Unit M48T512Y 4.2 4.35 4.5 V M48T512V 2.7 2.9 3.0 V M48T512Y 3.0 M48T512V VPFD –100mV Expected Data Retention Time V 10 YEARS Note: 1. All voltages referenced to VSS. 2. At 25°C. Table 8. Power Down/Up AC Characteristics (TA = 0 to 70 °C) Symbol tF (1) tFB (2) Parameter Min VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time Max Unit 300 µs M48T512Y 10 µs M48T512V 150 µs tR VPFD (min) to VPFD (max) VCC Rise Time 10 µs tRB VSS to VPFD (min) VCC Rise Time 1 µs tWP Write Protect Time on VCC = VPFD 40 150 µs tER E Recovery Time 40 200 ms Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes V PFD (min). 2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 6/14 M48T512Y, M48T512V Table 9. Read Mode AC Characteristics (TA = 0 to 70 °C) Symbol M48T512Y M48T512V -70 -85 Parameter Min tAVAV Read Cycle Time Max 70 Min Unit Max 85 ns tAVQV (1) Address Valid to Output Valid 70 85 ns tELQV (1) Chip Enable Low to Output Valid 70 85 ns tGLQV (1) Output Enable Low to Output Valid 40 55 ns tELQX (2) Chip Enable Low to Output Transition 5 5 ns tGLQX (2) Output Enable Low to Output Transition 5 5 ns tEHQZ (2) Chip Enable High to Output Hi-Z 25 30 ns tGHQZ (2) Output Enable High to Output Hi-Z 25 30 ns tAXQX (1) Address Transition to Output Transition 10 5 ns Note: 1. CL = 100pF. 2. CL = 5pF. Figure 6. Address Controlled, Read Mode AC Waveforms tAVAV VALID A0-A16 tAVQV tAXQX DQ0-DQ7 DATA VALID DATA VALID AI02324 Setting the Clock. Bit D7 of the Control Register (7FFF8h) is the WRITE bit. Setting the WRITE bit to a '1', like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 11). Resetting the WRITE bit to a '0' then transfers the values of all time registers 7FFFFh-7FFF9h to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur approximately one second later. See Application Note, AN923, (TIMEKEEPERS "ROLLING INTO" THE 21ST CENTURY) on the ST Web Site for more information on Century Rollover. Note: Upon power-up, both the WRITE bit and the READ bit will be reset to '0'. Stopping and Starting the Oscillator. The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is located at Bit D7 within 7FFF9h. Setting it to a '1' stops the oscillator. The M48T512Y/V is shipped from STMicroelectronics with the STOP bit set to a '1'. When reset to a '0', the M48T512Y/V oscillator starts after approximately one second. Note: It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST bit (FT) or the STOP bit (ST). 7/14 M48T512Y, M48T512V Table 10. Write Mode AC Characteristics (TA = 0 to 70 °C) Symbol M48T512Y M48T512V -70 -85 Parameter Min Max Min Unit Max tAVAV Write Cycle Time 70 85 ns tAVWL Address Valid to Write Enable Low 0 0 ns tAVEL Address Valid to Chip Enable Low 0 0 ns tWLWH Write Enable Pulse Width 50 60 ns tELEH Chip Enable Low to Chip Enable High 55 65 ns tWHAX Write Enable High to Address Transition 5 5 ns tEHAX Chip Enable High to Address Transition 10 15 ns tDVWH Input Valid to Write Enable High 30 35 ns tDVEH Input Valid to Chip Enable High 30 35 ns tWHDX Write Enable High to Input Transition 5 5 ns tEHDX Chip Enable High to Input Transition 10 15 ns tWLQZ (1, 2) Write Enable Low to Output Hi-Z 25 30 ns tAVWH Address Valid to Write Enable High 60 70 ns tAVE1H Address Valid to Chip Enable High 60 70 ns Write Enable High to Output Transition 5 5 ns tWHQX (1, 2) Note: 1. CL = 5pF. 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. Calibrating the Clock. The M48T512Y/V is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are factory calibrated at 25°C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than +4 ppm at 25°C. The oscillation rate of crystals changes with temperature. The M48T512Y/V design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 10. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, sub- 8/14 tracting counts slows the clock down. The Calibration bits occupy the five lower order bits (D4-D0) in the Control Register 7FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles; that is, +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. M48T512Y, M48T512V Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms tAVAV VALID A0-A18 tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 DATA OUT AI02389 Figure 8. Write Enable Controlled, Write AC Waveforms tAVAV VALID A0-A18 tAVWH tAVEL tWHAX E tWLWH tAVWL W tWHQX tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH AI02386 9/14 M48T512Y, M48T512V Figure 9. Chip Enable Controlled, Write AC Waveforms tAVAV A0-A18 VALID tAVEH tAVEL tELEH tEHAX E tAVWL W tWHDX DQ0-DQ7 DATA INPUT tDVWH AI02387 Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Figure 10 illustrates a TIMEKEEPER calibration waveform. One method for ascertaining how much calibration a given M48T512Y/V may require involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in STMicroelectronics Application Note: TIMEKEEPER CALIBRATION. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration bits. For more information on calibration, see Application Note (TIMEKEEPER CALIBRATION) on the ST Web Site. 10/14 POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION Note: ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V CC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values below V SS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount). M48T512Y, M48T512V Table 11. Register Map Data Address D7 7FFFFh D6 D5 D4 D3 10 Years D0 Year Year 00-99 Month Month 01-12 Date Date 01-31 Day 01-07 Hours Hour 00-23 0 0 7FFFDh 0 0 7FFFCh 0 0 0 7FFFBh 0 0 10 Hours 7FFFAh 0 10 Minutes Minutes Minutes 00-59 7FFF9h ST 10 Seconds Seconds Seconds 00-59 7FFF8h W Keys: 10 M D1 7FFFEh R 0 D2 Function/Range BCD Format 10 Date S 0 0 Day Calibration Control S = SIGN Bit R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to zero Figure 10. Calibration Waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B 11/14 M48T512Y, M48T512V Table 12. Ordering Information Scheme Example: M48T512Y -70 PM 1 Device Type M48T Supply Voltage and Write Protect Voltage 512Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V 512V = VCC = 3.0V to 3.6V; VPFD = 2.7V to 3.0V Speed -70 = 70ns -85 = 85 ns Package PM = PMDIP32 Temperature Range 1 = 0 to 70 °C For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 13. Revision History Date Revision Details June 1998 First Issue 12/03/99 M48T512Y: VPFD (Min) changed Figure 3 changed tFB changed (Figure 5, Table 8) tRB changed (Figure 5, Table 8) 12/14 M48T512Y, M48T512V Table 14. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data mm inches Symb Typ Min Max A 9.27 A1 Typ Min Max 9.52 0.365 0.375 0.38 – 0.015 – B 0.43 0.59 0.017 0.023 C 0.20 0.33 0.008 0.013 D 42.42 43.18 1.670 1.700 E 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 e3 34.29 41.91 1.350 1.650 eA 14.99 16.00 0.590 0.630 L 3.05 3.81 0.120 0.150 S 1.91 2.79 0.075 0.110 N 32 32 Figure 11. PMDIP32 - 32 pin Plastic Module DIP, Package Outline A A1 B S L C eA e1 e3 D N E 1 PMDIP Drawing is not to scale. 13/14 M48T512Y, M48T512V Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 14/14