STMICROELECTRONICS M48Z512AY

M48Z512A
M48Z512AY
4 Mbit (512Kb x8) ZEROPOWER SRAM
■
INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
■
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
■
32
1
10 YEARS of DATA RETENTION in the
ABSENCE of POWER
■
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
PMDIP32 (PM)
Module
SNAPHAT (SH)
Battery
– M48Z512A: 4.50V ≤ VPFD ≤ 4.75V
– M48Z512AY: 4.20V ≤ VPFD ≤ 4.50V
■
BATTERY INTERNALLY ISOLATED UNTIL
POWER IS APPLIED
■
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 512K x 8 SRAMs
■
■
■
SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 28-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY
32
1
TSOP II 32
(10 x 20mm)
SOH28
Surface Mount Chip Set Solution (CS)
Figure 1. Logic Diagram
SNAPHAT HOUSING (BATTERY) IS
REPLACEABLE
VCC
19
Table 1. Signal Names
A0-A18
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
8
A0-A18
W
DQ0-DQ7
M48Z512A
M48Z512AY
E
G
VSS
AI02043
VSS
March 2000
Ground
1/17
M48Z512A, M48Z512AY
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
0 to 70
°C
TSTG
Storage Temperature (V CC Off)
–40 to 70
°C
TBIAS
Temperature Under Bias
–40 to 70
°C
260
°C
TSLD (2)
Lead Solder Temperature for 10 seconds
V IO
Input or Output Voltages
–0.3 to 7
V
VCC
Supply Voltage
–0.3 to 7
V
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
VCC
Mode
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
Write
Read
Read
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
D IN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO
X
X
X
High Z
Battery Back-up Mode
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Figure 2. DIP Connections
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8 M48Z512A 25
9 M48Z512AY 24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
AI02044
2/17
VCC
A15
A17
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
DESCRIPTION
The M48Z512A/512AY ZEROPOWER RAM is a
non-volatile 4,194,304 bit Static RAM organized
as 524,288 words by 8 bits. The device combines
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic 32 pin DIP Module.
For surface mount environments ST provides a
Chip Set solution consisting of a 28 pin 330mil
SOIC NVRAM Supervisor (M40Z300) and a 32 pin
TSOP Type II (10 x 20mm) LPSRAM (M68Z512)
packages.
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel
form. The part number is ”M4Zxx-BR00SH1”.
M48Z512A, M48Z512AY
Figure 3. Block Diagram
VCC
A0-A18
POWER
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
512K x 8
SRAM ARRAY
DQ0-DQ7
E
W
G
INTERNAL
BATTERY
VSS
The M48Z512A/512AY also has its own Power-fail
Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls
below approximately 3V, the control circuitry connects the battery which maintains data until valid
power returns.
The ZEROPOWER RAM replaces industry standard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special write
AI02045
timing or limitations on the number of writes that
can be performed.
The M48Z512A/512AY has its own Power-fail Detect Circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable system operations brought on by low VCC. As VCC
falls below approximately 3V, the control circuitry
connects the battery which sustains data until valid
power returns.
3/17
M48Z512A, M48Z512AY
Figure 4. Hardware Hookup for SMT Chip Set (1)
THS(2)
SNAPHAT
BATTERY(3)
VOUT
VCC
E2
M40Z300
M68Z512
DQ0-DQ7
E
E1CON
E
E2CON
E3CON
E4CON
A0-A18
A
RST
B
W
BL
VSS
VSS
AI03631
Note: 1. For pin connections, see individual data sheets for M40Z300 and M68Z512 at www.st.com.
2. Connect THS pin to VOUT if 4.2V ≤ VPFD ≤ 4.5V (M48Z512AY) or connect THS pin to VSS if 4.5V ≤ VPFD ≤ 4.75V (M48Z512A).
3. SNAPHAT top ordered separately.
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 5. AC Testing Load Circuit
≤ 5ns
5V
0 to 3V
1.5V
1.9kΩ
Note that Output Hi-Z is defined as the point where data is no longer
driven.
DEVICE
UNDER
TEST
OUT
1kΩ
CL includes JIG capacitance
4/17
CL = 100pF or 5pF
AI01030
M48Z512A, M48Z512AY
Table 5. Capacitance (1, 2)
(TA = 25 °C, f = 1MHz)
Symbol
C IN
CIO (3)
Parameter
Test Condit ion
Input Capacitance
Input / Output Capacitance
Min
Max
Unit
VIN = 0V
10
pF
VOUT = 0V
10
pF
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(TA = 0 to 70 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
ILI (1)
Input Leakage Current
ILO (1)
Output Leakage Current
Test Conditio n
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
E = VIL, Outputs open
115
mA
E = VIH
10
mA
E ≥ VCC – 0.2V
5
mA
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
VIL
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
2.4
V
Note: 1. Outputs deselected.
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA = 0 to 70 °C)
Symbol
Parameter
VPFD
Power-fail Deselect Voltage
V SO
Battery Back-up Switchover Voltage
tDR (2)
Data Retention Time
Min
Typ
Max
Unit
M48Z512A
4.5
4.6
4.75
V
M48Z512AY
4.2
4.3
4.5
V
3
10
V
YEARS
Note: 1. All voltages referenced to VSS.
2. At 25 °C.
5/17
M48Z512A, M48Z512AY
Table 8. Power Down/Up AC Characteristics
(TA = 0 to 70 °C)
Symbol
Parameter
Min
Max
Unit
tF (1)
V PFD (max) to VPFD (min) VCC Fall Time
300
µs
tFB (2)
V PFD (min) to VSO VCC Fall Time
10
µs
Write Protect Time from VCC = VPFD
40
tR
V SO to VPFD (max) VCC Rise Time
0
tER
E Recovery Time
40
tWP
µs
150
µs
120
ms
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 6. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tDR
tR
tFB
tER
tWP
E
RECOGNIZED
DON’T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01031
6/17
M48Z512A, M48Z512AY
Table 9. Read Mode AC Characteristics
(TA = 0 to 70 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z512A/M48Z512AY
Symbol
Parameter
-70
Min
tAVAV
Read Cycle Time
-85
Max
70
Min
Unit
Max
85
ns
tAVQV (1)
Address Valid to Output Valid
70
85
ns
tELQV (1)
Chip Enable Low to Output Valid
70
85
ns
tGLQV (1)
Output Enable Low to Output Valid
35
45
ns
tELQX (2)
Chip Enable Low to Output Transition
5
5
ns
tGLQX (2)
Output Enable Low to Output Transition
5
5
ns
tEHQZ (2)
Chip Enable High to Output Hi-Z
30
35
ns
tGHQZ (2)
Output Enable High to Output Hi-Z
20
25
ns
tAXQX (1)
Address Transition to Output Transition
5
5
ns
Note: 1. CL = 100pF.
2. CL = 5pF.
Figure 7. Address Controlled, Read Mode AC Waveforms
A0-A18
tAVAV
tAVQV
DQ0-DQ7
tAXQX
DATA VALID
AI01220
Note:
Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.
7/17
M48Z512A, M48Z512AY
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
VALID
A0-A18
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01221
Note: Write Enable (W) = High.
READ MODE
The M48Z512A/512AY is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable)
is low. The device architecture allows ripplethrough access of data from eight of 4,194,304 locations in the static storage array. Thus, the
unique address specified by the 19 Address Inputs
defines which one of the 524,288 bytes of data is
to be accessed. Valid data will be available at the
Data I/O pins within Address Access time (tAVQV)
after the last address input signal is stable, providing that the E (Chip Enable) and G (Output Enable) access times are also satisfied. If the E and
G access times are not met, valid data will be
8/17
available after the later of Chip Enable Access
time (tELQV) or Output Enable Access Time
(tGLQV). The state of the eight three-state Data I/O
signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven
to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain
low, output data will remain valid for Output Data
Hold time (tAXQX) but will go indeterminate until the
next Address Access.
M48Z512A, M48Z512AY
Table 10. Write Mode AC Characteristics
(TA = 0 to 70 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z512A/M48Z512AY
Symbol
Parameter
-70
Min
-85
Max
Min
Unit
Max
tAVAV
Write Cycle Time
70
85
ns
tAVWL
Address Valid to Write Enable Low
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
ns
tWLWH
Write Enable Pulse Width
55
65
ns
tELEH
Chip Enable Low to Chip Enable High
55
75
ns
tWHAX
Write Enable High to Address Transition
5
5
ns
tEHAX
Chip Enable High to Address Transition
15
15
ns
tDVWH
Input Valid to Write Enable High
30
35
ns
tDVEH
Input Valid to Chip Enable High
30
35
ns
tWHDX
Write Enable High to Input Transition
0
0
ns
tEHDX
Chip Enable High to Input Transition
10
10
ns
tWLQZ (1, 2)
Write Enable Low to Output Hi-Z
25
30
ns
tAVWH
Address Valid to Write Enable High
65
75
ns
tAVEH
Address Valid to Chip Enable High
65
75
ns
Write Enable High to Output Transition
5
5
ns
tWHQX (1, 2)
Note: 1. CL = 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE MODE
The M48Z512A/512AY is in the Write Mode whenever W and E are active. The start of a write is referenced from the latter occurring falling edge of W
or E. A write is terminated by the earlier rising edge
of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for a minimum of tE-
from E or tWHAX from W prior to the initiation
of another read or write cycle. Data-in must be valid t DVEH or tDVWH prior to the end of write and remain valid for tEHDX or tWHDX afterward. G should
be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable
the outputs tWLQZ after W falls.
HAX
9/17
M48Z512A, M48Z512AY
Figure 9. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A18
VALID
tAVWH
tAVEL
tWHAX
E
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01222
Note: Output Enable (G) = High.
Figure 10. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A18
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01223
Note: Output Enable (G) = High.
10/17
M48Z512A, M48Z512AY
Figure 11. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
DATA RETENTION MODE
With valid VCC applied, the M48Z512A/512AY operates as a conventional BYTEWIDE static
RAM. Should the supply voltage decay, the RAM
will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All
outputs become high impedance, and all inputs
are treated as ”don’t care.”
If power fail detection occurs during a valid access, the memory cycle continues to completion. If
the memory cycle fails to terminate within the time
tWP, write protection takes place. When VCC drops
below VSO, the control circuit switches power to
the internal energy source which preserves data.
The internal coin cell will maintain data in the
M48Z512A/512AY after the initial application of
VCC for an accumulated period of at least 10 years
when VCC is less than VSO. As system power returns and VCC rises above VSO , the battery is disconnected, and the power supply is switched to
external VCC. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can
resume.
For more information on Battery Storage Life refer
to the Application Note AN1012.
POWER SUPPLY DECOUPLING
and UNDERSHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure
11) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values
below VSS by as much as one Volt. These negative spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommeded to connect
a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
11/17
M48Z512A, M48Z512AY
Table 11. Ordering Information Scheme
Example:
M48Z512AY
-85
PM
1
Device Type
M48Z
Supply Voltage and Write Protect Voltage
512A = VCC = 4.75V to 5.5V; VPFD = 4.5V to 4.75V
512AY = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V
Speed
-70 = 70ns
-85 = 85ns
Package
PM = PMDIP32
CS (1) = Surface Mount Chip Set solution M40Z300 (SOH28) + M68Z512 (TSOP II 32)
Temperature Range
1 = 0 to 70 °C
9 (2) = Extended Temperature
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT ) which is ordered separately under the part number
”M4Zxx-BR00SH1” in plastic tube or ”M4Zxx-BR00SH1TR” in Tape & Reel form.
2. Contact Sales Offices for availability of Extended Temperature.
Caution: Do not place the SNAPHAT battery package ”M4Zxx-BR00SH1” in conductive foam since this will drain the lithium button-cell
battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
12/17
M48Z512A, M48Z512AY
Table 12. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Mechanical Data
mm
inches
Symbol
Typ
Min
Max
A
Typ
Min
Max
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.95
1.05
0.037
0.041
b
0.30
0.52
0.012
0.020
C
0.12
0.21
0.005
0.008
CP
0.10
D
20.82
21.08
–
–
E
11.56
E1
0.004
0.820
0.830
–
–
11.96
0.455
0.471
10.03
10.29
0.395
0.405
L
0.40
0.60
0.016
0.024
α
0°
5°
0°
5°
N
32
e
1.27
0.050
32
Figure 12. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Outline
D
1
16
E1
E
32
17
b
e
A2
A
C
A1
CP
α
L
TSOP-d
Drawing is not to scale.
13/17
M48Z512A, M48Z512AY
Table 13. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm
inches
Symbol
Typ
Min
Max
A
Typ
Min
3.05
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
28
e
1.27
0.050
28
CP
0.10
0.004
Figure 13. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
1
SOH-A
Drawing is not to scale.
14/17
Max
α
L
M48Z512A, M48Z512AY
Table 14. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Mechanical Data
mm
inches
Symbol
Typ
Min
A
Max
Typ
Min
Max
10.54
0.415
A1
8.00
8.51
0.315
0.335
A2
7.24
8.00
0.285
0.315
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
0.710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
Figure 14. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Outline
A1
eA
A2
A
A3
B
L
eB
D
E
SHZP-A
Drawing is not to scale.
15/17
M48Z512A, M48Z512AY
Table 15. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data
mm
inches
Symbol
Typ
Min
Max
A
9.27
A1
Typ
Min
Max
9.52
0.365
0.375
0.38
–
0.015
–
B
0.43
0.59
0.017
0.023
C
0.20
0.33
0.008
0.013
D
42.42
43.18
1.670
1.700
E
18.03
18.80
0.710
0.740
e1
2.29
2.79
0.090
0.110
e3
34.29
41.91
1.350
1.650
eA
14.99
16.00
0.590
0.630
L
3.05
3.81
0.120
0.150
S
1.91
2.79
0.075
0.110
N
32
32
Figure 15. PMDIP32 - 32 pin Plastic Module DIP, Package Outline
A
A1
S
B
L
C
eA
e1
e3
D
N
E
1
Drawing is not to scale.
16/17
PMDIP
M48Z512A, M48Z512AY
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