M74HC259 8 BIT ADDRESSABLE LATCH ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : tPD = 20 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 259 DESCRIPTION The M74HC259 is an high speed CMOS 8 BIT ADDRESSABLE LATCH fabricated with silicon gate C2MOS technology. The M74HC259 has single data input (D) 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), common enable input (E), and a common CLEAR input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to be entered is held on the A, B, and C inputs. When ENABLE is taken low the data flows through to the addresses output. The data is stored on the positive-going edge of the ENABLE pulse. All unaddressed latches will remain unaffected. With ENABLE in the high state the device is deselected and all DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC259B1R M74HC259M1R T&R M74HC259RM13TR M74HC259TTR latches remain in their previous state, unaffected by changes on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the ENABLE should be held high (inactive) while the address lines are changing. If ENABLE is held high and CLEAR is taken low all eight latches are cleared to the low state. If ENABLE is low all latches except the addressed latch will be cleared. The addressed latch will instead follow the D input, effectively implementing a 3-to-8 line decoder. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/13 M74HC259 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 2, 3 4, 5, 6, 7, 9, 10, 11, 12 13 A, B, C Address Inputs Q0 to Q7 Latch Outputs 14 ENABLE 15 CLEAR 8 16 GND Vcc D NAME AND FUNCTION Data Input Latch Enable Input (Active Low) Conditional Reset Input (Low) Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS FUNCTION ENABLE OUTPUTS OF ADDRESSED LATCH EACH OTHER OUTPUT CLEAR H L D Qi0 ADDRESSABLE LATCH H H Qi0 Qi0 MEMORY L L D L 8 LINE DEMULTIPLEXER L H L L CLEAR ALL BITS TO ’L’ D : The level at the data input Qi0 : The level before the indicated steady state input conditions where established, (i = 0, 1, ......., 7). SELECT INPUTS LATCH ADDRESSED 2/13 C B A L L L Q0 L L H Q1 L H L Q2 L H H Q3 H L L Q4 H L H Q5 H H L Q6 H H H Q7 M74HC259 LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage IIK DC Input Diode Current -0.5 to VCC + 0.5 ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) V ± 50 mA 500(*) mW -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C 3/13 M74HC259 RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Supply Voltage VI Input Voltage VO Output Voltage Top Operating Temperature Input Rise and Fall Time tr, tf Unit 2 to 6 V 0 to VCC V 0 to VCC V -55 to 125 °C VCC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL II ICC 4/13 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 1.5 3.15 4.2 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 Max. 1.5 3.15 4.2 0.5 1.35 1.8 V 0.5 1.35 1.8 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10 5.68 Unit V V 6.0 IO=-5.2 mA 2.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=20 µA 0.0 0.1 0.1 0.1 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=4.0 mA 0.17 0.26 0.33 0.40 6.0 IO=5.2 mA 0.18 0.26 0.33 0.40 6.0 VI = VCC or GND ± 0.1 ±1 ±1 µA 6.0 VI = VCC or GND 4 40 80 µA 5.8 5.63 5.60 V M74HC259 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (DATA - Q) tPLH tPHL Propagation Delay Time (A, B, C - Q) tPLH tPHL Propagation Delay Time (G - Q) tPLH tPHL Propagation Delay Time (CLEAR - Q) tW(L) tW(L) ts ts th th Minimum Pulse Width (ENABLE) Minimum Pulse Width (CLEAR) Minimum Set-up Time (DATA) Minimum Set-up Time (A, B, C) Minimum Hold Time (DATA) Minimum Hold Time (A, B, C) Value TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 30 8 7 56 18 15 76 24 20 57 19 16 45 15 13 28 7 6 24 6 5 12 3 3 75 15 13 140 28 24 190 38 32 150 30 26 115 23 20 75 15 13 75 15 13 50 10 9 25 5 5 5 5 5 0 0 0 -40 to 85°C -55 to 125°C Min. Min. Max. 95 19 16 175 35 30 240 48 41 190 38 32 145 29 25 90 19 16 90 19 16 60 12 11 30 6 5 5 5 5 0 0 0 Unit Max. 110 22 19 210 42 36 285 57 48 225 45 38 175 35 30 115 23 20 115 23 20 75 15 13 40 8 7 5 5 5 0 0 0 ns ns ns ns ns ns ns ns ns ns ns CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) Value TA = 25°C Min. Typ. Max. 10 CIN Input Capacitance 5.0 5 CPD Power Dissipation Capacitance (note 1) 5.0 66 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC 5/13 M74HC259 TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 6/13 M74HC259 WAVEFORM 2 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) WAVEFORM 3 : MINIMUM PULSE WIDTH (G), SETUP AND HOLD TIME (D TO G)(f=1MHz; 50% duty cycle) 7/13 M74HC259 WAVEFORM 4 : MINIMUM PULSE WIDTH (CLR) (f=1MHz; 50% duty cycle) WAVEFORM 5 : SETUP AND HOLD TIME (f=1MHz; 50% duty cycle) 8/13 M74HC259 WAVEFORM 6 : INPUT WAVEFORMS (f=1MHz; 50% duty cycle) 9/13 M74HC259 Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 10/13 M74HC259 SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8° (max.) PO13H 11/13 M74HC259 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.60 0.0256 BSC 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 12/13 M74HC259 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 13/13