AMD MACH211SP-12JC

FINAL
COM’L: -7.5/10/12/15/20
IND: -10/12/14/18/24
MACH211SP-7/10/12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
■ JTAG-Compatible, 5-V in-system programming
■ 44 Pins
■ 64 Macrocells
■ Peripheral Component Interconnect (PCI)
compliant (-7/-10)
■ Programmable power-down mode
■ 7.5 ns tPD Commercial
10 ns tPD Industrial
■ 133 MHz fCNT
■ 34 Bus-Friendly™ Inputs and I/Os
■
■
■
■
32 Outputs
64 Flip-flops; 2 clock choices
4 “PAL26V16” blocks with buried macrocells
Improved routing over the MACH210
IN-SYSTEM PROGRAMMING
In-system programming allows the MACH211SP to be
programmed while soldered onto a system board. Programming the MACH211SP in-system yields numerous benefits at all stages of development: prototyping,
manufacturing, and in the field. Since insertion into a
programmer isn’t needed, multiple handling steps and
the resulting bent leads are eliminated. The design can
be modified in-system for design changes and debugging while prototyping, programming boards in production, and field upgrades.
The MACH211SP offers advantages not available in
other CPLD architectures with in-system programming.
MACH devices have extensive routing resources for
pin-out retention; design changes resulting in pin-out
changes for other CPLDs cancel the advantages of
in-system programming. The MACH211SP can be employed in any JTAG (IEEE 1149.1) compliant chain.
GENERAL DESCRIPTION
The MACH211SP is a member of AMD’s EE CMOS
Performance Plus MACH 2 device family. This device
has approximately six times the logic macrocell capability of the popular PAL22V10 without loss of speed.
The MACH211SP consists of four PAL blocks interconnected by a programmable switch matrix. The four
PAL blocks are essentially “PAL26V16” structures complete with product-term arrays and programmable
macrocells, which can be programmed as high speed
or low power, and buried macrocells. The switch matrix
connects the PAL blocks to each other and to all input
pins, providing a high degree of connectivity between
the fully-connected PAL blocks. This allows designs to
be placed and routed efficiently.
The MACH211SP has two kinds of macrocell: output
and buried. The MACH211SP output macrocell provides registered, latched, or combinatorial outputs with
programmable polarity. If a registered configuration is
chosen, the register can be configured as D-type or
T-type to help reduce the number of product terms. The
register type decision can be made by the designer or
by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired,
the internal feedback path from the macrocell can be
used, which frees up the I/O pin for use as an input.
The MACH211SP has dedicated buried macrocells
which, in addition to the capabilities of the output
macrocell, also provide input registers or latches for
use in synchronizing signals and reducing setup time
requirements.
The MACH211SP is an enhanced version of the
MACH211, adding the JTAG-compatible in-system programming feature.
Publication# 20405 Rev: B Amendment/0
Issue Date: February 1996
BLOCK DIAGRAM
I/O0–I/O7
I/O8–I/O15
8
I/O Cells
8
I/O Cells
8
8
8
Macrocells
Macrocells
8
8
8
OE
52 x 68
AND Logic Array
and
Logic Allocator
2
Macrocells
Macrocells
OE
52 x 68
AND Logic Array
and
Logic Allocator
26
26
Switch Matrix
26
26
52 x 68
AND Logic Array
and
Logic Allocator
OE
Macrocells
8
8
I/O Cells
Macrocells
8
52 x 68
AND Logic Array
and
Logic Allocator
OE
Macrocells
8
8
Macrocells
8
2
2
I/O Cells
8
8
I/O24–I/O31
I/O16–I/O23
CLK0/I0
CLK1/I1
20405B-1
2
MACH211SP-7/10/12/15/20
CONNECTION DIAGRAM MACH211SP
Top View
3 2
I/O28
I/O29
I/O30
I/O31
VCC
GND
5 4
I/O0
6
I/O1
I/O3
I/O2
I/O4
44-Pin PLCC
1 44 43 42 41 40
I/O5
7
39
I/O27
I/O6
8
38
I/O26
I/O7
9
37
I/O25
TDI
10
36
I/O24
CLK0/I0
11
35
TDO
GND
12
34
GND
TCK
13
33
CLK1/I1
I/O8
14
32
TMS
I/O9
15
31
I/O23
I/O10
16
30
I/O22
I/O11
17
29
I/O21
I/O20
I/O19
I/O18
I/O17
I/O16
VCC
GND
I/O15
I/O14
I/O13
I/O12
18 19 20 21 22 23 24 25 26 27 28
20405B-2
PIN DESIGNATIONS
CLK/I = Clock or Input
TDI
= Test Data In
GND = Ground
TCK = Test Clock
I
= Input
TMS = Test Mode Select
I/O
= Input/Output
TDO = Test Data Out
VCC = Supply Voltage
MACH211SP-7/10/12/15/20
3
CONNECTION DIAGRAM MACH211SP
Top View
44
43
42
41
40
39
38
37
36
35
34
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
44-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
I/O27
I/O26
I/O25
I/O24
TDO
GND
CLK1/I1
TMS
I/O23
I/O22
I/O21
I/O12
I/O13
I/O14
I/O15
VCC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
12
13
14
15
16
17
18
19
20
21
22
I/O5
I/O6
I/O7
TDI
CLK0/I0
GND
TCK
I/O8
I/O9
I/O10
I/O11
20405B-3
PIN DESIGNATIONS
CLK/I = Clock or Input
TDI
GND = Ground
TCK = Test Clock
I
= Input
TMS = Test Mode Select
I/O
= Input/Output
TDO = Test Data Out
VCC
= Supply Voltage
4
= Test Data In
MACH211SP-7/10/12/15/20
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
MACH
211
SP
-7
J
C
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING
Blank = Standard Processing
DEVICE NUMBER
211 = 64 Macrocells, 44 Pins,
Power-Down mode,
Bus-Friendly Inputs and I/Os
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
V = 44-Pin Thin Quad Flat Pack
(PQT044)
PRODUCT DESIGNATION
SP = In-system Programmable
SPEED
-7 = 7.5 ns tPD
-10 = 10 ns tPD
-12 = 12 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
Valid Combinations
Valid Combinations
The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local AMD
sales office to confirm availability of specific valid combinations and to check on newly released combinations.
MACH211SP-7
MACH211SP-10
MACH211SP-12
JC, VC
MACH211SP-15
MACH211SP-20
MACH211SP-7/10/12/15/20 (Com’l)
5
ORDERING INFORMATION
Industrial Products
AMD programmable logic products for industrial applications are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:
MACH
211
SP
-10
J
I
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING
Blank = Standard Processing
DEVICE NUMBER
211 = 64 Macrocells, 44 Pins,
Power-Down mode,
Bus-Friendly Inputs and I/Os
OPERATING CONDITIONS
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
PRODUCT DESIGNATION
SP = In-system Programmable
SPEED
-10 = 10 ns tPD
-12 = 12 ns tPD
-14 = 14.5 ns tPD
-18 = 18 ns tPD
-24 = 24 ns tPD
Valid Combinations
Valid Combinations
The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local AMD
sales office to confirm availability of specific valid combinations and to check on newly released combinations.
MACH211SP-10
MACH211SP-12
MACH211SP-14
JI
MACH211SP-18
MACH211SP-24
6
MACH211SP-10/12/14/18/24 (Ind)
FUNCTIONAL DESCRIPTION
Table 1.
The MACH211SP consists of four PAL blocks connected by a switch matrix. There are 32 I/O pins feeding
the switch matrix. These signals are distributed to the
four PAL blocks for efficient design implementation.
There are two clock pins that can also be used as dedicated inputs.
Macrocell
Output
Buried
M0
Each PAL block in the MACH211SP (Figure 1) contains
a 64-product-term logic array, a logic allocator, 8 output
macrocells, 8 buried macrocells, and 8 I/O cells. The
switch matrix feeds each PAL block with 26 inputs. This
makes the PAL block look effectively like an independent “PAL26V16” with 8 buried macrocells.
In addition to the logic product terms, two output enable
product terms, an asynchronous reset product term,
and an asynchronous preset product term are provided. One of the two output enable product terms can
be chosen within each I/O cell in the PAL block. All
flip-flops within the PAL block are initialized together.
The Switch Matrix
M1
The Product-term Array
The MACH211SP product-term array consists of 64
product terms for logic use, and 4 special-purpose
product terms. Two of the special-purpose product
terms provide programmable output enable; one provides asynchronous reset, and one provides asynchronous preset.
The Logic Allocator
The logic allocator in the MACH211SP takes the 64
logic product terms and allocates them to the 16
macrocells as needed. Each macrocell can be driven
by up to 16 product terms. The design software automatically configures the logic allocator when fitting the
design into the device.
Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
The Macrocell
The MACH211SP has two types of macrocell: output
and buried. The output macrocells can be configured
as either registered, latched, or combinatorial, with programmable polarity. The macrocell provides internal
C0, C1, C2, C3
C1, C2, C3, C4
M3
M4
C2, C3, C4, C5
C3, C4, C5, C6
M5
M6
C4, C5, C6, C7
C5, C6, C7, C8
M7
M8
C6, C7, C8, C9
C7, C8, C9, C10
M9
M10
C8, C9, C10, C11
C9, C10, C11, C12
M11
M12
The MACH211SP switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 8 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that
also provides for high performance. The design software automatically configures the switch matrix when
fitting a design into the device.
Available Clusters
C0, C1, C2
M2
The PAL Blocks
Logic Allocation
C10, C11, C12, C13
C11, C12, C13, C14
M13
M14
C12, C13, C14, C15
C13, C14, C15
M15
C14, C15
feedback whether configured with or without the
flip-flop. The registers can be configured as D-type or
T-type, allowing for product-term optimization.
The flip-flops can individually select one of two clock/
gate pins, which are also available as data inputs. The
registers are clocked on the LOW-to-HIGH transition of
the clock signal. The latch holds its data when the gate
input is HIGH, and is transparent when the gate input
is LOW. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms.
The buried macrocells are the same as the output
macrocells if they are used for generating logic. In that
case, the only thing that distinguishes them from the
output macrocells is the fact that there is no I/O cell
connection, and the signal is only used internally. The
buried macrocell can also be configured as an input
register or latch.
The I/O Cell
The I/O cell in the MACH211SP consists of a
three-state output buffer. The three-state buffer can be
configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms
may be used to provide the control. The two product
terms that are available are common to all I/O cells in a
PAL block.
MACH211SP-7/10/12/15/20
7
These choices make it possible to use the macrocell as
an output, an input, a bidirectional pin, or a three-state
output for use in driving a bus.
Power-Down Mode
The MACH211SP features a programmable low-power
mode in which individual signal paths can be programmed as low power. These low-power speed paths
will be slightly slower than the non-low-power paths.
This feature allows speed critical paths to run at maximum frequency while the rest of the paths operate in
the low-power mode, resulting in power savings of up
to 75%. If all signals in a PAL block are low-power, then
total power is reduced further.
In-System Programming
Programming is the process where MACH devices are
loaded with a pattern defined in a JEDEC file obtained
from MACHXL software or third-party software. Programming is accomplished through four JTAG pins:
Test Mode Select (TMS), Test Clock (TCK), Test Data
In (TDI), and Test Data Out (TDO). The MACH211SP
can be employed in any JTAG (IEEE 1149.1) compliant chain. While the MACH211SP is fully JTAG compatible, it supports the BYPASS instruction, not the
EXTEST and SAMPLE/PRELOAD instructions. The
MACH211SP can be programmed across the commercial temperature range. Programming the MACH device after it has been placed on a circuit board is easily
accomplished. Programming is initiated by placing the
device into programming mode, using the MACHPRO
programming software provided by AMD. The device is
bulk erased and the JEDEC file is then loaded. After
the data is transferred into the device, the PROGRAM
instruction is loaded. Further programming details can
be found in application note, “Advanced In-circuit
Programming Guidelines.”
should be programmed. The configuration file is discussed in detail in the MACHPRO software manual.
The MACH211SP devices tristate the outputs during
programming. They have one security bit which inhibits
program and verify. This allows the user to protect proprietary patterns and designs.
Program verification of a MACH device involves reading back the programmed pattern and comparing it with
the original JEDEC file. The AMD method of program
verification performed on the MACH devices permits
the verification of one device at a time.
Accidental Programming or Erasure
Protection
It is virtually impossible to program or erase a MACH
device inadvertently. The following conditions must be
met before programming actually takes place:
■ The device must be in the password-protected
program mode
■ The programming or bulk erase instruction must be
in the instruction register
If the above conditions are not met, the programming
circuitry cannot be activated.
To ensure that the AMD ten year device data retention
guarantee applies, 100 program/erase cycle limit
should not be exceeded.
Bus-Friendly Inputs and I/Os
The MACH211SP inputs and I/Os include two inverters
in series which loop back to the input. This double
inversion reinforces the state of the input and pulls the
voltage away from the input threshold voltage. For an
illustration of this configuration, please turn to the
Input/Output Equivalent Schematics section.
On-Board Programming Options
PCI Compliance
Since the MACHPRO software performs these steps
automatically, the following programming options are
published for reference.
The MACH211SP-7/10 is fully compliant with the PCI
Local Bus Specification published by the PCI Special
Interest Group. The MACH211SP-7/10’s predictable
timing ensures compliance with the PCI AC specifications independent of the design. On the other hand, in
CPLD and FPGA architectures without predictable timing, PCI compliance is dependent upon routing and
product term distribution.
The configuration file, which is also known as the chain
file, defines the MACH device JTAG chain. The file contains the information concerning which JEDEC file is to
be placed into which device, the state which the outputs should be placed, and whether the security fuses
8
MACH211SP-7/10/12/15/20
0
4
8
12
16
20
24
28
32
36
40
43
47
51
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
Output
Macro
Cell
M0
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
I/O
Cell
I/O
Buried
Macro
Cell
M1
Output
Macro
Cell
M2
Buried
Macro
Cell
M3
0
C0
I/O
Cell
Output
Macro
Cell
M4
C1
C2
Buried
Macro
Cell
M5
C3
C5
C6
Switch
Matrix
C7
C8
Logic Allocator
C4
C9
Output
Macro
Cell
M6
Buried
Macro
Cell
M7
Output
Macro
Cell
M8
C10
C11
Buried
Macro
Cell
M9
C12
C13
Output
Macro
Cell
M10
C14
C15
63
Buried
Macro
Cell
M11
Output
Macro
Cell
M12
Buried
Macro
Cell
M13
M15
Buried
Macro
Cell
CLK
M14
Output
Macro
Cell
2
0
4
8
12
16
20
24
28
32
36
40
43
47
51
16
8
20405B-4
Figure 1.
MACH211SP PAL Block
MACH211SP-7/10/12/15/20
9
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . .0°C to +70°C
Supply Voltage with
Respect to Ground. . . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . .–0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . .–0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to 70°C) . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
2.4
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL
VOL
Output LOW Voltage
IOL = 16 mA, VCC = Min, VIN = VIH or VIL
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Current
VIN = 0 V, VCC = Max (Note 2)
–10
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Notes 3, 5)
–160
mA
Supply Current (Static)
VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4)
40
mA
Supply Current (Active)
VCC = 5 V, TA = 25°C, f = 1 MHz (Note 4)
45
mA
ICC
V
0.5
2.0
V
V
–30
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each
PAL block and is capable of being loaded, enabled and reset.
5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
10
MACH211SP-7/10 (Com’l)
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Typ
Unit
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
6
pF
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
-7
Parameter
Symbol
Parameter Description
tPD
Input, I/O, or Feedback to Combinatorial Output (Note 3)
tS
Setup Time from Input, I/O, or Feedback to Clock
(Note 3)
tH
Register Data Hold Time
tCO
Clock to Output (Note 3)
tWL
Max
Min
7.5
Max
Unit
10
ns
D-type
5.5
6.5
ns
T-type
6.5
7.5
ns
0
0
ns
4.5
6
ns
LOW
3
5
ns
HIGH
3
5
ns
D-type
100
80
MHz
T-type
91
74
MHz
D-type
133
100
MHz
T-type
125
91
MHz
166.7
100
MHz
5.5
6.5
ns
0
0
ns
Clock Width
tWH
External Feedback
fMAX
Min
-10
Maximum
Frequency
(Note 1)
1/(tS + tCO)
Internal Feedback (fCNT)
1/(tWL + tWH)
No Feedback
tSL
Setup Time from Input, I/O, or Feedback to Gate
tHL
Latch Data Hold Time
tGO
Gate to Output
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through Transparent Input or
Output Latch
tSIR
Input Register Setup Time
2
2
ns
tHIR
Input Register Hold Time
2
2
ns
tICO
Input Register Clock to Combinatorial Output
tICS
Input Register Clock to Output Register Setup
tWICL
7
3
5
9.5
ns
12
11
ns
13
ns
ns
D-type
9
10
ns
T-type
10
11
ns
LOW
3
5
ns
HIGH
3
5
ns
166.7
100
MHz
Input Register Clock Width
tWICH
fMAXIR
7
Maximum Input Register Frequency
tSIL
Input Latch Setup Time
2
2
ns
tHIL
Input Latch Hold Time
2
2
ns
tIGO
Input Latch Gate to Combinatorial Output
12
14
ns
tIGOL
Input Latch Gate to Output Through Transparent Output Latch
14
16
ns
tSLL
Setup Time from Input, I/O, or Feedback Through Transparent Input
Latch to Output Latch Gate
MACH211SP-7/10 (Com’l)
7.5
8.5
ns
11
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
Parameter
Symbol
tIGS
-7
Parameter Description
Min
-10
Max
Min
Max
Unit
Input Latch Gate to Output Latch Setup
10
11
ns
tWIGL
Input Latch Gate Width LOW
3
5
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent Input and
Output Latches
tAR
Asynchronous Reset to Registered or Latched Output
12.5
14
ns
9.5
15
ns
tARW
Asynchronous Reset Width (Note 1)
5
10
ns
tARR
Asynchronous Reset Recovery Time (Note 1)
5
10
ns
tAP
Asynchronous Preset to Registered or Latched Output
9.5
15
ns
tAPW
Asynchronous Preset Width (Note 1)
5
10
ns
tAPR
Asynchronous Preset Recovery Time (Note 1)
5
10
ns
tEA
Input, I/O, or Feedback to Output Enable (Note 1)
9.5
12
ns
tER
Input, I/O, or Feedback to Output Disable (Note 1)
9.5
12
ns
tLP
tPD Increase for Powered-down Macrocell (Note 3)
10
10
ns
tLPS
tS Increase for Powered-down Macrocell (Note 3)
10
10
ns
tLPCO
tCO Increase for Powered-down Macrocell (Note 3)
0
0
ns
tLPEA
tEA Increase for Powered-down Macrocell (Note 3)
10
10
ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
2. See Switching Test Circuit for test conditions.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
12
MACH211SP-7/10 (Com’l)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . .0°C to +70°C
Supply Voltage with
Respect to Ground. . . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . .–0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . .–0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to 70°C) . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
2.4
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL
VOL
Output LOW Voltage
IOL = 16 mA, VCC = Min, VIN = VIH or VIL
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Current
VIN = 0 V, VCC = Max (Note 2)
–10
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Notes 3, 5)
–160
mA
Supply Current (Static)
VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4)
40
mA
Supply Current (Active)
VCC = 5 V, TA = 25°C, f = 1 MHz (Note 4)
45
mA
ICC
V
0.5
2.0
V
V
–30
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each
PAL block and is capable of being loaded, enabled and reset.
5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
MACH211SP-12/15/20 (Com’l)
13
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Typ
Unit
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
6
pF
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
-12
Parameter
Symbol
Parameter Description
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 3)
tS
Setup Time from Input, I/O, or
Feedback to Clock
tH
Register Data Hold Time
tCO
Clock to Output (Note 3)
tWL
Min
12
-20
Max
Min
15
Max
Unit
20
ns
D-type
7
10
13
ns
T-type
8
11
14
ns
0
0
0
ns
10
12
ns
LOW
6
6
8
ns
HIGH
6
6
8
ns
D-type
66.7
50
40
MHz
T-type
62.5
47.6
38.5
MHz
D-type
83.3
66.6
50
MHz
T-type
76.9
62.5
47.6
MHz
83.3
83.3
62.5
MHz
Clock Width
External
Feedback
Maximum
Frequency
(Note 1)
1/(tS + tCO)
Internal Feedback (fCNT)
No
Feedback
1/(tWL + tWH)
tSL
Setup Time from Input, I/O, or Feedback to Gate
7
10
13
ns
tHL
Latch Data Hold Time
0
0
0
ns
tGO
Gate to Output
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
tSIR
Input Register Setup Time
2
2
2
ns
tHIR
Input Register Hold Time
2
2.5
3
ns
tICO
Input Register Clock to Combinatorial Output
tICS
Input Register Clock to Output Register D-type
Setup
T-type
tWICL
10
6
11
6
14
12
8
17
15
ns
22
18
ns
23
ns
ns
12
15
20
ns
13
16
21
ns
LOW
6
6
8
ns
HIGH
6
6
8
ns
83.3
83.3
62.5
MHz
Input Register Clock Width
tWICH
14
Max
8
tWH
fMAX
Min
-15
fMAXIR
Maximum Input Register
Frequency
tSIL
Input Latch Setup Time
2
2
2
ns
tHIL
Input Latch Hold Time
2
2.5
3
ns
1/(tWICL + tWICH)
MACH211SP-12/15/20 (Com’l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
Parameter
Symbol
-12
Parameter Description
Min
-15
Max
Min
-20
Max
Min
Max
Unit
tIGO
Input Latch Gate to Combinatorial Output
17
20
25
ns
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
19
22
27
ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
9
12
15
ns
tIGS
Input Latch Gate to Output Latch Setup
13
16
21
ns
tWIGL
Input Latch Gate Width LOW
6
6
8
ns
tPDLL
Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches
16
19
24
ns
Asynchronous Reset to Registered or Latched
Output
16
20
25
ns
tAR
tARW
Asynchronous Reset Width (Note 1)
12
15
20
ns
tARR
Asynchronous Reset Recovery Time (Note 1)
8
10
15
ns
tAP
Asynchronous Preset to Registered or Latched
Output
16
20
25
ns
tAPW
Asynchronous Preset Width (Note 1)
12
15
20
ns
tAPR
Asynchronous Preset Recovery Time (Note 1)
8
10
15
ns
tEA
Input, I/O, or Feedback to Output Enable (Note 1)
15
15
15
ns
tER
Input, I/O, or Feedback to Output Disable
(Note 1)
15
15
15
ns
tLP
tPD Increase for Powered-down Macrocell
(Note 3)
10
10
10
ns
tLPS
tS Increase for Powered-down Macrocell (Note 3)
10
10
10
ns
tLPCO
tCO Increase for Powered-down Macrocell
(Note 3)
0
0
0
ns
tLPEA
tEA Increase for Powered-down Macrocell
(Note 3)
10
10
10
ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
2. See Switching Test Circuit for test conditions.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
MACH211SP-12/15/20 (Com’l)
15
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Industrial (I) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . .–40°C to +85°C
Supply Voltage with
Respect to Ground. . . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
DC Input Voltage . . . . . . . . . . . .–0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . .–0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = –40°C to +85°C). . . . . 200 mA
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
2.4
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL
VOL
Output LOW Voltage
IOL = 16 mA, VCC = Min, VIN = VIH or VIL
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 2)
–10
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Notes 3, 5)
–160
mA
Supply Current (Static)
VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4)
40
mA
Supply Current (Active)
VCC = 5 V, TA = 25°C, f = 1 MHz (Note 4)
45
mA
ICC
V
0.5
2.0
V
V
–30
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each
PAL block and is capable of being loaded, enabled and reset.
5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
16
MACH211SP-10/12 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Typ
Unit
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
6
pF
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
-10
Parameter
Symbol
Parameter Description
tPD
Input, I/O, or Feedback to Combinatorial Output (Note 3)
tS
Setup Time from Input, I/O, or Feedback to Clock
tH
Register Data Hold Time
tCO
Clock to Output (Note 3)
tWL
Max
Min
10
Max
Unit
12
ns
D-type
6.5
8
ns
T-type
7.5
9
ns
0
0
ns
6
7.5
ns
LOW
5
6
ns
HIGH
5
6
ns
D-type
80
64
MHz
T-type
74
59
MHz
D-type
100
80
MHz
T-type
91
72.5
MHz
100
80
MHz
6.5
8
ns
0
0
ns
Clock Width
tWH
External Feedback
fMAX
Min
-12
Maximum
Frequency
(Note 1)
1/(tS + tCO)
Internal Feedback (fCNT)
No Feedback
1/(tWL + tWH)
tSL
Setup Time from Input, I/O, or Feedback to Gate
tHL
Latch Data Hold Time
tGO
Gate to Output
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through Transparent Input or
Output Latch
tSIR
Input Register Setup Time
2
2.5
ns
tHIR
Input Register Hold Time
2
3
ns
tICO
Input Register Clock to Combinatorial Output
tICS
Input Register Clock to Output Register Setup
tWICL
8
5
6
12
ns
14.5
13
ns
16
ns
ns
D-type
10
12
ns
T-type
11
13
ns
LOW
5
6
ns
HIGH
5
6
ns
100
80
MHz
Input Register Clock Width
tWICH
fMAXIR
8.5
Maximum Input Register Frequency
1/(tWICL + tWICH)
tSIL
Input Latch Setup Time
2
2.5
ns
tHIL
Input Latch Hold Time
2
3
ns
tIGO
Input Latch Gate to Combinatorial Output
14
17
ns
tIGOL
Input Latch Gate to Output Through Transparent Output Latch
16
19.5
ns
MACH211SP-10/12 (Ind)
17
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued)
-10
-12
Parameter
Symbol
Parameter Description
Min
tSLL
Setup Time from Input, I/O, or Feedback Through Transparent Input
Latch to Output Latch Gate
8.5
10.5
ns
tIGS
Input Latch Gate to Output Latch Setup
11
13.5
ns
tWIGL
Input Latch Gate Width LOW
5
6
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent Input and
Output Latches
14
17
ns
Asynchronous Reset to Registered or Latched Output
15
19.5
ns
tAR
Max
Min
Max
Unit
tARW
Asynchronous Reset Width (Note 1)
10
12
ns
tARR
Asynchronous Reset Recovery Time (Note 1)
10
10
ns
tAP
Asynchronous Preset to Registered or Latched Output
15
18
ns
tAPW
Asynchronous Preset Width (Note 1)
10
12
ns
tAPR
Asynchronous Preset Recovery Time (Note 1)
10
10
ns
tEA
Input, I/O, or Feedback to Output Enable (Note 1)
15
15
ns
tER
Input, I/O, or Feedback to Output Disable (Note 1)
15
15
ns
tLP
tPD Increase for Powered-down Macrocell (Note 3)
10
10
ns
tLPS
tS Increase for Powered-down Macrocell (Note 3)
10
10
ns
tLPCO
tCO Increase for Powered-down Macrocell (Note 3)
0
0
ns
tLPEA
tEA Increase for Powered-down Macrocell (Note 3)
10
10
ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit for test conditions.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
18
MACH211SP-10/12 (Ind)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Industrial (I) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . .–40°C to +85°C
Supply Voltage with
Respect to Ground. . . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
DC Input Voltage . . . . . . . . . . . .–0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . .–0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = –40°C to 85°C) . . . . . . 200 mA
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
2.4
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL
VOL
Output LOW Voltage
IOL = 16 mA, VCC = Min, VIN = VIH or VIL
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 2)
–10
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Notes 3, 5)
–160
mA
Supply Current (Static)
VCC = 5 V, TA = 25°C, f = 0 MHz (Note 4)
40
mA
Supply Current (Active)
VCC = 5 V, TA = 25°C, f = 1 MHz (Note 4)
45
mA
ICC
V
0.5
2.0
V
V
–30
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each
PAL block and is capable of being loaded, enabled and reset.
5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
MACH211SP-14/18/24 (Ind)
19
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Typ
Unit
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
6
pF
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
-14
Parameter
Symbol
Parameter Description
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 3)
tS
Setup Time from Input, I/O, or
Feedback to Clock
tH
Register Data Hold Time
tCO
Clock to Output (Note 3)
tWL
Min
14.5
-24
Max
Min
18
Max
Unit
24
ns
D-type
8.5
12
16
ns
T-type
10
13.5
17
ns
0
0
0
ns
12
14.5
ns
LOW
7.5
7.5
10
ns
HIGH
7.5
7.5
10
ns
D-type
53
40
32
MHz
T-type
50
38
30.5
MHz
D-type
61.5
53
38
MHz
T-type
57
44
34.5
MHz
66.5
66.5
50
MHz
8.5
12
16
ns
0
0
0
ns
Clock Width
External
Feedback
Maximum
Frequency
(Note 1)
1/(tS + tCO)
Internal Feedback (fCNT)
No
Feedback
1/(tWL + tWH)
tSL
Setup Time from Input, I/O, or Feedback to Gate
tHL
Latch Data Hold Time
tGO
Gate to Output
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
tSIR
Input Register Setup Time
2.5
2.5
2.5
ns
tHIR
Input Register Hold Time
3
3.5
4
ns
tICO
Input Register Clock to Combinatorial Output
tICS
Input Register Clock to Output Register D-type
Setup
T-type
tWICL
12
7.5
13.5
7.5
17
14.5
10
20.5
18
ns
26.5
22
ns
28
ns
ns
14.5
18
24
ns
16
19.5
25.5
ns
LOW
7.5
7.5
10
ns
HIGH
7.5
7.5
10
ns
66.5
66.5
50
MHz
Input Register Clock Width
tWICH
20
Max
10
tWH
fMAX
Min
-18
fMAXIR
Maximum Input Register
Frequency
tSIL
Input Latch Setup Time
2.5
2.5
2.5
ns
tHIL
Input Latch Hold Time
3
3.5
4
ns
tIGO
Input Latch Gate to Combinatorial Output
1/(tWICL + tWICH)
20.5
MACH211SP-14/18/24 (Ind)
24
30
ns
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued)
-14
-18
-24
Parameter
Symbol
Parameter Description
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
11
14.5
18
ns
tIGS
Input Latch Gate to Output Latch Setup
16
19.5
25.5
ns
tWIGL
Input Latch Gate Width LOW
7.5
7.5
10
ns
tPDLL
Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches
19.5
23
29
ns
Asynchronous Reset to Registered or Latched
Output
19.5
24
30
ns
tAR
tARW
Asynchronous Reset Width (Note 1)
tARR
Asynchronous Reset Recovery Time (Note 1)
tAP
Min
Max
Min
23
Max
Min
26.5
Max
Unit
32.5
ns
14.5
18
24
ns
10
12
18
ns
Asynchronous Preset to Registered or Latched
Output
19.5
24
30
ns
tAPW
Asynchronous Preset Width (Note 1)
tAPR
Asynchronous Preset Recovery Time (Note 1)
tEA
Input, I/O, or Feedback to Output Enable (Note 1)
14.5
18
24
ns
tER
Input, I/O, or Feedback to Output Disable
(Note 1)
14.5
18
24
ns
tLP
tPD Increase for Powered-down Macrocell
(Note 3)
10
10
10
ns
tLPS
tS Increase for Powered-down Macrocell (Note 3)
10
10
10
ns
tLPCO
tCO Increase for Powered-down Macrocell
(Note 3)
0
0
0
ns
tLPEA
tEA Increase for Powered-down Macrocell
(Note 3)
10
10
10
ns
14.5
18
24
ns
10
12
18
ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit for test conditions.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
MACH211SP-14/18/24 (Ind)
21
TYPICAL ICC CHARACTERISTICS
VCC = 5 V, TA = 25°C
200
High Speed
150
ICC (mA)
100
Low Power
50
0
0
10
20
30
40
50
60
70
80
90
Frequency (MHz)
20405B-5
The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.
Maximum frequency shown uses internal feedback and a D-type register.
22
MACH211SP-7/10/12/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Typ
Parameter
Symbol
Parameter Description
θjc
Thermal impedance, junction to case
θja
Thermal impedance, junction to ambient
θjma
Thermal impedance, junction to ambient
with air flow
TQFP
PLCC
Unit
11.3
4
°C/W
41
30.4
°C/W
200 lfpm air
35
18.5
°C/W
400 lfpm air
33.7
15.9
°C/W
600 lfpm air
32.6
13.5
°C/W
800 lfpm air
32
12.8
°C/W
Plastic θjc Considerations
The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of
the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at
a constant temperature. Therefore, the measurements can only be used in a similar environment. TQFP thermal measurements
are taken with components on a six-layer printed circuit board.
MACH211SP-7/10/12/15/20
23
SWITCHING WAVEFORMS
Input, I/O, or
Feedback
VT
tPD
Combinatorial
Output
VT
20405B-6
Combinatorial Output
Input, I/O, or
Feedback
Input, I/O, or
Feedback
VT
tS
VT
tH
tSL
Gate
VT
Clock
tHL
tCO
Registered
Output
VT
tPDL
VT
tGO
Latched
Out
VT
20405B-7
20405B-8
Registered Output
Latched Output
tWH
Gate
Clock
VT
tGWL
tWL
20405B-9
20405B-10
Clock Width
Gate Width
Registered
Input
Registered
Input
VT
tSIR
Input
Register
Clock
tHIR
Input
Register
Clock
VT
tICO
Combinatorial
Output
VT
Output
Register
Clock
20405B-11
Registered Input
VT
tICS
VT
20405B-12
Input Register to Output Register Setup
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
24
VT
MACH211SP-7/10/12/15/20
SWITCHING WAVEFORMS
Latched
In
VT
tSIL
tHIL
VT
Gate
tIGO
Combinatorial
Output
VT
20405B-13
Latched Input
tPDLL
Latched
In
VT
Latched
Out
Input
Latch Gate
VT
tIGOL
tSLL
tIGS
VT
Output
Latch Gate
20405B-14
Latched Input and Output
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
MACH211SP-7/10/12/15/20
25
SWITCHING WAVEFORMS
tWICH
Clock
Input
Latch
Gate
VT
tWICL
VT
tWIGL
20405B-15
20405B-16
Input Register Clock Width
Input Latch Gate Width
tARW
tAPW
Input, I/O, or
Feedback
Input, I/O,
or Feedback
VT
VT
tAP
tAR
Registered
Output or
Latched
Output
Registered
Output or
Latched
Output
VT
tARR
Clock or
Input Latch
Gate
VT
VT
tAPR
Clock or
Input Latch
Gate
VT
20405B-17
20405B-18
Asynchronous Reset
Asynchronous Preset
Input, I/O, or
Feedback
VT
tER
Outputs
tEA
VOH – 0.5 V
VOL + 0.5 V
VT
20405B-19
Output Disable/Enable
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
26
MACH211SP-7/10/12/15/20
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1
Output
Test Point
R2
CL
20405B-20
Commercial
Specification
tPD, tCO
tEA
tER
S1
CL
R1
R2
Measured Output Value
Closed
Z → H: Open
35 pF
Z → L: Closed
H → Z: Open
L → Z: Closed
1.5 V
300 Ω
390 Ω
5 pF
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
* Switching several outputs simultaneously should be avoided for accurate measurement.
MACH211SP-7/10/12/15/20
27
FMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which
the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, fMAX is specified for
three types of synchronous designs.
The first type of design is a state machine with feedback signals sent off-chip. This external feedback could
go back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the
input setup time for the external signals (tS + tCO). The
reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed
device. This fMAX is designated “fMAX external.”
The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by
the internal delay from the flip-flop outputs through the
internal feedback and logic to the flip-flop inputs. This
fMAX is designated “fMAX internal”. A simple internal
counter is a good example of this type of design; therefore, this parameter is sometimes called “fCNT.”
The third type of design is a simple data path application. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the
minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third
fMAX, designated “fMAX no feedback.”
For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no
feedback, it is calculated the same way as fMAX no
feedback. The minimum period will be limited either by
the sum of the setup and hold times (tSIR + tHIR) or the
sum of the clock widths (tWICL + t WICH ). The clock
widths are normally the limiting parameters, so that
fMAXIR is specified as 1/(tWICL + tWICH). Note that if both
input and output registers are use in the same path, the
overall frequency will be limited by tICS.
All frequencies except fMAX internal are calculated from
other measured AC parameters. fMAX internal is measured directly.
CLK
CLK
(SECOND
CHIP)
LOGIC
tS
tCO
tS
fMAX External; 1/(tS + tCO)
LOGIC
REGISTER
LOGIC
REGISTER
fMAX Internal (fCNT)
CLK
CLK
REGISTER
REGISTER
tS
tSIR
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)
LOGIC
tHIR
fMAXIR; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
20405B-21
28
MACH211SP-7/10/12/15/20
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using AMD’s advanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the
factory.
Endurance Characteristics
Parameter
Symbol
tDR
N
Parameter Description
Min
Units
Test Conditions
10
Years
Max Storage Temperature
20
Years
Max Operating Temperature
100
Cycles
Normal Programming Conditions
Min Pattern Data Retention Time
Max Reprogramming Cycles
MACH211SP-7/10/12/15/20
29
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
100 kΩ
VCC
1 kΩ
ESD
Protection
Input
VCC
VCC
100 kΩ
1 kΩ
Preload
Circuitry
Feedback
Input
I/O
30
MACH211SP-7/10/12/15/20
20405B-22
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up. Following
power-up, all flip-flops will be reset to LOW. The output
state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially
valuable in simplifying state machine initialization. A
timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up
Parameter Symbol
1. The VCC rise must be monotonic.
2. Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Descriptions
tPR
Power-Up Reset Time
tS
Input or Feedback Setup Time
tWL
reset and the wide range of ways VCC can rise to its
steady state, two conditions are required to insure a
valid power-up reset. These conditions are:
Max
Unit
10
µs
See Switching Characteristics
Clock Width LOW
VCC
Power
4V
tPR
Registered
Output
tS
Clock
tWL
20405B-23
Power-Up Reset Waveform
MACH211SP-7/10/12/15/20
31
DEVELOPMENT SYSTEMS (subject to change)
For more information on the products listed below, please consult the AMD FusionPLD Catalog.
MANUFACTURER
SOFTWARE DEVELOPMENT SYSTEMS
Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
(800) 222-9323 or (408) 732-2400
MACHXL® Software
Ver. 3.0
Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
(800) 222-9323 or (408) 732-2400
Design Center/AMD Software
Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
(800) 222-9323 or (408) 732-2400
AMD-ABEL Software
Data I/O MACH Fitters
Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
(800) 222-9323 or (408) 732-2400
PROdeveloper/AMD
Software
PROsynthesis/AMD Software
Cadence Design Systems
555 River Oaks Pkwy
San Jose, CA 95134
(408) 943-1234
PLD™ Designer
Verilog, LeapFrog, RapidSim Simulators
Ver. 9504
Data I/O Corporation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
(800) 332-8246 or (206) 881-6444
ABEL™ Software
Synario™ Software
Mentor Graphics Corp.
8005 S.W. Boeckman Rd.
Wilsonville, OR 97070-7777
(800) 547-3000 or (503) 685-7000
MicroSim Corp.
20 Fairbanks
Irvine, CA 92718
(714) 770-3022
PLDSynthesis™ II
QuickSim Simulator
Design Center Software
MINC Incorporated
6755 Earl Drive, Suite 200
Colorado Springs, CO 80918
(800) 755-FPGA or (719) 590-1155
PLDesigner™-XL Software
SUSIE-CAD
10000 Nevada Highway, Suite 201
Boulder City, NV 89005
(702) 293-2271
SUSIE™ Simulator
Synopsys Logic Modeling
19500 NW Gibbs Dr.
P.O. Box 310
Beaverton, OR 97075
(503) 690-6900
Teradyne EDA
321 Harrison Ave.
Boston, MA 02118
(800) 777-2432 or (617) 422-2793
32
SmartModel® Library
MultiSIM Interactive Simulator
LASAR
MACH211SP-7/10/12/15/20
DEVELOPMENT SYSTEMS (subject to change) (continued)
MANUFACTURER
Viewlogic Systems, Inc.
293 Boston Post Road West
Marlboro, MA 01752
(800) 442-4660 or (508) 480-0881
MANUFACTURER
Acugen Software, Inc.
427-3 Amherst St., Suite 391
Nashua, NH 03063
(603) 891-1995
SOFTWARE DEVELOPMENT SYSTEMS
ViewPLD or PROPLD
(Requires PROSim Simulator MACH Fitter)
ViewSim Simulator
TEST GENERATION SYSTEM
ATGEN™ Test Generation Software
iNt GmbH
Busenstrasse 6
D-8033 Martinsried, Munich, Germany
(87) 857-6667
PLDCheck 90
Advanced Micro Devices is not responsible for any information relating to the products of third parties. The inclusion of such information is not a
representation nor an endorsement by AMD of these products.
MACH211SP-7/10/12/15/20
33
APPROVED PROGRAMMERS (subject to change)
For more information on the products listed below, please consult the AMD FusionPLD Catalog.
MANUFACTURER
PROGRAMMER CONFIGURATION
Advin Systems, Inc.
1050-L East Duane Ave.
Sunnyvale, CA 94086
(408) 243-7000
Pilot U84
BP Microsystems
100 N. Post Oak Rd.
Houston, TX 77055-7237
(800) 225-2102 or (713) 688-4600
Data I/O Corporation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
(800) 332-8246 or (206) 881-6444
BP1148
UniSite™
Model 2900
Hi/Lo
4F, No. 2, Sec. 5, Ming Shoh E. Rd.
Taipei, Taiwan
ALL-07
Logical Devices Inc./Digelec
692 S. Military Trail
Deerfield Beach, FL 33442
(800) 331-7766 or (305) 428-6868
SMS North America, Inc.
16522 NE 135th Place
Redmond, WA 98052
(800) 722-4122
or
SMS
lm Grund 15
D-7988 Vangen Im Allgau, Germany
07522-5018
BP2100
Model 3900
FLEX-700
ALLPRO™-88
Sprint
Stag Microsystems Inc.
1600 Wyatt Dr. Suite 3
Santa Clara, CA 95054
(408) 988-1118
or
Stag House
Martinfield, Welwyn Garden City
Herfordshire UK AL7 1JT
707-332148
Expert
Multisite
Stag Quazar
Stag Eclipse
System General
510 S. Park Victoria Dr.
Milpitas, CA 95035
(408) 263-6667
or
3F, No. 1, Alley 8, Lane 45
Bao Shing Rd., Shin Diau
Taipei, Taiwan
2-917-3005
34
BP1200
Turpro-1
MACH211SP-7/10/12/15/20
FX
TX
AutoSite
APPROVED ON-BOARD PROGRAMMERS
MANUFACTURER
PROGRAMMER CONFIGURATION
Corelis, Inc.
12607 Hidden Creek Way, Suite H
Cerritos, California 70703
(310) 926-6727
JTAG PROG
Advanced Micro Devices
P.O. Box 3453, MS-1028
Sunnyvale, CA 94088-3453
(800) 222-9323
MACHpro
PROGRAMMER SOCKET ADAPTERS (subject to change)
MANUFACTURER
PART NUMBER
California Integration Technologies
656 Main Street
Placerville, CA 95667
(916) 626-6168
Contact Manufacturer
EDI Corporation
P.O. Box 366
Patterson, CA 95363
(209) 892-3270
Contact Manufacturer
Emulation Technology
2344 Walsh Ave., Bldg. F
Santa Clara, CA 95051
(408) 982-0660
Contact Manufacturer
Logical Systems Corp.
P.O. Box 6184
Syracuse, NY 13217-6184
(315) 478-0722
Contact Manufacturer
Procon Technologies, Inc.
1333 Lawrence Expwy, Suite 207
Santa Clara, CA 95051
(408) 246-4456
Contact Manufacturer
MACH211SP-7/10/12/15/20
35
PHYSICAL DIMENSIONS*
PL 044
44-Pin Plastic Leaded Chip Carrier (measured in inches)
.685
.695
.650
.656
.042
.056
.062
.083
Pin 1 I.D.
.685
.695
.650
.656
.500 .590
REF .630
.013
.021
.026
.032
.050 REF
.009
.015
.090
.120
.165
.180
TOP VIEW
SIDE VIEW
* For reference only. BSC is an ANSI standard for Basic Space Centering.
36
SEATING PLANE
MACH211SP-7/10/12/15/20
16-038-SQ
PL 044
DA78
6-28-94 ae
PHYSICAL DIMENSIONS
PQT044
44-Pin Thin Quad Flat Pack (measured in millimeters)
44
1
11.80
12.20
9.80
10.20
9.80
10.20
11.80
12.20
11° – 13°
0.95
1.05
1.20 MAX
1.00 REF.
0.30
0.45
0.80 BSC
11° – 13°
16-038-PQT-2
PQT 44
7-11-95 ae
Trademarks
Copyright  1996 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc.
Bus-Friendly is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
MACH211SP-7/10/12/15/20
37