FINAL COM’L: -12/15/20 IND: -14/18/24 Lattice Semiconductor MACH215-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ■ 44 Pins ■ 38 Inputs with pull-up resistors ■ 32 Output Macrocells ■ 32 Outputs ■ 32 Input Macrocells ■ 64 Flip-flops ■ Product terms for: — Individual flip-flop clock — Individual asynchronous reset, preset — Individual output enable ■ For asynchronous and synchronous applications ■ 4 “PAL22RA8” blocks with buried macrocells ■ Pin-compatible with MACH110, MACH111, MACH210, and MACH211 ■ 12 ns tPD Commercial 14.5 ns tPD Industrial ■ 67 MHz fCNT GENERAL DESCRIPTION The MACH215 is a member of the high-performance EE CMOS MACH device family. This device has approximately three times the capability of the popular PAL20RA10 without loss of speed. This device is designed for use in asynchronous as well as synchronous applications. The MACH215 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially “PAL22RA8” structures complete with product-term arrays and programmable macrocells, individual register control product terms, and input registers. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH215 has two kinds of macrocell: output and input. The MACH215 output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. Each macrocell has its own dedicated clock, asynchronous reset, and asynchronous preset control. The polarity of the clock signal is programmable. All output macrocells can be connected to an I/O cell. The MACH215 has dedicated input macrocells which provide input registers or latches for synchronizing input signals and reducing setup time requirements. Publication# 16751 Rev. E Issue Date: May 1995 Amendment/0 BLOCK DIAGRAM I0–I1, I3–I4 I/O8–I/O15 I/O0–I/O7 8 I/O Cells 8 I/O Cells 8 8 Output Macrocells OE Output Macrocells Input Macrocells CLK OE 8 44x64 AND Logic Array and Logic Allocator 8 8 Input Macrocells CLK 8 44x64 AND Logic Array and Logic Allocator 22 8 8 4 22 Switch Matrix 22 22 44x64 AND Logic Array and Logic Allocator OE 8 CLK Output Macrocells I/O24–I/O31 8 OE Input Macrocells 8 8 8 2 CLK Output Macrocells Input Macrocells 8 8 I/O Cells 8 44x64 AND Logic Array and Logic Allocator 8 I/O Cells I/O16–I/O23 8 CLK0/I2 CLK1/I5 16751E-1 2 MACH215-12/15/20 CONNECTION DIAGRAM Top View I/O0 GND 4 2 3 I/O29 I/O28 I/O2 I/O1 5 I/O31 I/O30 I/O3 6 VCC I/O4 PLCC 1 44 43 42 41 40 I/O5 I/O6 7 39 I/O27 8 38 I/O7 I0 9 37 I/O26 I/O25 10 I/O24 CLK1/I5 I1 11 36 35 GND 12 34 GND CLK0/I2 13 33 I4 I/O8 I/O9 14 32 I3 15 31 I/O10 I/O11 16 30 I/O23 I/O22 29 I/O21 17 I/O20 I/O18 I/O19 I/O16 I/O17 GND VCC I/O14 I/O15 I/O12 I/O13 18 19 20 21 22 23 24 25 26 27 28 16751E-2 Note: Pin-compatible with MACH110, MACH111, MACH210, and MACH211. PIN DESIGNATIONS CLK/I = GND = I = I/O = VCC Clock or Input Ground Input Input/Output = Supply Voltage MACH215-12/15/20 3 ORDERING INFORMATION Commercial Products Programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 215 -12 J C FAMILY TYPE MACH = Macro Array CMOS High-Speed OPTIONAL PROCESSING Blank = Standard Processing DEVICE NUMBER 215 = 32 Asynchronous Output Macrocells, 44 Pins OPERATING CONDITIONS C = Commercial (0°C to +70°C) SPEED -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) Valid Combinations MACH215-12 MACH215-15 MACH215-20 4 JC Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH215-12/15/20 (Com’l) ORDERING INFORMATION Industrial Products Programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 215 -14 J I FAMILY TYPE MACH = Macro Array CMOS High-Speed OPTIONAL PROCESSING Blank = Standard Processing DEVICE NUMBER 215 = 32 Asynchronous Output Macrocells, 44 Pins OPERATING CONDITIONS I = Industrial (–40°C to +85°C) SPEED -14 = 14.5 ns tPD -18 = 18 ns tPD -24 = 24 ns tPD PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) Valid Combinations MACH215-14 MACH215-18 MACH215-24 JI Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH215-14/18/24 (Ind) 5 FUNCTIONAL DESCRIPTION Table 1. Logic Allocation The MACH215 consists of four asynchronous PAL blocks connected by a switch matrix. There are 32 I/O pins and 4 dedicated input pins feeding the switch matrix. These signals are distributed to the four PAL blocks for efficient design implementation. There are also two additional global clock pins that can be used as dedicated inputs. This device provides two kinds of macrocell: output macrocells and input macrocells. This adds greater logic density without affecting the number of pins. M0 M1 M2 M3 M4 M5 M6 M7 The PAL Blocks Each PAL block in the MACH215 (Figure 1) contains a 64-product-term array, a logic allocator, 8 output macrocells, 8 input macrocells, and 8 I/O cells. The switch matrix feeds each PAL block with 22 inputs. This makes the PAL block look effectively like an independent “PAL22RA8” with 8 input macrocells. All flip-flops within the device can operate independently. The Switch Matrix The MACH215 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 16 internal feedback signals and 8 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that also provides for high performance. The design software automatically configures the switch matrix when fitting a design into the device. The Product-term Array The MACH215 product-term array consists of 32 product terms for logic use and 32 product terms for generating macrocell control signals. The logic allocator in the MACH215 (Figure 2) takes the 32 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 12 product terms. The design software automatically configures the logic allocator when fitting the design into the device. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. 6 C0, C1 C0, C1, C2 C1, C2, C3 C2, C3, C4 C3, C4, C5 C4, C5, C6 C5, C6, C7 C6, C7 The Macrocell There are two types of macrocell in the MACH215: output macrocells and input macrocells. The output macrocell takes the logic of the device and provides it to I/O pins and/or provides feedback for additional logic generation. The input macrocell allows I/O pins to be configured as registered or latched inputs. The output macrocell (Figure 3) can generate registered or combinatorial outputs. In addition, a transparent-low latched configuration is provided. If used, the register can be configured as a T-type or a D-type flip-flop. Register and latch functionality is defined in Table 2. Programmable polarity and the T-type flip-flop both give the software a way to minimize the number of product terms needed. These choices can be made automatically by the software when it fits the design into the device. Table 2. Register/Latch Operation Configuration The Logic Allocator Available Clusters Output Macrocell D/T CLK/LE* Q+ D-Register X 0 1 0, 1, ↓ (↑) ↑ (↓) ↑ (↓) Q 0 1 T-Register X 0 1 0, 1, ↓ (↑) ↑ (↓) ↑ (↓) Q Q Q Latch X 0 1 1 (0) 0 (1) 0 (1) Q 0 1 *Polarity of CLK/LE can be programmed. MACH215-12/15/20 The output macrocell sends its output back to the switch matrix, via internal feedback, and to the I/O cell. The feedback is always available regardless of the configuration of the I/O cell. This allows for buried combinatorial or registered functions, freeing up the I/O pins for use as inputs if not needed as outputs. The basic output macrocell configurations are shown in Figure 4. The clock/latch-enable for each individual output macrocell can be driven by one of four signals. Two of the signals are provided by the global clock pin CLK0/LE0; either polarity may be chosen. The other two signals come from a product term provided for each output macrocell. Either polarity of the logic generated by the product term can be chosen. The global clock pin is also available as an input, although care must be taken when a signal acts as both clock and input to the same device. Each individual output macrocell also has a product term for asynchronous reset and a product term for asynchronous preset. This means that any register or latch may be reset or preset without affecting any other register or latch in the device. The functionality of the flip-flops with respect to initialization is illustrated in Table 3. The input macrocell (Figure 5) consists of a flip-flop that can be used to provide registered or latched inputs. The flip-flop can be clocked by either polarity of one of the two global clock/latch-enable pins. Reset or preset are not provided for these flip-flops. If combinatorial inputs are desired, this macrocell is not used, and the feedback from the I/O pin is used directly. Both the I/O pin feedback and the output of the input register or latch are always available to the switch matrix. Possible input macrocell configurations are shown in Figure 6. The I/O Cell The I/O cell (Figure 7) provides a three-state output buffer. The three-state control is provided by an individual product term for each I/O cell. Depending on the logic programmed onto this product term, the I/O pin can be configured as an output, an input, or a bidirectional pin. The feedback from the I/O pin is always available to the switch matrix, regardless of the state of the output buffer or the output macrocell. Table 3. Asynchronous Reset/Preset Operation AR 0 0 1 1 AP 0 1 0 1 CLK/LE X X X X Q+ See Table 12 1 0 0 MACH215-12/15/20 7 0 4 8 12 16 20 24 28 32 36 40 43 Output Macro Cell M0 I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O 2 2 Input Macro Cell Output Macro Cell M1 2 2 Input Macro Cell 0 Output Macro Cell M2 C0 2 C1 Switch Matrix C3 C4 Logic Allocator C2 2 Output Macro Cell M3 2 2 M4 Input Macro Cell Output Macro Cell 2 C5 C6 Input Macro Cell 2 M5 Input Macro Cell Output Macro Cell 2 C7 64 63 2 M6 Input Macro Cell Output Macro Cell 2 2 M7 Input Macro Cell Output Macro Cell 2 2 8 12 16 20 24 28 32 36 40 43 CLK1 4 CLK0 0 Input Macro Cell 16 8 16751E-3 Figure 1. MACH215 PAL Block 8 MACH215-12/15/20 To n–1 From n–1 n n Product Term Cluster To n+1 To Macrocell n From n+1 Logic Allocator 16751E-4 Figure 2. Product Term Clusters and the Logic Allocator Individual Asynchronous Preset 1 AP D/T/L Q Sum of Products from Logic Allocator CLK0 Individual Clock 1 0 0 To I/O Cell AR Individual Asynchronous Reset To Switch Matrix 16751E-5 Figure 3. Output Macrocell MACH215-12/15/20 9 n From Logic Allocator To I/O Cell To Switch Matrix a. Combinatorial, Active High b. Combinatorial, Active Low Individual Preset n D APQ CLK0 Individual Clock To I/O Cell From Logic Allocator AR D APQ CLK0 To I/O Cell AR Individual Preset To Switch Matrix To Switch Matrix c. D-type Register, Active High d. D-type Register, Active Low Individual Preset Individual Preset n T APQ CLK0 Individual Clock To I/O Cell From Logic Allocator n T APQ CLK0 Individual Clock AR Individual Preset To I/O Cell AR Individual Preset To Switch Matrix To Switch Matrix f. T-type Register, Active Low e. T-type Register, Active High Individual Preset From Logic Allocator n Individual Clock Individual Preset From Logic Allocator To I/O Cell To Switch Matrix Individual Preset From Logic Allocator n From Logic Allocator Individual Preset n L APQ CLK0 G AR Individual Clock Individual Preset To I/O Cell From Logic Allocator n L APQ CLK0 To I/O Cell G AR Individual Clock Individual Preset To Switch Matrix To Switch Matrix h. Latch, Active Low g. Latch, Active High 16751E-6 Figure 4. Output Macrocell Configurations 10 MACH215-12/15/20 From I/O Pin AP D/L Q CLK0 CLK1 To Switch Matrix 16751E-7 Figure 5. Input Macrocell From I/O Cell From I/O Cell D L Q CLK0 CLK0 CLK1 CLK1 Q G To Switch Matrix To Switch Matrix b. Input Latch a. Input Register 16751E-8 Figure 6. Input Macrocell Configurations Individual Output Enable Product Term From Output Macrocell To Switch Matrix To Input Macrocell 16751E-9 Figure 7. I/O Cell MACH215-12/15/20 11 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +70°C) . . . . . . . . . . . . . . . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 24 mA, VCC = Min VIN = VIH or VIL (Note 1) VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) 0.8 V IIH Input HIGH Current VIN = 5.25 V, VCC = Max (Note 3) 10 µA IIL Input LOW Current VIN = 0 V, VCC = Max (Note 3) –100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) –160 mA ICC Supply Current (Typical) VCC = 5 V, TA = 25°C, f = 25 MHz (Note 5) V 0.5 2.0 V V –30 95 mA Notes: 1. 2. 3. 4. Total IOL for one PAL block should not exceed 128 mA. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. 12 MACH215-12/15/20 (Com’l) CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) -12 Min Max Parameter Symbol Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tSA Setup Time from Input, I/O, or Feedback to Product Term Clock 3 fMAXA tSS Internal Feedback (fCNTA) 6 7 9 ns Setup Time from Input, I/O, or Feedback to Global Clock tHS Register Data Hold Time Using Global Clock tCOS Global Clock to Output (Note 3) tWHS fMAXS Global Clock Width Maximum Frequency Using Global Clock (Note 1) External Feedback 1/(tSS + tCOS) Internal Feedback (fCNTS) No Feedback 4 8 18 4 ns 22 ns 8 9 12 ns HIGH 8 9 12 ns D-type 52.6 41.7 33.3 MHz T-type 50 40 32.2 MHz D-type 58.8 45.5 35.7 MHz T-type 55.6 43.5 34.5 MHz 62.5 55.6 41.7 MHz D-type 7 10 13 ns T-type 8 11 14 ns 0 0 0 ns 2 tWLS 6 14 LOW 1/(tWLA + tWHA) No Feedback ns T-type 4 1/(tSA + tCOA) Unit ns 5 External Feedback 20 8 Product Term Clock to Output (Note 3) Maximum Frequency Using Product Term Clock (Note 1) 3 6 Register Data Hold Time Using Product Term Clock tWHA 15 5 tHA Product Term, Clock Width 3 -20 Min Max D-type tCOA tWLA 12 -15 Min Max 8 2 10 2 12 ns LOW 6 6 8 ns HIGH 6 6 8 ns D-type 66.7 50 40 MHz T-type 62.5 47.6 38.5 MHz D-type 83.3 66.6 50 MHz T-type 76.9 62.5 47.6 MHz 83.3 83.3 62.5 MHz 5 6 8 ns 5 6 8 ns 1/(tWLS + tWHS) tHLA Setup Time from Input, I/O, or Feedback to Product Term Gate Latch Data Hold Time Using Product Term Clock tGOA Product Term Gate to Output (Note 3) tGWA Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) 8 9 12 ns tSLS Setup Time from Input, I/O, or Feedback to Global Gate 7 10 13 ns tHLS Latch Data Hold Time Using Global Gate 0 0 0 ns tGOS Gate to Output (Note 3) tGWS Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) tSLA 16 19 10 MACH215-12/15/20 (Com’l) 6 22 11 6 12 8 ns ns ns 13 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description tPDL -12 Min Max Input, I/O, or Feedback to Output Through Transparent Input or Output Latch -15 Min Max 14 -20 Min Max 17 22 Unit ns tSIR Input Register Setup Time 2 2 2 ns tHIR Input Register Hold Time 2 2.5 3 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup tWICL Input Register Clock Width tWICH fMAXIR Maximum Input Register Frequency 15 18 23 ns D-type 12 15 20 ns T-type 13 16 21 ns LOW 6 6 8 ns HIGH 6 6 8 ns 83.3 83.3 62.5 MHz 1/(tWICL + tWICH) tSIL Input Latch Setup Time 2 2 2 ns tHIL Input Latch Hold Time 2 2.5 3 ns tIGO Input Latch Gate to Combinatorial Output 17 20 25 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 19 22 27 ns tSLLA Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Latch Gate tIGSA Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate tSLLS Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Global Output Latch Gate 7 8 10 ns 7 8 10 ns 9 12 15 ns tIGSS Input Latch Gate to Output Latch Setup Using Global Output Latch Gate 13 16 21 ns tWIGL Input Latch Gate Width LOW 6 6 8 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 16 19 24 ns Asynchronous Reset to Registered or Latched Output 16 20 25 ns tAR tARW Asynchronous Reset Width (Note 1) 12 tARR Asynchronous Reset Recovery Time (Note 1) 8 tAP Asynchronous Preset to Registered or Latched Output 15 20 10 16 ns 15 20 ns 25 ns tAPW Asynchronous Preset Width (Note 1) 12 15 20 ns tAPR Asynchronous Preset Recovery Time (Note 1) 8 10 15 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 2 12 2 15 2 20 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 2 12 2 15 2 20 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. Switching waveforms illustrate true clocks only. Switching waveforms can be used to illustrate both synchronous and asynchronous clock timing. For example, tSS is the tS parameter for synchronous clocks and tSA is the tS parameter for asynchronous clocks. 3. Parameters measured with 16 outputs switching. 14 MACH215-12/15/20 (Com’l) ABSOLUTE MAXIMUM RATINGS INDUSTRIAL OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . –40°C to +85°C Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . . . +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = –40°C to +85°C) . . . . . . . . . . . . . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 24 mA, VCC = Min VIN = VIH or VIL (Note 1) VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) –100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) –160 mA ICC Supply Current (Typical) VCC = 5 V, TA = 25°C, f = 25 MHz (Note 5) V 0.5 2.0 V V –30 95 mA Notes: 1. Total IOL for one PAL block should not exceed 128 mA. 2. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. MACH215-14/18/24 (Ind) 15 CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) -14 Min Max Parameter Symbol Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tSA Setup Time from Input, I/O, or Feedback to Product Term Clock tHA Register Data Hold Time Using Product Term Clock tCOA Product Term Clock to Output (Note 3) tWLA Product Term, Clock Width tWHA fMAXS tSS Maximum Frequency Using Product Term Clock (Note 1) External Feedback 1/(tSA + tCOA) Internal Feedback (fCNTA) No Feedback tHS Register Data Hold Time Using Global Clock tCOS Global Clock to Output (Note 3) fMAXS Maximum Frequency Using Global Clock (Note 1) External Feedback 1/(tSS + tCOS) Internal Feedback (fCNTS) No Feedback 24 Unit ns D-type 6 7.5 10 ns T-type 7.5 8.5 11 ns 6 7.5 17 10 22 ns 26.5 ns LOW 10 11 15 ns HIGH 10 11 15 ns D-type 42 33 26.5 MHz T-type 40 32 25.5 MHz D-type 47 36 28.5 MHz T-type 44 34.5 27.5 MHz 50 44.5 33 MHz D-type 8.5 12 16 ns T-type 10 13.5 17 ns 0 0 0 12 ns 14.5 ns LOW 7.5 7.5 10 HIGH 7.5 7.5 10 ns D-type 53 40 32 MHz T-type 50 38 30.5 MHz D-type 66.5 53 40 MHz T-type 61.5 50 38 MHz 66.5 66.5 50 MHz 6 7.5 10 ns 1/(tWLS + tWHS) ns tHLA Setup Time from Input, I/O, or Feedback to Product Term Gate Latch Data Hold Time Using Product Term Clock tGOA Product Term Gate to Output (Note 3) tGWA Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) 10 11 14.5 8.5 12 16 ns 0 0 0 ns tSLA 16 Global Clock Width -24 Min Max 18 10 tWLS tWHS 14.5 1/(tWLA + tWHA) Setup Time from Input, I/O, or Feedback to Global Clock -18 Min Max tSLS Setup Time from Input, I/O, or Feedback to Global Gate tHLS Latch Data Hold Time Using Global Gate tGOS Gate to Output (Note 3) tGWS Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) 6 7.5 19.5 12 MACH215-14/18/24 (Ind) 7.5 10 23 13.5 7.5 ns 26.5 ns 14.5 10 ns ns ns SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued) -14 Parameter Symbol Parameter Description Min tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch -18 Max Min 17 -24 Max Min 20.5 Max Unit 26.5 ns tSIR Input Register Setup Time 2.4 2.4 2.4 ns tHIR Input Register Hold Time 3 3.5 4 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup tWICL tWICH fMAXIR Input Register Clock Width Maximum Input Register Frequency 18 18 24 ns T-type 16 19.5 25.5 ns LOW 7.5 7.5 10 ns HIGH 7.5 7.5 10 ns 66.5 66.5 50 MHz 2.5 2.5 ns Input Latch Setup Time 2.5 3 Input Latch Hold Time Input Latch Gate to Combinatorial Output tIGOL Input Latch Gate to Output Through Transparent Output Latch tSLLA ns 14.5 tSIL tHIL 28 D-type 1/(tWICL + tWICH) tIGO 22 Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Latch Gate 3.5 4 ns 20.5 24 30 ns 23 26.5 32.5 ns 8.5 10 12 ns tIGSA Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate 8.5 10 12 ns tSLLS Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Global Output Latch Gate 11 14.5 18 ns tIGSS Input Latch Gate to Output Latch Setup Using Global Output Latch Gate 16 19.5 25.5 ns tWIGL Input Latch Gate Width LOW 7.5 7.5 10 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 19.5 23 29 ns tAR Asynchronous Reset to Registered or Latched Output 19.5 24 30 ns tARW Asynchronous Reset Width (Note 1) tARR Asynchronous Reset Recovery Time (Note 1) tAP Asynchronous Preset to Registered or Latched Output 14.5 18 24 ns 10 12 18 ns 19.5 14.5 24 18 30 tAPW Asynchronous Preset Width (Note 1) tAPR Asynchronous Preset Recovery Time (Note 1) tEA Input, I/O, or Feedback to Output Enable (Note 3) 14.5 18 24 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 14.5 18 24 ns 10 24 ns 12 ns 18 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. Switching waveforms illustrate true clocks only. Switching waveforms can be used to illustrate both synchronous and asynchronous clock timing. For example, tSS is the tS parameter for synchronous clocks and tSA is the tS parameter for asynchronous clocks. 3. Parameters measured with 16 outputs switching. MACH215-14/18/24 (Ind) 17 TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS VCC = 5.0 V, TA = 25°C IOL (mA) 80 60 40 20 VOL (V) –1.0 –0.8 –0.6 –0.4 –0.2 –20 .2 .4 .6 .8 1.0 –40 –60 –80 16751E-10 Output, LOW IOH (mA) 25 1 2 3 4 5 VOH (V) –3 –2 –1 –25 –50 –75 –100 –125 –150 16751E-11 Output, HIGH II (mA) 20 VI (V) –2 –1 –20 1 2 3 4 5 –40 –60 –80 –100 16751E-12 Input 18 MACH215-12/15/20 TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25°C 150 125 MACH215 100 ICC (mA) 75 50 25 0 0 10 20 30 40 50 60 70 80 90 Frequency (MHz) 16751E-13 The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. MACH215-12/15/20 19 TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Parameter Symbol Parameter Description Typ PLCC Units θjc Thermal impedance, junction to case 15 °C/W θja Thermal impedance, junction to ambient 40 °C/W 200 lfpm air 36 °C/W 400 lfpm air 33 °C/W 600 lfpm air 31 °C/W 800 lfpm air 29 °C/W θjma Thermal impedance, junction to ambient with air flow Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 20 MACH215-12/15/20 SWITCHING WAVEFORMS Input, I/O, or Feedback VT tPD Combinatorial Output VT 16751E-14 Combinatorial Output Input, I/O, or Feedback Input, I/O, or Feedback VT tS VT tH tSL Gate VT Clock tHL tCO Registered Output VT tPDL tGO Latched Out VT VT 16751E-16 16751E-15 Registered Output Latched Output (MACH 2, 3, and 4) tWH Clock Gate VT tGWS tWL 16751E-18 16751E-17 Clock Width Gate Width (MACH 2, 3, and 4) Registered Input VT tSIR Input Register Clock Registered Input VT tHIR Input Register Clock VT tICO Combinatorial Output VT 16751E-19 Output Register Clock Registered Input (MACH 2 and 4) VT tICS VT 16751E-20 Input Register to Output Register Setup (MACH 2 and 4) Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. MACH215-12/15/20 21 SWITCHING WAVEFORMS Latched In VT tSIL tHIL Gate VT tIGO Combinatorial Output VT 16751E-21 Latched Input (MACH 2 and 4) tPDLL Latched In VT Latched Out Input Latch Gate VT tIGOL tSLL tIGS VT Output Latch Gate 16751E-22 Latched Input and Output (MACH 2, 3, and 4) Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. 22 MACH215-12/15/20 SWITCHING WAVEFORMS tWICH Clock Input Latch Gate VT VT tWICL tWIGL 16751E-24 16751E-23 Input Register Clock Width (MACH 2 and 4) Input Latch Gate Width (MACH 2 and 4) tARW tAPW Input, I/O, or Feedback Input, I/O, or Feedback VT VT tAR Registered Output tAP Registered Output VT VT tARR Clock tAPR Clock VT VT 16751E-25 16751E-26 Asynchronous Reset Asynchronous Preset Input, I/O, or Feedback VT tER Outputs tEA VOH - 0.5V VOL + 0.5V VT 16751E-27 Output Disable/Enable Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. MACH215-12/15/20 23 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT 5V S1 R1 Output Test Point R2 CL 16751E-28 Commercial Specification tPD, tCO tEA tER S1 CL R1 R2 Closed Measured Output Value 1.5 V Z → H: Open Z → L: Closed 35 pF H → Z: Open L → Z: Closed 5 pF 1.5 V 300 Ω 390 Ω H → Z: VOH – 0.5 V L → Z: VOL + 0.5 V *Switching several outputs simultaneously should be avoided for accurate measurement. 24 MACH215-12/15/20 fMAX PARAMETERS The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated “fMAX external.” The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated “fMAX internal”. A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called “fCNT.” The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated “fMAX no feedback.” For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly. CLK CLK (SECOND CHIP) LOGIC LOGIC REGISTER tS t CO tS fMAX Internal (fCNT) fMAX External; 1/(tS + tCO) LOGIC REGISTER CLK CLK REGISTER REGISTER tS tSIR fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL) LOGIC tHIR fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH) 16751E-29 MACH215-12/15/20 25 ENDURANCE CHARACTERISTICS The MACH families are manufactured using our advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics Parameter Symbol tDR N 26 Parameter Description Min Units Test Conditions 10 Years Max Storage Temperature Min Pattern Data Retention Time 20 Years Max Operating Temperature Max Reprogramming Cycles 100 Cycles Normal Programming Conditions MACH215-12/15/20 INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC 100 kΩ 1 kΩ VCC ESD Protection Input VCC VCC 100 kΩ 1 kΩ Preload Circuitry Feedback Input 16751E-30 I/O MACH215-12/15/20 27 POWER-UP RESET The MACH devices have been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the Parameter Symbol wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Descriptions Max Unit tPR Power-Up Reset Time 10 µs tS Input or Feedback Setup Time tWL Clock Width LOW See Switching Characteristics VCC Power 4V tPR Registered Output tS Clock tWL 16751E-31 Power-Up Reset Waveform 28 MACH215-12/15/20 USING PRELOAD AND OBSERVABILITY In order to be testable, a circuit must be both controllable and observable. To achieve this, the MACH devices incorporate register preload and observability. Preloaded HIGH D In preload mode, each flip-flop in the MACH device can be loaded from the I/O pins, in order to perform functional testing of complex state machines. Register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. This ability to control the MACH device’s internal state can shorten test sequences, since it is easier to reach the state of interest. Q1 Q AR Preloaded HIGH The observability function makes it possible to see the internal state of the buried registers during test by overriding each register’s output enable and activating the output buffer. The values stored in output and buried registers can then be observed on the I/O pins. Without this feature, a thorough functional test would be impossible for any designs with buried registers. D Q2 Q AR While the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. One case involves asynchronous reset and preset. If the MACH registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. This is illustrated in Figure 8. Care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. Another case to be aware of arises in testing combinatorial logic. When an output is configured as combinatorial, the observability feature forces the output into registered mode. When this happens, all product terms are forced to zero, which eliminates all combinatorial data. For a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. If the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in Figure 9. As this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. To insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. On Preload Mode Off Q1 AR Q2 Figure 8. Preload/Reset Conflict 16751E-32 Set All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support. Reset Figure 9. Combinatorial Latch 16751E-33 MACH215-12/15/20 29 PHYSICAL DIMENSIONS* PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches) .685 .695 .650 .656 .042 .056 .062 .083 Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630 .013 .021 .026 .032 .050 REF .009 .015 TOP VIEW SEATING PLANE SIDE VIEW *For reference only. BSC is an ANSI standard for Basic Space Centering. 34 .090 .120 .165 .180 MACH215-12/15/20 16-038-SQ PL 044 DA78 6-28-94 ae