LATTICE MACH4-96

MACH 4 FAMILY
1
FINAL
COM’L: -15
IND: -18
Lattice Semiconductor
MACH4-96/96-15
High-Performance EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
◆ 144 Pins in PQFP
◆ 96 Macrocells
◆
◆
◆
◆
◆
MACH 4 Family
◆ 15 ns tPD Commercial, 18 ns tPD Industrial
◆ 47.6 MHz fCNT
◆ 102 Inputs with pull-up resistors
◆ 96 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs
◆ 96 Flip-flops
◆ Up to 20 product terms per macrocell, with XOR
◆ Flexible clocking
— Four global clock pins with selectable edges
— Asynchronous mode available for each macrocell
3 MACH111SP-size blocks
SpeedLocking™ for guaranteed fixed timing
JTAG, 5-V, in-system programmable
JTAG (IEEE 1149.1) boundary scan testing capability
Input and output switch matrices for high routability
PLEASE NOTE: The MACH4-96/96 (M4-96/96) reflects a new nomenclature for the MACH® 4 Family.
This device is currently dual-marked with the MACH355 ordering part number. The dual-mark
scheme will facilitate design and manufacturing flows until we have completely phased in the new
M4-96/96 nomenclature. Please use the MACH355 data sheet (PID# 17467) as a reference.
GENERAL DESCRIPTION
The MACH4-96/96 (M4-96/96) is a member of Vantis’ high-performance EE CMOS MACH 4 family.
This device has approximately three times the macrocell capability of the popular MACH111SP,
with significant additional density and functional features.
The M4-96/96 consists of six PAL® blocks interconnected by a programmable central switch matrix.
The central switch matrix connects the PAL blocks to each other and to all input pins, providing a
high degree of connectivity between the PAL blocks. This allows designs to be placed and routed
efficiently. Routability is further enhanced by an input switch matrix and an output switch matrix.
The input switch matrix provides input signals with alternative paths into the central switch matrix;
the output switch matrix provides flexibility in assigning macrocells to I/O pins.
Publication# 21535
Amendment/+1
Rev: A
Issue Date: November 1997
1
V A N T I S
The M4-96/96 has macrocells that can be configured as synchronous or asynchronous. This allows
designers to implement both synchronous and asynchronous logic together on the same device.
The two types of design can be mixed in any proportion, since the selection on each macrocell
affects only that macrocell.
Up to 20 product terms per macrocell can be assigned. It is possible to allocate some product terms
away from a macrocell without losing the use of that macrocell for logic generation.
The M4-96 macrocell provides either registered or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the register can be configured as D-type, T-type, JK, or S-R to help reduce the number of product terms used. The flip-flop can also be configured as
a latch. The register type decision can be made by the designer using software.
All macrocells can be connected to an I/O cell through the output switch matrix. The output switch
matrix makes it possible to make significant design changes while minimizing the risk of pinout
changes.
Vantis offers software design support for MACH devices through its own development system and
device fitters integrated into third-party CAE tools. Platform support extends across PCs, Sun and
HP workstations under advanced operating systems such as Windows 3.1, Windows 95 and NT,
SunOS and Solaris, and HPUX.
MACHXL® software is a complete development system for the PC, supporting Vantis’ MACH
devices. It supports design entry with Boolean and behavioral syntax, state machine syntax and
truth tables. Functional simulation and static timing analysis are also included in this easy-to-use
system. This development system includes high-performance device fitters for all MACH devices.
The same fitter technology included in MACHXL software is seamlessly incorporated into thirdparty tools from leading CAE vendors such as Synario, Viewlogic, Mentor Graphics, Cadence and
MINC. Interface kits and MACHXL configurations are also available to support design entry and
verification with other leading vendors such as Synopsys, Exemplar, OrCAD, Synplicity and Model
Technology. These MACHXL configurations and interfaces accept EDIF 2.0.0 netlists, generate
JEDEC files for MACH devices, and create industry-standard SDF, VITAL-compliant VHDL and
Verilog output files for design simulation.
Vantis offers in-system programming support for MACH devices through its MACHPRO® software
enabling MACH device programmability through JTAG compliant ports and easy-to-use PC
interface. Additionally, MACHPRO generated vectors work seamlessly with HP3070, GenRad and
Teradyne testers to program MACH devices or test them for connectivity.
All MACH devices are supported by industry standard programmers available from a number of
vendors. These programmer vendors include Advin Systems, BP Microsystems, Data I/O
Corporation, Hi-Lo Systems, SMS GmbH, Stag House, and System General.
2
MACH4-96/96-15
4
4
MACH4-96/96-15
OE
OE
4
Block D
I/O48-I/O63
Block E
I/O64-I/O79
16
16
Output Switch
Matrix
16
4
16
16
Macrocells
I/O Cells
16
Clock Generator
I/O Cells
16
Output Switch
Matrix
4
OE
16
Input Switch
Matrix
16
16
66 X 98
AND Logic Array
and Logic Allocator
33
16
16
32
4
16
4
4
16
4
OE
16
Macrocells
4
Input Switch
Matrix
32
4
16
16
Input Switch
Matrix
Central Switch Matrix
33
66 X 98
AND Logic Array
and Logic Allocator
16
Macrocells
16
Output Switch
Matrix
16
I/O Cells
16
Block F
I/O80-I/O95
16
I/O Cells
16
Output Switch
Matrix
16
Macrocells
16
66 X 98
AND Logic Array
and Logic Allocator
33
33
66 X 98
AND Logic Array
and Logic Allocator
16
Macrocells
16
Output Switch
Matrix
16
I/O Cells
16
I/O0-I/015
Block A
16
16
32
32
16
16
Input Switch
Matrix
4
4
Block B
I/O16-I/031
OE
16
66 X 98
AND Logic Array
and Logic Allocator
32
32
4
4
16
4
OE
33
16
16
Input Switch
Matrix
33
66 X 98
AND Logic Array
and Logic Allocator
16
Macrocells
16
Output Switch
Matrix
16
I/O Cells
16
Clock Generator
4
4
16
4
Block C
Clock Generator
4
Clock Generator
Input Switch
Matrix
Clock Generator
Clock Generator
I0/CLK0, I1/CLK1,
I3/CLK2, I4/CLK3
3
MACH 4 Family
I/O32-I/047
2
V A N T I S
BLOCK DIAGRAM
I2, I5
V A N T I S
CONNECTION DIAGRAM
Top View
144-Pin PQFP
Block F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
I/O35
GND
I/O36
I/O37
I/O38
I/O39
VCC
I/O40
I/O41
GND
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
VCC
GND
GND
VCC
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
GND
I/O54
I/O55
VCC
I/O56
I/O57
I/O58
I/O59
GND
I/O60
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I/O13
I/O14
I/O15
VCC
TDI
I5
GND
I0/CLK0
I1/CLK1
I/O16
I/O17
VCC
I/O18
I/O19
GND
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
VCC
GND
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
GND
TMS
TCK
VCC
I/O32
I/O33
I/O34
Block C
Block D
PIN DESIGNATIONS
CLK/I
= Clock or Input
TMS
= Test Mode Select
GND
= Ground
TCK
= Test Clock
I
= Input
TDO
= Test Data Out
I/O
= Input/Output
TRST
= Test Reset
VCC
= Supply Voltage
ENABLE = Program
TDI
= Test Data In
4
MACH4-96/96-15
I/O82
I/O81
I/O80
VCC
TDO
TRST
GND
I4/CLK3
I3/CLK2
I/O79
I/O78
VCC
I/O77
I/O76
GND
I/O75
I/O74
I/O73
I/O72
I/O71
I/O70
VCC
GND
I/O69
I/O68
I/O67
I/O66
I/O65
I/O64
GND
I2
ENABLE
VCC
I/O63
I/O62
I/O61
Block E
Block B
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
I/O12
GND
I/O11
I/O10
I/O9
I/O8
VCC
I/O7
I/O6
GND
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
GND
GND
VCC
I/O95
I/O94
I/O93
I/O92
I/O91
I/O90
GND
I/O89
I/O88
VCC
I/O87
I/O86
I/O85
I/O84
GND
I/O83
Block A
V A N T I S
ORDERING INFORMATION
Commercial Products
Vantis programmable logic products for commercial applications are available with several ordering options. The order
number (Valid Combination) is formed by a combination of:
M4
-96
/96
-15
Y
C
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
DEVICE NUMBER
96 = 96 Macrocells
PACKAGE TYPE
Y = 144-Pin Plastic Quad Pack
(PQR144)
I/O
/96 =144-pin Package
SPEED
-15 = 15 ns tPD
Valid Combinations
MACH4-96/96-15
YC
MACH 4 Family
FAMILY TYPE
M4 = MACH 4 Family (5-V VCC)
Valid Combinations
The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local Vantis
sales office to confir m availability of specific valid
combinations and to check on newly released combinations.
MACH4-96/96-15 (Com’l)
5
V A N T I S
ORDERING INFORMATION
Industrial Products
Vantis programmable logic products for commercial applications are available with several ordering options. The order
number (Valid Combination) is formed by a combination of:
M4
-96
/96
-18
Y
I
FAMILY TYPE
M4 = MACH 4 Family (5-V VCC)
OPERATING CONDITIONS
I= Industrial (–40°C to +85°C)
DEVICE NUMBER
96 = 96 Macrocells
PACKAGE TYPE
Y = 144-Pin Plastic Quad Pack
(PQR144)
I/O
/96 =144-pin Package
SPEED
-18 = 18 ns tPD
Valid Combinations
MACH4-96/96-18
6
YI
Valid Combinations
The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local Vantis
sales office to confir m availability of specific valid
combinations and to check on newly released combinations.
MACH4-96/96-18 (Ind)
V A N T I S
FUNCTIONAL DESCRIPTION
The M4-96/96 consists of six PAL blocks connected by a central switch matrix. There are 96 I/O
pins and 6 dedicated input pins feeding the central switch matrix. These signals are distributed to
the eight PAL blocks for efficient design implementation. There are 4 global clock pins that can
also be used as dedicated inputs.
All inputs and I/O pins have built-in pull-up resistors. While it is always good design practice to
tie unused pins high, the pull-up resistors provide design security and stability in the event that
unused pins are left disconnected.
Each PAL block in the M4-96/96 (Figure 7) contains a clock generator, a 98-product-term logic
array, a logic allocator, 16 macrocells, an output switch matrix, 16 I/O cells, and an input switch
matrix. The central switch matrix feeds each PAL block with 33 inputs. This makes the PAL block
look effectively like an independent “PALCE33V16”.
In addition to the logic product terms, individual output enable product terms and two PAL block
initialization product term are provided. Each I/O pin can be individually enabled. All flip-flops
that are in the synchronous mode within a PAL block are initialized together by either of the PAL
block initialization product terms.
Dedicated
Input Pins
33
Logic
Array
Input
Switch
Matrix
Logic 16
Output
Allocator
Macrocells
with XOR
16
16
16
16
I/O Cells
Central Switch Matrix
Clock/Input
Pins
Output Switch Matrix
PAL Block
4
Clock
Generator
I/O
Pins
I/O
Pins
PAL Block
PAL Block
I/O
Pins
21535A-1
Figure 1. MACH4-96/96 Block Diagram and PAL Block Structure
The Central Switch Matrix and Input Switch Matrix
The M4-96/96 central switch matrix is fed by the input switch matrices in each PAL block. Each
PAL block provides 16 internal feedback signals and 16 I/O pin signals to the input switch matrix.
Of these 32 signals, 24 decoded signals are provided to the central switch matrix by the input
switch matrix. The central switch matrix distributes these signals back to the PAL blocks in a very
efficient manner that provides for high performance. The design software automatically configures
the input and central switch matrices when fitting a design into the device. The input switch matrix
(Figure 2) optimizes routing of inputs to the central switch matrix. Without the input switch matrix,
each input and feedback signal has only one way to enter the central switch matrix. The input
switch matrix provides additional ways for these signals to enter the central switch matrix.
MACH4-96/96-15
7
MACH 4 Family
The PAL Blocks
From I/O Pin
To Central Switch Matrix
From Macrocell
V A N T I S
21535A-2
Figure 2. MACH4-96/96 Input Switch Matrix
The Clock Generator
Each PAL block has a clock generator that can generate four clock signals for use throughout the PAL
block. These four signals are available to all macrocells and I/O cells in the PAL block, whether in
synchronous or asynchronous mode. The clock generator chooses the four signals from the eight
possible signals given by the true and complement versions of the four global clock pin signals.
GCLK0
Block CLK0
(GCLK0 or GCLK1)
GCLK1
Block CLK1
(GCLK1 or GCLK0)
GCLK2
Block CLK2
(GCLK2 or GCLK3)
GCLK3
Block CLK3
(GCLK3 or GCLK2)
21535A-3
Figure 3.
PAL Block Clock Generator
Synchronous and Asynchronous Operation
The MACH 4 family can perform synchronous or asynchronous logic. Each individual cell can be
programmed as synchronous or asynchronous, allowing unlimited “mixing and matching” of the
two logic styles. The selection of synchronous or asynchronous mode affects the logic allocator
and the macrocell, since product terms used for logic in the synchronous mode are used for control
functions in the asynchronous mode.
The Product-Term Array
The M4-96/96 product-term array consists of 80 product terms for logic use, 16 product terms for
output enable use, and two product terms for global PAL block initialization. Each macrocell has
8
MACH4-96/96-15
V A N T I S
a nominal allocation of 5 product terms for logic, although the logic allocator allows for logic
redistribution. Each I/O pin has its own individual output enable term. The initialization product
terms provide asynchronous reset or preset to synchronous-mode macrocells in the PAL block.
The logic allocator also provides an exclusive-OR gate. This gate allows generation of
combinatorial exclusive-OR logic, such as comparison or addition. It allows registered exclusiveOR functions, such as CRC generation, to be implemented more efficiently. Emulating all flip-flop
types with a D-type flip-flop is also made possible. Register type emulation is automatically
handled by the design software.
Table 1 illustrates which product term clusters are available to each macrocell within a PAL block.
Refer to Figure 7 for cluster and macrocell numbers.
Table 1. Output Switch Matrix Combinations
Macrocell
M0, M1
Routable to I/O Pins
M2, M3
I/O0, I/O1,I/O2,I/O3,I/O4,I/O5,
M4, M5
I/O6,I/O7
M6, M7
M8, M9
M10, M11
I/O8,I/O9,I/O10,I/O11,I/O12,
M12, M13
I/O13,I /O14,I/O15
M14, M15
I/O Pin
I/O0
Available Macrocells
M0, M1, M2, M3, M4, M5, M6, M7
I/O1
M1, M2, M3, M4, M5, M6, M7, M0
I/O2
M2, M3, M4, M5, M6, M7, M0, M1
I/O3
M3, M4, M5, M6, M7, M0, M1, M2
I/O4
M4, M5, M6, M7 M0, M1, M2, M3
I/O5
M5, M6, M7, M0, M1, M2, M3, M4
I/O6
M6, M7, M0, M1, M2, M3, M4, M5
I/O7
M7, M0, M1, M2, M3, M4, M5, M6
I/O8
M8, M9, M10, M11, M12, M13, M14, M15
I/O9
M9, M10, M11, M12, M13, M14, M15, M8
I/O10
M10, M11, M12, M13, M14, M15, M8, M9
I/O11
M11, M12, M13, M14, M15, M8, M9, M10
I/O12
M12, M13, M14, M15, M8, M9, M10, M11
I/O13
M13, M14, M15, M8, M9, M10, M11, M12
I/O14
M14, M15, M8, M9, M10, M11, M12, M13
I/O15
M15, M8, M9, M10, M11, M12, M13, M14
MACH4-96/96-15
9
MACH 4 Family
The Logic Allocator
The logic allocator in the M4-96/96 takes the 80 logic product terms and allocates them to the 16
macrocells as needed. Each macrocell can be driven by up to 20 product terms in synchronous
mode, or 18 product terms in asynchronous mode. When product terms are routed away from a
macrocell, it is possible to redirect all 5 product terms away, which precludes the use of the
macrocell for logic generation. It is possible to route only 4 product terms; or it is possible to route
only 4 product terms away, leaving one for simple function generation. The design software
automatically configures the logic allocator when fitting the design into the device.
V A N T I S
The Macrocell and Output Switch Matrix
Each M4-96/96 PAL block has 16 macrocells, half of which can drive I/O pins; this selection is made by
the output switch matrix. Each macrocell can drive one of four I/O cells. The allowed combinations are
shown in Table 1. Please refer to Figure 7 for macrocell and I/O pin numbers.The macrocells can be
configured as registered, latched, or combinatorial. In combination with the logic allocator, the registered
configuration can be any of the standard flip-flop types. The macrocell provides internal feedback
whether configured with or without the flip-flop, and whether or not the macrocell drives an I/O cell.
The flip-flop clock depends on the mode selected for the macrocell. In synchronous mode, any of
the PAL block clocks generated by the Clock Generator can be used. In asynchronous mode, the
additional choice of either edge of an individual product-term clock is available.
Initialization can be handled as part of a bank of macrocells via the PAL block initialization terms if in
synchronous mode, or individually if in asynchronous mode (Figure 4). In synchronous mode, one of
the PAL block product terms is available each for preset and reset. The swap function determines which
product term drives which function. This allows initialization polarity compatibility with the MACH 1
and 2 series. In asynchronous mode, one product term can be used either to drive reset or preset.
Power-Up
Reset
PAL-Block
Initialization
Product Terms
SWAP
Common PAL-block resource
Individual macrocell resources
AP
D/T/L
From Logic Allocator
From
PAL-Clock
Generator
AR
Q
To Output and Input
Switch Matrices
Block CLK0
Block CLK1
Block CLK2
Block CLK3
a. Synchronous Mode
Power-Up
Reset
Individual
Initialization
Product Term
AP
AR
Q
D/T/L
From Logic
Allocator
From PAL-Block
Clock Generator
To Output and Input
Switch Matrices
Block CLK0
Block CLK1
Individual Clock
Product Term
b. Asynchronous Mode
21535A-4
Figure 4. Macrocell
10
MACH4-96/96-15
V A N T I S
The output switch matrix allows macrocells to be connected to any of several I/O cells within a
PAL block. This provides high flexibility in determining pinout, and allows design changes that will
not affect pinout.
In the MACH 4 devices, each PAL block has twice as many macrocells as I/O cells. The MACH 4
output switch matrix allows for half of the macrocells to drive I/O cells within a PAL block, in
combinations according to Figure 5. Each I/O cell can choose from eight macrocells; each
macrocell has a choice of four I/O cells.
Macrocell
I/O
cell
Macrocell
I/O
cell
Macrocell
I/O
cell
Macrocell
MACH 4 Family
Macrocell
I/O
Cell
MUX
I/O
cell
Macrocell
I/O
cell
Macrocell
I/O
cell
Macrocell
I/O
cell
Macrocell
a. Macrocell drives one of 3 I/Os
I/O
Cell
b. I/O can choose one of 8 macrocells
21535A-5
Figure 5.
MACH4-96/96 Output Switch Matrix
The I/O Cell
The I/O cell (Figure 6) in the M4-96/96 consists of a three-state buffer and an input flip-flop. The
I/O cell is driven by one of the macrocells, as selected by the output switch matrix. Each I/O cell
can take its input from one of eight macrocells. The three-state buffer is controlled by an individual
product term. The direct I/O signal is available to the input switch matrix, and can be used
if desired.
MACH4-96/96-15
11
V A N T I S
Individual
Output Enable
Product Term
From Output
Switch Matrix
To Input
Switch
Matrix
Q
D/L*
Block CLK0
Block CLK1
Block CLK2
Block CLK3
21535A-6
Figure 6. I/O Cell
SpeedLocking for Guaranteed Fixed Timing
The MACH 4 architecture allows allocation of up to 20 product terms to an individual macrocell
with the assistance of an XOR gate without incurring additional timing delays. Using this
architectural strength, the M4-96/96 provides the industry’s highest-speed and only fixed timing
at 5-V supply voltages. This SpeedLocking feature delivers guaranteed fixed speed independent
of logic path, routing resources, or design refits.
5-V In-System Programming
Another benefit of the JTAG circuitry is the ability to use the JTAG port for 5-V programming.
This allows the device to be soldered to the board before programming. Once the device is
attached, the delicate Plastic Quad Flat Pack, or PQFP, leads are protected from programming
and testing operations that could potentially damage them. Programming and verification of the
device is done serially which is ideal for on-board programming since it only requires the use
of the Test Access Port. There is an optional ENABLE pin which can be used to inhibit
programming for additional security. These devices can be programmed in any JTAG chain.
JTAG Boundary Scan Testing
JTAG is the commonly used acronym for the IEEE Standard 1149.1-1990. The JTAG standard
defines input and output pins, logic control functions, and instructions. Vantis has incorporated
this standard into the M4-96/96 device.
12
MACH4-96/96-15
16
CLK2/I3
CLK3/I4
CLK0/I0
CLK1/I1
V A N T I S
Clock
Generator
4
M0
M0
Macrocell
C1
M1
Macrocell
C2
M2
Macrocell
C3
M3
Macrocell
C4
M4
Macrocell
C5
M5
Macrocell
M6
Macrocell
M7
Macrocell
C8
M8
Macrocell
C9
M9
Macrocell
C10 M10
Macrocell
C11 M11
Macrocell
C12 M12
Macrocell
C13 M13
Macrocell
C14 M14
Macrocell
C15 M15
Macrocell
C7
O0
M1
O1
I/O
Cell
I/O
Cell
I/O0
I/O1
M2
O2
I/O
Cell
I/O2
M3
O3
I/O
Cell
I/O3
M4
O4
I/O
Cell
O5
I/O
Cell
O6
I/O
Cell
O7
I/O
Cell
O8
I/O
Cell
I/O8
O9
I/O
Cell
I/O9
I/O
Cell
I/O10
I/O
Cell
I/O11
I/O
Cell
I/O12
O13
I/O
Cell
I/O13
O14
I/O
Cell
I/O14
O15
I/O
Cell
I/O15
M5
M6
M7
Output Switch Matrix
C6
Logic Allocator
C0
M8
M9
M10 O10
M11
O11
M12 O12
M13
M14
M15
MACH 4 Family
Central Switch Matrix
0
I/O4
I/O5
I/O6
I/O7
97
17
16
24
Input
Switch
Matrix
16
Figure 7. M4-96/96 PAL Block
MACH4-96/96-15
13
V A N T I S
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . .
Ambient Temperature
with Power Applied . . . . . . .
Device Junction Temperature
Supply Voltage with
Respect to Ground . . . . . . . .
DC Input Voltage . . . . . . . . .
DC Output or
I/O Pin Voltage . . . . . . . . . . .
Static Discharge Voltage . . . .
Latchup Current
(TA = 0°C to +70°C) . . . . . . .
Commercial (C) Devices
. . . . . . .-65°C to +150°C
. . . . . . .-55°C to +125°C
. . . . . . . . . . . . . +150°C
. . . . . . -0.5 V to +7.0 V
. . . -0.5 V to VCC +0.5 V
Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage (VCC) with
Respect to Ground. . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
. . . -0.5 V to VCC +0.5 V
. . . . . . . . . . . . . 2001 V
. . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
DC CHARACTERISTICS over COMMERCIAL operating ranges
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = -3.2 mA, VCC = Min
VIN = VIH or VIL
VOL
Output LOW Voltage
IOL = 24 mA, VCC = Min
VIN = VIH or VIL (Note 1)
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 2)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for all
Inputs (Note 2)
0.8
V
IIH
Input HIGH Leakage
Current
VIN = 5.25 V, VCC = Max (Note 3)
10
µA
IIL
Input LOW Leakage
Current
VIN = 0 V, VCC = Max (Note 3)
-100
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 3)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 3)
-100
µA
ISC
Output Short-Circuit
Current
VOUT = 0.5 V, VCC = Max
(Note 4)
-160
mA
ICC
Supply Current
VIN = 0 V, Outputs Open
(IOUT = 0 mA), VCC = 5.0 V,
f =25 MHz, TA = 25°C (Note 5)
2.4
V
0.5
2.0
V
V
-30
225
mA
Notes:
1. Total IOL for one PAL block should not exceed 128 mA.
2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded,
enabled, and reset. An actual ICC value can be calculated by using the “Typical Dynamic ICC Characteristics” Chart towards the
end of this data sheet.
14
MACH4-96/96-15 (Com’l)
V A N T I S
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
Output Capacitance
VOUT = 2.0 V
Typ
Unit
6
pF
8
pF
VCC = 5.0 V, TA = 25°C,
f = 1 MHz
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
Parameter Symbol
Parameter Description
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 2)
tSA
Setup Time from Input, I/O, or Feedback to Product
Term Clock
tHA
tCOA
tWLA
Max
Unit
3
15
ns
D-type
8
ns
T-type
9
ns
Register Data Hold Time Using Product Term Clock
8
ns
Product Term Clock to Output (Note 2)
4
9
ns
HIGH
9
ns
Maximum
Frequency
Using Product
Term Clock
(Note 3)
External Feedback
1/(tSA+tCO)
D-type
38.5
MHz
T-type
37
MHz
Internal Feedback f(CNTA)
D-type
47.6
MHz
T-type
45.4
MHz
55.6
MHz
D-type
10
ns
T-type
11
ns
ns
tSS
Setup Time from Input, I/O, or Feedback to Global Clock
tHS
Register Data Hold Time Using Global Clock
0
tCOS
Global Clock to Output (Note 2)
2
10
ns
LOW
6
ns
HIGH
6
ns
D-type
50
MHz
T-type
47.6
MHz
D-type
66.6
MHz
T-type
62.5
MHz
83.3
MHz
Global Clock Width
tWHS
fMAXS
ns
LOW
No Feedback (Note 4) 1/(tWLA+tWHA)
tWLS
18
Product Term, Clock Width
tWHA
fMAXA
Min
Maximum
Frequency
Using Global
Clock (Note 3)
External
Feedback
1/(tSS + tCOS)
Internal Feedback (fCNTS)
No Feedback (Note4)
1/(tWLS + tWHS)
tSLA
Setup Time from Input, I/O, or Feedback to Product Term Clock
8
ns
tHLA
Latch Data Hold Time Using Product Term Clock
8
ns
tGOA
Product Term Gate to Output (Note 2)
MACH4-96/96-15 (Com’l)
19
ns
15
MACH 4 Family
-15
V A N T I S
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (Continued)
-15
Parameter Symbol
Parameter Description
Min
Max
Unit
tGWA
Product Term Gate Width LOW (for LOW transparent) or HIGH (for
HIGH transparent)
9
ns
tSLS
Setup Time from Input, I/O, or Feedback to Global Gate
10
ns
tHLS
Latch Data Hold Time Using Global Gate
0
ns
tGOS
Gate to Output (Note 2)
tGWS
Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH
transparent)
tPDL
Input, I/O or Feedback to Output through Transparent Output Latch
17
ns
tAR
Asynchronous Reset to Registered or Latched Output
20
ns
11
6
ns
ns
tARW
Asynchronous Reset Width (Note 3)
15
ns
tARR
Asynchronous Reset Recovery Time (Note 3)
15
ns
tAP
Asynchronous Preset to Registered or Latched Output
20
ns
tAPW
Asynchronous Preset Width (Note 3)
15
ns
tAPR
Asynchronous Preset Recovery Time (Note 3)
15
ns
tEA
Input, I/O, or Feedback to Output Enable (Note 2)
2
15
ns
tER
Input, I/O, or Feedback to Output Disable (Note 2
2
15
ns
Notes:
1. See Switching Test Circuit at the end of this Data Book for test conditions.
2. Parameters measured with 32 outputs switching.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
frequency may be affected.
4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
16
MACH4-96/96-15 (Com’l)
V A N T I S
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . .
Ambient Temperature
with Power Applied . . . . . . .
Device Junction Temperature
Supply Voltage with
Respect to Ground . . . . . . . .
DC Input Voltage . . . . . . . . .
DC Output or
I/O Pin Voltage . . . . . . . . . . .
Static Discharge Voltage . . . .
Latchup Current
(TA = –40°C to +85°C) . . . . . .
Industrial (I) Devices
. . . . . . .-65°C to +150°C
. . . . . . .-55°C to +125°C
. . . . . . . . . . . . . +150°C
. . . . . . -0.5 V to +7.0 V
. . . -0.5 V to VCC +0.5 V
Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltage (VCC) with
Respect to Ground. . . . . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
MACH 4 Family
. . . -0.5 V to VCC +0.5 V
. . . . . . . . . . . . . 2001 V
. . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
DC CHARACTERISTICS over COMMERCIAL operating ranges
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
VOH
Output HIGH Voltage
IOH = -3.2 mA, VCC = Min
VIN = VIH or VIL
VOL
Output LOW Voltage
IOL = 24 mA, VCC = Min
VIN = VIH or VIL (Note 1)
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 2)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for all
Inputs (Note 2)
0.8
V
IIH
Input HIGH Leakage
Current
VIN = 5.25 V, VCC = Max (Note 3)
10
µA
IIL
Input LOW Leakage
Current
VIN = 0 V, VCC = Max (Note 3)
-100
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 3)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 3)
-100
µA
ISC
Output Short-Circuit
Current
VOUT = 0.5 V, VCC = Max
(Note 4)
-160
mA
ICC
Supply Current
VIN = 0 V, Outputs Open
(IOUT = 0 mA), VCC = 5.0 V,
f =25 MHz, TA = 25°C (Note 5)
2.4
V
0.5
2.0
V
V
-30
225
mA
Notes:
1. Total IOL for one PAL block should not exceed 128 mA.
2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded,
enabled, and reset. An actual ICC value can be calculated by using the “Typical Dynamic ICC Characteristics” Chart towards the
end of this data sheet.
MACH4-96/96-18 (Ind)
17
V A N T I S
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Input Capacitance
VIN = 2.0 V
Output Capacitance
VOUT = 2.0 V
Typ
Unit
6
pF
8
pF
VCC = 5.0 V, TA = 25°C,
f = 1 MHz
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
-18
Parameter Symbol
Parameter Description
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 2)
tSA
Setup Time from Input, I/O, or Feedback to Product
Term Clock
tHA
tCOA
tWLA
Unit
3
18
ns
10
ns
T-type
11
ns
Register Data Hold Time Using Product Term Clock
10
ns
Product Term Clock to Output (Note 2)
4
10
ns
HIGH
10
ns
Maximum
Frequency
Using Product
Term Clock
(Note 3)
External Feedback
1/(tSA+tCO)
D-type
33.3
MHz
T-type
33.2
MHz
Internal Feedback f(CNTA)
D-type
35.7
MHz
T-type
34.4
MHz
50.0
MHz
D-type
12
ns
T-type
13
ns
ns
Setup Time from Input, I/O, or Feedback to Global Clock
tHS
Register Data Hold Time Using Global Clock
0
tCOS
Global Clock to Output (Note 2)
2
12
ns
LOW
7
ns
HIGH
7
ns
D-type
41.7
MHz
T-type
40.0
MHz
D-type
58.8
MHz
T-type
55.5
MHz
71.4
MHz
Global Clock Width
tWHS
fMAXS
ns
LOW
tSS
tWLS
20
Product Term, Clock Width
No Feedback (Note 4) 1/(tWLA+tWHA)
Maximum
Frequency
Using Global
Clock (Note 3)
External
Feedback
1/(tSS + tCOS)
Internal Feedback (fCNTS)
No Feedback (Note4)
18
Max
D-type
tWHA
fMAXA
Min
1/(tWLS + tWHS)
tSLA
Setup Time from Input, I/O, or Feedback to Product Term Clock
10
ns
tHLA
Latch Data Hold Time Using Product Term Clock
10
ns
tGOA
Product Term Gate to Output (Note 2)
MACH4-96/96-18 (Ind)
22
ns
V A N T I S
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (Continued)
-18
Parameter Symbol
Parameter Description
Min
Max
Unit
tGWA
Product Term Gate Width LOW (for LOW transparent) or HIGH (for
HIGH transparent)
11
ns
tSLS
Setup Time from Input, I/O, or Feedback to Global Gate
12
ns
tHLS
Latch Data Hold Time Using Global Gate
0
ns
tGOS
Gate to Output (Note 2)
tGWS
Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH
transparent)
tPDL
Input, I/O or Feedback to Output through Transparent Output Latch
20
ns
tAR
Asynchronous Reset to Registered or Latched Output
22
ns
12
ns
tARW
Asynchronous Reset Width (Note 3)
17
ns
tARR
Asynchronous Reset Recovery Time (Note 3)
17
ns
tAP
Asynchronous Preset to Registered or Latched Output
22
MACH 4 Family
7
ns
ns
tAPW
Asynchronous Preset Width (Note 3)
17
ns
tAPR
Asynchronous Preset Recovery Time (Note 3)
17
ns
tEA
Input, I/O, or Feedback to Output Enable (Note 2)
2
17
ns
tER
Input, I/O, or Feedback to Output Disable (Note 2
2
17
ns
Notes:
1. See Switching Test Circuit at the end of this Data Book for test conditions.
2. Parameters measured with 32 outputs switching.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
frequency may be affected.
4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
MACH4-96/96-18 (Ind)
19
V A N T I S
TYPICAL CURRENT vs. VOLTAGE (I-V) CHARACTERISTICS
VCC = 5.0 V, TA = 25°C
IOL (mA)
80
60
40
20
–1.0 –0.8 –0.6 –0.4 –0.2
–20
0.2 0.4
0.6
0.8 1.0
VOL (V)
–40
–60
–80
Output, LOW
21535A-7
IOH (mA)
25
1
–3
–2
2
3
4
5
VOH (V)
–1
–25
–50
–75
–100
–125
–150
Output, HIGH
21535A-8
II (mA)
20
VI (V)
–2
–1
–20
1
2
3
4
5
–40
–60
–80
–100
Input
20
MACH4-96/96-15
21535A-9
V A N T I S
TYPICAL ICC CHARACTERISTICS
VCC = 5 V, TA = 25°C
400
350
MACH 4 Family
300
ICC (mA)
250
200
150
100
50
0
0
10
20
30
40
50
60
70
80
90
Frequency (MHz)
21535A-10
The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.
Maximum frequency shown uses internal feedback and a D-type register.
MACH4-96/96-15
21
V A N T I S
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Typ
Parameter
Symbol
Parameter Description
θjc
Thermal impedance, junction to case
θja
Thermal impedance, junction to ambient
θjma
Thermal impedance, junction to ambient air flow
PQFP
Unit
7
°C /W
25
°C /W
200 lfpm air
21
°C /W
400 lfpm air
18
°C /W
600 lfpm air
16
°C /W
800 lfpm air
15
°C /W
Plastic θ jc Considerations
The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment.
SWITCHING WAVEFORMS
Input, I/O, or
Feedback
VT
tPD
Combinatorial
Output
VT
21535A-11
Combinatorial Output
Input, I/O, or
Feedback
Input, I/O, or
Feedback
VT
tS
tH
tSL
tCO
Registered
Output
tHL
Gate
VT
Clock
VT
VT
tPDL
VT
tGO
Latched
Out
VT
21535A-12
Registered Output
Latched Output
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
22
21535A-13
MACH4-96/96-15
V A N T I S
SWITCHING WAVEFORMS
tWH
Gate
Clock
VT
tGWS
tWL
21535A-14
21535A-15
Clock Width
Gate Width
Registered
Input
VT
tSIR
Input
Register
Clock
VT
tHIR
Input
Register
Clock
VT
tICO
Combinatorial
Output
MACH 4 Family
Registered
Input
VT
VT
Output
Register
Clock
tICS
21535A-16
VT
21535A-17
Registered Input
Input Register to Output Register Setup
Latched
In
VT
tSIL
tHIL
VT
Gate
tIGO
Combinatorial
Output
VT
21535A-18
Latched Input
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
MACH4-96/96-15
23
V A N T I S
SWITCHING WAVEFORMS
tPDLL
Latched
In
VT
Latched
Out
VT
tIGOL
Input
Latch Gate
tSLL
tIGS
VT
Output
Latch Gate
21535A-19
Latched Input and Output
tWICH
Clock
VT
tWICL
Input
Latch
Gate
VT
tWIGL
21535A-20
Input Register Clock Width
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
24
21535A-21
Input Latch Gate Width
MACH4-96/96-15
V A N T I S
SWITCHING WAVEFORMS
tARW
tAPW
Input, I/O, or
Feedback
Input, I/O,
or Feedback
VT
VT
tAP
tAR
Registered
Output
Registered
Output
VT
VT
tAPR
VT
Clock
VT
Clock
21535A-22
21535A-23
Asynchronous Reset
Asynchronous Preset
Input, I/O, or
Feedback
VT
tER
Outputs
tEA
VOH – 0.5 V
VOL + 0.5 V
VT
21535A-24
Output Disable/Enable
Notes:
1. VT = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
MACH4-96/96-15
25
MACH 4 Family
tARR
V A N T I S
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
VCC
S1
R1
Output
Test Point
R2
CL
21535A-25
Commercial
Specification
tPD, tCO
tEA
tER
S1
CL
R1
R2
300 Ω
390 Ω
Closed
Z → H: Open
35 pF
Z → L: Closed
H → Z: Open
L → Z: Closed
5 pF
* Switching several outputs simultaneously should be avoided for accurate measurement.
26
Measured Output Value
MACH4-96/96-15
1.5 V
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
V A N T I S
fMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate.
Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop
designs, fMAX is specified for three types of synchronous designs.
The first type of design is a state machine with feedback signals sent off-chip. This external feedback
could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest
path defining the period is the sum of the clock-to-output time and the input setup time for the
external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback
or in conjunction with an equivalent speed device. This fMAX is designated “fMAX external.”
The third type of design is a simple data path application. In this case, input data is presented to
the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is
limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit
for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum
clock period determines the period for the third fMAX, designated “fMAX no feedback.”
For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this
involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period
will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock
widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is
specified as 1/(tWICL + tWICH). Note that if both input and output registers are used in the same
path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are
calculated from other measured AC parameters. fMAX internal is measured directly.
CLK
CLK
(SECOND
CHIP)
LOGIC
tS
REGISTER
LOGIC
tCO
tS
fMAX Internal (fCNT)
fMAX External 1/(ts + tCO)
CLK
LOGIC
REGISTER
CLK
REGISTER
REGISTER
tS
fMAX No Feedback; 1/(ts + tH) or 1/(tWH + tWL)
LOGIC
tHIR
tSIR
fMAXIR; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
21535A-26
MACH4-96/96-15
27
MACH 4 Family
The second type of design is a single-chip state machine with internal feedback only. In this case,
flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the
period is limited by the internal delay from the flip-flop outputs through the internal feedback and
logic to the flip-flop inputs. This fMAX is designated “fMAX internal”. A simple internal counter is a
good example of this type of design; therefore, this parameter is sometimes called “fCNT.”
V A N T I S
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using Vantis’ advanced Electrically Erasable process. This
technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device
can be erased and reprogrammed, a feature which allows 100% testing at the factory.
Endurance Characteristics
Parameter
Symbol
tDR
Parameter Description
Units
Test Conditions
10
Years
Max Storage Temperature
20
Years
Max Operating Temperature
100
Cycles
Normal Programming Conditions
Min Pattern Data Retention Time
N
Max Reprogramming Cycles
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up.
Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic
polarity. This feature provides extra flexibility to the designer and is especially valuable in
simplifying state machine initialization. A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise
to its steady state, two conditions are required to insure a valid power-up reset. These conditions
are:
1. The VCC rise must be monotonic.
2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter Symbol
Parameter Descriptions
tPR
Power-Up Reset Time
tS
Input or Feedback Setup Time
tWL
Max
Unit
10
µs
See Switching Characteristics
Clock Width LOW
VCC
Power
4V
tPR
Registered
Output
tS
Clock
tWL
21535A-27
Power-Up Reset Waveform
28
MACH4-96/96-15
V A N T I S
DEVELOPMENT SYSTEMS (subject to change)
For more information on the products listed below, please consult the local Vantis sales office.
MANUFACTURER
SOFTWARE DEVELOPMENT SYSTEMS
Vantis Corporation
P.O. Box 3755
920 DeGuigne Drive
Sunnyvale, CA 94088
(408) 732-0555 or 1(888) 826-8472 (VANTIS2)
http://www.vantis.com
MACHXL Software
Vantis-ABEL Software
Vantis-Synario Software
ACTIVE-CAD
Cadence Design Systems
555 River Oaks Pkwy
San Jose, CA 95134
(408) 943-1234 or (800) 746-6223
PIC Designer
Concept/Composer
Synergy
Leapfrog/Verilog-XL
Exemplar Logic, Inc.
815 Atlantic Avenue, Suite 105
Alameda, CA 94501
(510) 337-3700
Leonardo™
Galileo™
Logic Modeling
19500 NW Gibbs Dr.
P.O. Box 310
Beaverton, OR 97075
(800) 346-6335
Mentor Graphics Corp.
8005 S.W. Boeckman Rd.
Wilsonville, OR 97070-7777
(800) 547-3000 or (503) 685-7000
MACH 4 Family
Aldec, Inc.
3 Sunset Way, Suite F
Henderson, NV 89014
(702) 456-1222 or (800) 487-8743
SmartModel® Library
Design Architect, PLDSynthesis™ II
Autologic II Synthesizer, QuickSim Simulator, QuickHDL Simulator
MicroSim Corp.
20 Fairbanks
Irvine, CA 92718
(714) 770-3022
MicroSim Design Lab
PLogic, PLSyn
MINC Inc.
6755 Earl Drive, Suite 200
Colorado Springs, CO 80918
(800) 755-FPGA or (719) 590-1155
PLDesigner-XL™ Software
Model Technology
8905 S.W. Nimbus Avenue, Suite 150
Beaverton, OR 97008
(503) 641-1340
V-System/VHDL
OrCAD, Inc.
9300 S.W. Nimbus Avenue
Beaverton, OR 97008
(503) 671-9500 or (800) 671-9505
OrCAD Express
Synario® Design Automation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
(800) 332-8246 or (206) 881-6444
ABEL™
Synario™ Software
MACH4-96/96-15
29
V A N T I S
MANUFACTURER
SOFTWARE DEVELOPMENT SYSTEMS
Synopsys
700 E. Middlefield Rd.
Mountain View, CA 94040
(415) 962-5000 or (800) 388-9125
FPGA or Design Compiler
(Requires MINC PLDesigner-XL™)
VSS Simulator
Synplicity, Inc.
624 East Evelyn Ave.
Sunnyvale, CA 94086
(408) 617-6000
Synplify
Teradyne EDA
321 Harrison Ave.
Boston, MA 02118
(800) 777-2432 or (617) 422-2793
MultiSIM Interactive Simulator
LASAR
VeriBest, Inc.
6101 Lookout Road, Suite A
Boulder, CO 80301
(800) 837-4237
Viewlogic Systems, Inc.
293 Boston Post Road West
Marlboro, MA 01752
(800) 873-8439 or (508) 480-0881
VeriBest PLD
Viewdraw, ViewPLD, Viewsynthesis
Speedwave Simulator, ViewSim Simulator, VCS Simulator
MANUFACTURER
TEST GENERATION SYSTEM
Acugen Software, Inc.
427-3 Amherst St., Suite 391
Nashua, NH 03063
(603) 881-8821
ATGEN™ Test Generation Software
iNt GmbH
Busenstrasse 6
D-8033 Martinsried, Munich, Germany
(87) 857-6667
PLDCheck 90
Vantis is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor an endorsement by Vantis of these products.
30
MACH4-96/96-15
V A N T I S
APPROVED PROGRAMMERS (subject to change)
For more information on the products listed below, please consult the local Vantis sales office.
MANUFACTURER
PROGRAMMER CONFIGURATION
Advin Systems, Inc.
1050-L East Duane Ave.
Sunnyvale, CA 940 86
(408) 243-7000 or (800) 627-2456
BBS (408) 737-9200
Fax (408) 736-2503
Data I/O Corporation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
(800) 426-1045 or (206) 881-6444
BBS (206) 882-3211
Fax (206) 882-1043
BP1200
UniSite™
Hi-Lo Systems
4F, No. 2, Sec. 5, Ming Shoh E. Road
Taipei, Taiwan
(886) 2-764-0215
Fax (886) 2-756-6403
or
Tribal Microsystems / Hi-Lo Systems
44388 South Grimmer Blvd.
Fremont, CA 94538
(510) 623-8859
BBS (510) 623-0430
Fax (510) 623-9925
SMS GmbH
Im Grund 15
88239 Wangen
Germany
(49) 7522-97280
Fax (49) 7522-972850
or
SMS USA
544 Weddell Dr. Suite 12
Sunnyvale, CA 94089
(408) 542-0388
Pilot-U84
BP1400
Model 2900
ALL-07
Sprint Expert
Stag House
Silver Court Watchmead, Welwyn Garden City
Herfordshire UK AL7 1LT
44-1-707-332148
Fax 44-1-707-371503
MVP
BP2100
MACH 4 Family
BP Microsystems
1000 N. Post Oak Rd., Suite 225
Houston, TX 77055-7237
(800) 225-2102 or (713) 688-4600
BBS (713) 688-9283
Fax (713) 688-0920
Pilot-U40
BP2200
Model 3900
AutoSite
FLEX-700
Sprint Optima
Multisite
Stag Quazar
MACH4-96/96-15
31
V A N T I S
MANUFACTURER
PROGRAMMER CONFIGURATION
System General
1603A South Main Street
Milpitas, CA 95035
(408) 263-6667
BBS (408) 262-6438
Fax (408) 262-9220
or
3F, No. 1, Alley 8, Lane 45
Bao Shing Road, Shin Diau
Taipei, Taiwan
(886) 2-917-3005
Fax (886) 2-911-1283
Turpro-1
Turpro-1/FX
Turpro-1/TX
APPROVED ADAPTER MANUFACTURERS
MANUFACTURER
PROGRAMMER CONFIGURATION
California Integration Coordinators, Inc.
656 Main Street
Placerville, CA 95667
(916) 626-6168
Fax (916) 626-7740
MACH/PAL Programming Adapters
Emulation Technology, Inc.
2344 Walsh Ave., Bldg. F
Santa Clara, CA 95051
(408) 982-0660
Fax (408) 982-0664
Adapt-A-Socket®
Programming Adapters
APPROVED ON-BOARD ISP PROGRAMMING TOOLS
MANUFACTURER
PROGRAMMER CONFIGURATION
Corelis, Inc.
12607 Hidden Creek Way, Suite H
Cerritos, California 70703
(310) 926-6727
JTAGPROG™
Vantis Corporation
P.O. Box 3755
920 DeGuigne Drive
Sunnyvale, CA 94088
(408) 732-0555 or 1(888) 826-8472 (VANTIS2)
http://www.vantis.com
MACHPRO®
32
MACH4-96/96-15
V A N T I S
PHYSICAL DIMENSIONS
PQR144
144-Pin Plastic Quad Flat Pack; Trimmed and Formed (measured in millimeters)
Pin 144
22.75
REF
27.90
28.10
31.00
31.40
Pin 108
MACH 4 Family
Pin 1 I.D.
22.75
REF
27.90
28.10
31.00
31.40
Pin 36
Pin 72
3.20
3.60
0.65 BASIC
0.25
MIN
3.95
MAX
SEATING PLANE
16-038-PQR-1_AH
PQR144
DP92
9-3-96 lv
Trademarks
Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved.
AMD, Vantis, the Vantis logo and combinations thereof, SpeedLocking and Bus-Friendly are trademarks, MACH, MACHXL, MACHPRO and PAL
are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
MACH4-96/96-15
33