FINAL COM’L: -10/12/15/20 IND: -14/18/24 Advanced Micro Devices MACH220-10/12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 68 Pins 48 Outputs 96 Macrocells 96 Flip-flops; 4 clock choices 10 ns tPD 8 “PAL26V12” blocks with buried macrocells 100 MHz fCNT Pin-compatible with MACH120 and MACH221 56 Inputs with pull-up resistors GENERAL DESCRIPTION The MACH220 is a member of AMD’s high-performance EE CMOS MACH 2 device family. This device has approximately nine times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH220 consists of eight PAL blocks interconnected by a programmable switch matrix. The eight PAL blocks are essentially “PAL26V12” structures complete with product-term arrays, and programmable macrocells, including buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACH220 has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers for use in synchronizing signals and reducing setup time requirements. The MACH220 has two kinds of macrocell: output and buried. The output macrocell provides registered, latched, or combinatorial outputs with programmable BLOCK DIAGRAM If you would like to view Block Diagram in full size, please click on the box. Publication# 14130 Rev. I Issue Date: May 1995 Amendment /0 I2 – I3, I/O6 – I/O11 I/O0 – I/O5 6 I/O Cells 6 I/O Cells 6 6 Macrocells I/O Cells 6 6 Macrocells I6 – I7 6 6 6 Macrocells I/O18– I/O23 I/O12 – I/O17 6 I/O Cells 6 6 Macrocells Macrocells 6 6 6 Macrocells 6 Macrocells Macrocells OE OE OE OE 52 x 52 AND Logic Array and Logic Allocator 52 x 52 AND Logic Array and Logic Allocator 52 x 52 AND Logic Array and Logic Allocator 52 x 52 AND Logic Array and Logic Allocator 26 26 26 26 26 26 4 4 Switch Matrix 26 26 52 x 52 AND Logic Array and Logic Allocator 52 x 52 AND Logic Array and Logic Allocator OE OE Macrocells 6 6 6 6 Macrocells 6 I/O Cells 6 6 6 Macrocells 6 I/O Cells Macrocells 6 6 4 Macrocells 6 6 I/O Cells 6 I/O30 – I/O35 4 OE Macrocells 6 I/O36 – I/O41 52 x 52 AND Logic Array and Logic Allocator OE Macrocells Macrocells I/O Cells I/O42 – I/O47 52 x 52 AND Logic Array and Logic Allocator 6 I/O24 – I/O29 CLK0/I0, CLK1/I1 CLK2/I4 , CLK3/I5 14130I-1 AMD CONNECTION DIAGRAMS Top View 6 5 4 3 I/O42 GND I/O44 I/O43 I/O45 VCC I/O47 I/O46 GND 7 8 I/O0 I/O5 I/O4 I/O3 9 I/O2 I/O1 I/O6 GND PLCC 2 1 68 67 66 65 64 63 62 61 I/O7 I/O8 10 I/O9 I/O10 I/O11 CLK0/I0 12 CLK1/I1 I2 VCC 16 17 18 54 GND I3 I/O12 I/O13 19 51 20 50 21 22 23 24 49 14 15 52 I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I7 GND VCC I6 48 47 CLK3/I5 CLK2/I4 I/O35 I/O34 46 45 44 I/O33 I/O32 I/O31 GND I/O30 I/O28 I/O29 I/O26 I/O27 I/O24 I/O25 GND VCC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O21 I/O22 I/O23 25 26 53 GND I/O18 I/O17 13 I/O19 I/O20 I/O14 I/O15 I/O16 60 59 58 57 56 55 11 14130D-001A 14130I-2 Note: Pin-compatible with MACH120 and MACH221. PIN DESIGNATIONS CLK/I = GND = I = I/O = VCC Clock or Input Ground Input Input/Output = Supply Voltage MACH220-10/12/15/20 3 AMD ORDERING INFORMATION Commercial Products AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 220 -10 J C FAMILY TYPE MACH = Macro Array CMOS High-Speed OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial (0°C to +70°C) DEVICE NUMBER 220 = 96 Macrocells, 68 Pins SPEED -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD PACKAGE TYPE J = 68-Pin Plastic Leaded Chip Carrier (PL 068) Valid Combinations MACH220-10 MACH220-12 MACH220-15 MACH220-20 4 JC Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH220-10/12/15/20 (Com’l) AMD ORDERING INFORMATION Industrial Products AMD programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 220 -14 J FAMILY TYPE MACH = Macro Array CMOS High-Speed OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS I = Industrial (–40°C to +85°C) DEVICE NUMBER 220 = 96 Macrocells, 68 Pins SPEED -14 = 14.5 ns tPD -18 = 18 ns tPD -24 = 24 ns tPD PACKAGE TYPE J = 68-Pin Plastic Leaded Chip Carrier (PL 068) Valid Combinations MACH220-14 MACH220-18 MACH220-24 I JI Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH220-14/18/24 (Ind) 5 AMD Table 1. Logic Allocation FUNCTIONAL DESCRIPTION The MACH220 consists of eight PAL blocks connected by a switch matrix. There are 48 I/O pins and 4 dedicated input pins feeding the switch matrix. These signals are distributed to the four PAL blocks for efficient design implementation. There are 4 clock pins that can also be used as dedicated inputs. All inputs and I/O pins have built-in pull-up resistors. While it is always good design practice to tie unused pins high or low, the pull-up resistors provide design security and stability in the event that unused pins are left disconnected. The PAL Blocks In addition to the logic product terms, two output enable product terms, an asynchronous reset product term, and an asynchronous preset product term are provided. One of the two output enable product terms can be chosen within each I/O cell in the PAL block. All flip-flops within the PAL block are initialized together. The Switch Matrix The MACH220 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 12 internal feedback signals and 6 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that also provides for high performance. The design software automatically configures the switch matrix when fitting a design into the device. The Product-Term Array The MACH220 product-term array consists of 48 product terms for logic use, and 4 special-purpose product terms. Two of the special-purpose product terms provide programmable output enable, one provides asynchronous reset, and one provides asynchronous preset. The Logic Allocator The logic allocator in the MACH220 takes the 48 logic product terms and allocates them to the 12 macrocells as needed. Each macrocell can be driven by up to 16 product terms. The design software automatically configures the logic allocator when fitting the design into the device. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. Available Clusters M1 C0, C1, C2 C0, C1, C2, C3 M3 C1, C2, C3, C4 C2, C3, C4, C5 M5 C3, C4, C5, C6 C4, C5, C6, C7 M7 C5, C6, C7, C8 C6, C7, C8, C9 M9 C7, C8, C9, C10 C8, C9, C10, C11 M11 C9, C10, C11 C10, C11 M0 M2 M4 M6 M8 M10 Each PAL block in the MACH220 (Figure 1) contains a 48-product-term logic array, a logic allocator, 6 output macrocells, 6 buried macrocells, and 6 I/O cells. The switch matrix feeds each PAL block with 26 inputs. This makes the PAL block look effectively like an independent “PAL26V12” with 6 buried macrocells. 6 Macrocell Output Buried The Macrocell The MACH220 has two types of macrocell: output and buried. The output macrocells can be configured as either registered, latched, or combinatorial, with programmable polarity. The macrocell provides internal feedback whether configured with or without the flipflop. The registers can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of four clock/gate pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The latch holds its data when the gate input is HIGH, and is transparent when the gate input is LOW. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The buried macrocells are the same as the output macrocells if they are used for generating logic. In that case, the only thing that distinguishes them from the output macrocells is the fact that there is no I/O cell connection, and the signal is only used internally. The buried macrocell can also be configured as an input register or latch. The I/O Cell The I/O cell in the MACH220 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to all I/O cells in a PAL block. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. MACH220-10/12/15/20 AMD 0 4 8 12 16 20 24 28 32 36 40 43 47 51 Output Enable Output Enable Asynchronous Reset Asynchronous Preset Output Macro Cell M0 I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O Buried Macro Cell M1 Output Macro Cell M2 0 I/O Cell C0 C1 Buried Macro Cell M3 C2 C3 M4 C5 C6 C7 C8 Logic Allocator C4 Switch Matrix Output Macro Cell Buried Macro Cell M5 Output Macro Cell M6 C9 C10 Buried Macro Cell M7 C11 47 4 8 12 16 20 24 28 32 36 40 43 47 Output Macro Cell M9 Buried Macro Cell M10 Output Macro Cell M11 Buried Macro Cell 51 CLK 0 M8 4 12 6 14130I-3 Figure 1. MACH220 PAL Block MACH220-10/12/15/20 7 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +70°C) . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –130 mA ICC Supply Current (Typical) VCC = 5 V, TA = 25°C, f = 25 MHz (Note 4) 205 V 0.5 2.0 V V mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. 8 MACH220-10 (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol tPD -10 Parameter Description Min Input, I/O, or Feedback to Combinatorial Output tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output tWL tWH Clock Width fMAX 10 Internal Feedback (fCNT) Unit ns D-type 6.5 ns T-type 7.5 ns 0 ns 6.0 External Feedback Maximum Frequency (Note 1) Max ns LOW HIGH 4 4 ns ns D-type 80 MHz T-type 74 MHz D-type 100 MHz T-type No Feedback 91 MHz 125 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 7 ns tHL Latch Data Hold Time 0 ns tGO Gate to Output tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch tSIR Input Register Setup Time 2 ns tHIR Input Register Hold Time 2 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup 7.5 4 tWICL tWICH Input Register Clock Width fMAXIR Maximum Input Register Frequency ns ns 14 15 ns ns D-type 11 ns T-type 12 ns LOW HIGH 4 4 ns ns 125 MHz tSIL Input Latch Setup Time 2 ns tHIL Input Latch Hold Time 2 ns tIGO Input Latch Gate to Combinatorial Output 17 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 18 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 10 ns tIGS Input Latch Gate to Output Latch Setup 11 ns MACH220-10 (Com’l) 9 AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol -10 Parameter Description Min tWIGL Input Latch Gate Width LOW tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Max 4 Unit ns 16 15 ns tAR Asynchronous Reset to Registered or Latched Output tARW Asynchronous Reset Width (Note 1) 10 ns tARR Asynchronous Reset Recovery Time (Note 1) 8 ns 15 ns tAP Asynchronous Preset to Registered or Latched Output tAPW Asynchronous Preset Width (Note 1) 10 ns ns tAPR Asynchronous Preset Recovery Time (Note 1) 8 ns tEA Input, I/O, or Feedback to Output Enable 10 ns tER Input, I/O, or Feedback to Output Disable 10 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 10 MACH220-10 (Com’l) AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . 65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +70°C) . . . . . . . . . . . . . . . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 ICC Supply Current (Typical) VCC = 5 V, TA = 25°C, f = 25 MHz (Note 4) 205 Max Unit V 0.5 2.0 V V 0.8 V 10 µA –100 µA 10 µA –100 µA –130 mA mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. MACH220-12/15/20 (Com’l) 11 AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) -12 Min Max Parameter Symbol Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output (Note 3) tWL tWH 1/(tS + tCO) External Feedback fMAX Internal Feedback (fCNT) No Feedback 12 -20 Min Max 15 20 Unit ns D-type 7 10 13 ns T-type 8 11 14 ns 0 0 0 ns 10 12 ns LOW 6 6 8 ns HIGH 6 6 8 ns D-type 66.7 50 40 MHz T-type 62.5 47.6 38.5 MHz D-type 83.3 66.6 50 MHz T-type 76.9 62.5 47.6 MHz 83.3 83.3 62.5 MHz 1/(tWL + tWH) tSL Setup Time from Input, I/O, or Feedback to Gate 7 10 13 ns tHL Latch Data Hold Time 0 0 0 ns tGO Gate to Output (Note 3) tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 10 6 11 6 14 12 8 17 ns ns 22 ns tSIR Input Register Setup Time 2 2 2 ns tHIR Input Register Hold Time 2 2.5 3 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup tWICL Input Register Clock Width tWICH fMAXIR Maximum Input Register Frequency 15 18 23 ns D-type 12 15 20 ns T-type 13 16 21 ns LOW 6 6 8 ns HIGH 6 6 8 ns 83.3 83.3 62.5 MHz 1/(tWICL + tWICH) tSIL Input Latch Setup Time 2 2 2 ns tHIL Input Latch Hold Time 2 2.5 3 ns tIGO Input Latch Gate to Combinatorial Output 17 20 25 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 19 22 27 ns tSLL tIGS 12 -15 Max 8 Clock Width Maximum Frequency (Note 1) Min Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 9 12 15 ns Input Latch Gate to Output Latch Setup 13 16 21 ns MACH220-12/15/20 (Com’l) AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) -12 Min Max Parameter Symbol Parameter Description -15 Min Max -20 Min Max Unit tWIGL Input Latch Gate Width LOW tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 16 19 24 ns tAR Asynchronous Reset to Registered or Latched Output 16 20 25 ns 6 6 8 ns tARW Asynchronous Reset Width (Note 1) 12 15 20 ns tARR Asynchronous Reset Recovery Time (Note 1) 8 10 15 ns tAP Asynchronous Preset to Registered or Latched Output 16 20 25 ns tAPW Asynchronous Preset Width (Note 1) 12 15 20 ns tAPR Asynchronous Preset Recovery Time (Note 1) 8 10 15 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 12 15 20 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 12 15 20 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit for test conditions. 3. Parameters measured with 24 outputs switching. MACH220-12/15/20 (Com’l) 13 AMD ABSOLUTE MAXIMUM RATINGS INDUSTRIAL OPERATING RANGES Storage Temperature . . . . . . . . . . . . 65°C to +150°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . –40°C to +85°C Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . . . +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = –40°C to +85°C) . . . . . . . . . . . . . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) ICC Supply Current (Typical) VCC = 5 V, TA = 25°C, f = 25 MHz (Note 4) Typ Max Unit V 0.5 2.0 V V 0.8 –30 205 V 10 µA –100 µA 10 µA –100 µA –130 mA mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. 14 MACH220-14/18/24 (Ind) AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) -14 Min Max Parameter Symbol Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output (Note 3) tWL tWH 1/(tS + tCO) External Feedback fMAX Internal Feedback (fCNT) No Feedback -18 Max 14.5 -24 Min Max 18 24 Unit ns D-type 8.5 12 16 ns T-type 10 13.5 17 ns 0 0 0 ns 10 Clock Width Maximum Frequency (Note 1) Min 12 14.5 ns LOW 7.5 7.5 10 ns HIGH 7.5 7.5 10 ns D-type 53 40 32 MHz T-type 50 38 30.5 MHz D-type 61.5 53 38 MHz T-type 57 44 34.5 MHz 66.5 66.5 50 MHz 8.5 12 16 ns 0 0 0 ns 1/(tWL + tWH) tSL Setup Time from Input, I/O, or Feedback to Gate tHL Latch Data Hold Time tGO Gate to Output (Note 3) tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch tSIR Input Register Setup Time 2.5 2.5 2.5 ns tHIR Input Register Hold Time 3 3.5 4 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup 12 7.5 fMAXIR 17 10 20.5 18 ns 26.5 22 ns 28 ns ns 14.5 18 24 ns T-type 16 19.5 25.5 ns LOW 7.5 7.5 10 ns HIGH 1/(tWICL + tWICH) 7.5 7.5 10 ns 66.5 66.5 50 MHz 2.5 2.5 ns Input Register Clock Width Maximum Input Register Frequency 7.5 14.5 D-type tWICL tWICH 13.5 tSIL Input Latch Setup Time 2.5 3 tHIL Input Latch Hold Time tIGO Input Latch Gate to Combinatorial Output tIGOL Input Latch Gate to Output Through Transparent Output Latch tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 11 14.5 18 ns tIGS Input Latch Gate to Output Latch Setup 16 19.5 25.5 ns tWIGL tPDLL Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 7.5 MACH220-14/18/24 (Ind) 3.5 4 ns 20.5 24 30 ns 23 26.5 32.5 ns 7.5 19.5 10 23 29 ns ns 15 AMD SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued) -14 Min Max Parameter Symbol Parameter Description tAR Asynchronous Reset to Registered or Latched Output tARW Asynchronous Reset Width (Note 1) tARR Asynchronous Reset Recovery Time (Note 1) tAP Asynchronous Preset to Registered or Latched Output -18 Min Max 19.5 -24 Min Max 24 30 Unit ns 14.5 18 24 ns 10 12 18 ns 19.5 24 30 ns tAPW Asynchronous Preset Width (Note 1) 14.5 18 24 ns tAPR Asynchronous Preset Recovery Time (Note 1) 10 12 18 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 14.5 18 24 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 14.5 18 24 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. Parameters measured with 24 outputs switching. 16 MACH220-14/18/24 (Ind) AMD TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS VCC = 5.0 V, TA = 25°C IOL (mA) 80 60 40 20 VOL (V) –1.0 –0.8 –0.6 –0.4 –0.2 –20 .2 .4 .6 .8 1.0 –40 –60 –80 14130I-4 Output, LOW IOH (mA) 25 1 2 3 4 5 VOH (V) –3 –2 –1 –25 –50 –75 –100 –125 14130I-5 –150 Output, HIGH II (mA) 20 VI (V) –2 –1 –20 1 2 3 4 5 –40 –60 –80 –100 14130I-6 Input MACH220-10/12/15/20 17 AMD TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25°C 275 MACH220 250 225 200 175 150 ICC (mA) 125 100 75 50 25 0 0 10 20 30 40 50 Frequency (MHz) 60 70 80 90 14130I-7 The selected “typical” pattern is a 12-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. 18 MACH220-10/12/15/20 AMD TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Parameter Symbol Typ Parameter Description PLCC Units θjc Thermal impedance, junction to case 10 °C/W θja Thermal impedance, junction to ambient 33 °C/W 200 lfpm air 29 °C/W 400 lfpm air 27 °C/W 600 lfpm air 24 °C/W 800 lfpm air 23 °C/W θjma Thermal impedance, junction to ambient with air flow Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. MACH220-10/12/15/20 19 AMD SWITCHING WAVEFORMS Input, I/O, or Feedback VT tPD Combinatorial Output VT 14130I-8 Combinatorial Output Input, I/O, or Feedback Input, I/O, or Feedback VT tS VT tH tSL Gate VT Clock tHL tCO Registered Output VT tPDL tGO Latched Out VT VT 14130I-10 14130I-9 Registered Output Latched Output (MACH 2, 3, and 4) tWH Clock Gate VT tGWS tWL 14130I-12 14130I-11 Clock Width Gate Width (MACH 2, 3, and 4) Registered Input VT tSIR Input Register Clock Registered Input tHIR Input Register Clock VT tICO Combinatorial Output VT 14130I-13 Output Register Clock Registered Input (MACH 2 and 4) Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. 20 VT MACH220-10/12/15/20 VT tICS VT 14130I-14 Input Register to Output Register Setup (MACH 2 and 4) AMD SWITCHING WAVEFORMS Latched In VT tSIL tHIL Gate VT tIGO Combinatorial Output VT 14130I-15 Latched Input (MACH 2 and 4) tPDLL Latched In VT Latched Out Input Latch Gate VT tIGOL tSLL tIGS VT Output Latch Gate 14130I-16 Latched Input and Output (MACH 2, 3, and 4) Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. MACH220-10/12/15/20 21 AMD SWITCHING WAVEFORMS tWICH Clock Input Latch Gate VT VT tWICL tWIGL 14130I-18 14130I-17 Input Register Clock Width (MACH 2 and 4) Input Latch Gate Width (MACH 2 and 4) tARW tAPW Input, I/O, or Feedback Input, I/O, or Feedback VT VT tAR Registered Output tAP Registered Output VT VT tARR Clock tAPR Clock VT VT 14130I-19 14130I-20 Asynchronous Reset Asynchronous Preset Input, I/O, or Feedback VT tER Outputs tEA VOH - 0.5V VOL + 0.5V VT 14130I-21 Output Disable/Enable Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. 22 MACH220-10/12/15/20 AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT 5V S1 R1 Output Test Point R2 CL 14130I-22 Commercial Specification tPD, tCO tEA tER S1 CL R1 R2 Closed Measured Output Value 1.5 V Z → H: Open Z → L: Closed 35 pF H → Z: Open L → Z: Closed 5 pF 1.5 V 300 Ω 390 Ω H → Z: VOH – 0.5 V L → Z: VOL + 0.5 V *Switching several outputs simultaneously should be avoided for accurate measurement. MACH220-10/12/15/20 23 AMD fMAX PARAMETERS The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated “fMAX external.” The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated “fMAX internal”. A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called “fCNT.” The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated “fMAX no feedback.” For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly. CLK CLK (SECOND CHIP) LOGIC LOGIC REGISTER tS tS t CO fMAX Internal (fCNT) fMAX External; 1/(tS + tCO) LOGIC REGISTER CLK CLK REGISTER REGISTER tS tSIR fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL) LOGIC tHIR fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH) 14130I-23 24 MACH220-10/12/15/20 AMD ENDURANCE CHARACTERISTICS The MACH families are manufactured using AMD’s advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics Parameter Symbol tDR N Parameter Description Min Units Test Conditions 10 Years Max Storage Temperature Min Pattern Data Retention Time 20 Years Max Operating Temperature Max Reprogramming Cycles 100 Cycles Normal Programming Conditions MACH220-10/12/15/20 25 AMD INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC 100 kΩ 1 kΩ VCC ESD Protection Input VCC VCC 100 kΩ 1 kΩ Preload Circuitry Feedback Input 14130I-24 I/O 26 MACH220-10/12/15/20 AMD POWER-UP RESET The MACH devices have been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the Parameter Symbol wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Descriptions Max Unit tPR Power-Up Reset Time 10 µs tS Input or Feedback Setup Time tWL Clock Width LOW See Switching Characteristics VCC Power 4V tPR Registered Output tS Clock tWL 14130I-25 Power-Up Reset Waveform MACH220-10/12/15/20 27 AMD USING PRELOAD AND OBSERVABILITY In order to be testable, a circuit must be both controllable and observable. To achieve this, the MACH devices incorporate register preload and observability. Preloaded HIGH D In preload mode, each flip-flop in the MACH device can be loaded from the I/O pins, in order to perform functional testing of complex state machines. Register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. This ability to control the MACH device’s internal state can shorten test sequences, since it is easier to reach the state of interest. Q1 Q AR Preloaded HIGH The observability function makes it possible to see the internal state of the buried registers during test by overriding each register’s output enable and activating the output buffer. The values stored in output and buried registers can then be observed on the I/O pins. Without this feature, a thorough functional test would be impossible for any designs with buried registers. D Q2 Q AR While the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. One case involves asynchronous reset and preset. If the MACH registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. This is illustrated in Figure 2. Care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. Another case to be aware of arises in testing combinatorial logic. When an output is configured as combinatorial, the observability feature forces the output into registered mode. When this happens, all product terms are forced to zero, which eliminates all combinatorial data. For a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. If the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in Figure 3. As this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. To insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. On Preload Mode Off Q1 AR Q2 Figure 2. Preload/Reset Conflict 14130I-26 Set All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support. Reset Figure 3. Combinatorial Latch 14130I-27 28 MACH220-10/12/15/20 AMD DEVELOPMENT SYSTEMS (subject to change) For more information on the products listed below, please consult the AMD FusionPLD Catalog. MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 MACHXL Software Ver. 2.0 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Design Center/AMD Software Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 AMD-ABEL Software Data I/O MACH Fitters Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 PROdeveloper/AMD Software PROsynthesis/AMD Software Cadence Design Systems 555 River Oaks Pkwy San Jose, CA 95134 (408) 943-1234 Capilano Computing 960 Quayside Dr., Suite 406 New Westminster, B.C. Canada V3M 6G2 (800) 444-9064 or (604) 552-6200 CINA, Inc. P.O. Box 4872 Mountain View, CA 94040 (415) 940-1723 ComposerPICTM Designer (Requires MACH Fitter) Verilog, LeapFrog, RapidSim Simulators (Models also available from Logic Modeling) Ver. 3.3 MacABELTM Software (Requires SmartPart MACH Fitter) SmartCAT Circuit Analyzer Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 ABELTM-5 Software (Requires MACH Fitter) SynarioTM Software iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (89) 857-6667 PLDSim 90 ISDATA GmbH Daimlerstr. 51 D7500 Karlsruhe 21 Germany Germany: 0721/75 10 87 U.S.: (510) 531-8553 LOG/iCTM Software (Requires MACH Fitter) Logic Modeling 19500 NW Gibbs Dr. P.O. Box 310 Beaverton, OR 97075 (503) 690-6900 SmartModel Library Logical Devices, Inc. 692 S. Military Trail Deerfield Beach, FL 33442 (800) 331-7766 or (305) 428-6868 CUPLTM Software MACH220-10/12/15/20 29 AMD DEVELOPMENT SYSTEMS (subject to change) (continued) MANUFACTURER Mentor Graphics Corp. 8005 S.W. Boeckman Rd. Wilsonville, OR 97070-7777 (800) 547-3000 or (503) 685-7000 SOFTWARE DEVELOPMENT SYSTEMS PLDSynthesisTM (Requires MACH Fitter) QuickSim Simulator (Models also available from Logic Modeling) MicroSim Corp. 20 Fairbanks Irvine, CA 92718 (714) 770-3022 MINC Incorporated 6755 Earl Drive, Suite 200 Colorado Springs, CO 80918 (800) 755-FPGA or (719) 590-1155 OrCAD 3175 N.W. Aloclek Dr. Hillsboro, OR 97124 (503) 690-9881 Design Center Software (Requires MACH Fitter) PLDesignerTM-XL Software (Requires MACH Fitter) Programmable Logic Design Tools 386+ Schematic Design Tool 386+ Digital Simulation Tools SUSIE–CAD 10000 Nevada Highway, Suite 201 Boulder City, NV 89005 (702) 293-2271 SUSIETM Simulator Teradyne EDA 321 Harrison Ave. Boston, MA 02118 (800) 777-2432 or (617) 422-2793 MultiSIM Interactive Simulator LASAR Viewlogic Systems, Inc. 293 Boston Post Road West Marlboro, MA 01752 (800) 442-4660 or (508) 480-0881 MANUFACTURER Acugen Software, Inc. 427-3 Amherst St., Suite 391 Nashua, NH 03063 (603) 891-1995 ViewPLD or PROPLD (Requires PROSim Simulator MACH Fitter) ViewSim Simulator (Models for ViewSim also available from Logic Modeling) TEST GENERATION SYSTEM ATGENTM Test Generation Software iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (87) 857-6667 PLDCheck 90 Advanced Micro Devices is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor an endorsement by AMD of these products. 30 MACH220-10/12/15/20 AMD APPROVED PROGRAMMERS (subject to change) For more information on the products listed below, please consult the AMD FusionPLD Catalog. MANUFACTURER PROGRAMMER CONFIGURATION Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, CA 94086 (408) 243-7000 Pilot U84 BP Microsystems 100 N. Post Oak Rd. Houston, TX 77055-7237 (800) 225-2102 or (713) 688-4600 BP1200 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 UniSiteTM Model 3900 Logical Devices Inc./Digelec 692 S. Military Trail Deerfield Beach, FL 33442 (800) 331-7766 or (305) 428-6868 AutoSite ALLPROTM–88 SMS North America, Inc. 16522 NE 135th Place Redmond, WA 98052 (800) 722-4122 or SMS lm Grund 15 D-7988 Vangen Im Allgau, Germany 07522-5018 Sprint/Expert Stag Microsystems Inc. 1600 Wyatt Dr. Suite 3 Santa Clara, CA 95054 (408) 988-1118 or Stag House Martinfield, Welwyn Garden City Herfordshire UK AL7 1JT 707-332148 Stag Quazar System General 510 S. Park Victoria Dr. Milpitas, CA 95035 (408) 263-6667 or 3F, No. 1, Alley 8, Lane 45 Bao Shing Rd., Shin Diau Taipei, Taiwan 2-917-3005 Turpro-1 APPROVED ON-BOARD PROGRAMMERS MANUFACTURER PROGRAMMER CONFIGURATION Corelis, Inc. 12607 Hidden Creek Way, Suite H Cerritos, California 70703 (310) 926-6727 JTAG PROG Advanced Micro Devices P.O. Box 3453, MS-1028 Sunnyvale, CA 94088-3453 (800) 222-9323 MACHpro MACH220-10/12/15/20 31 AMD PROGRAMMER SOCKET ADAPTERS (subject to change) MANUFACTURER PART NUMBER EDI Corporation P.O. Box 366 Patterson, CA 95363 (209) 892-3270 Contact Manufacturer Emulation Technology 2344 Walsh Ave., Bldg. F Santa Clara, CA 95051 (408) 982-0660 Contact Manufacturer Logical Systems Corp. P.O. Box 6184 Syracuse, NY 13217-6184 (315) 478-0722 Contact Manufacturer Procon Technologies, Inc. 1333 Lawrence Expwy, Suite 207 Santa Clara, CA 95051 (408) 246-4456 Contact Manufacturer 32 MACH220-10/12/15/20 AMD PHYSICAL DIMENSIONS* PL 068 68-Pin Plastic Leaded Chip Carrier (measured in inches) .985 .995 .042 .056 .950 .956 .062 .083 Pin 1 I.D. .985 .995 .950 .956 .800 .890 REF .930 .013 .021 .026 .032 .007 .013 .050 REF TOP VIEW .090 .130 .165 .180 SEATING PLANE SIDE VIEW 16-038-SQ PL 068 DA78 6-28-94 ae *For reference only. BSC is an ANSI standard for Basic Space Centering. Trademarks Copyright 1995 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. MACH220-10/12/15/20 33