MAXIM MAX14548AE

19-5248; Rev 0; 4/10
TION KIT
EVALUA BLE
IL
AVA A
100Mbps, 16-Channel LLTs
The MAX14548E/MAX14548AE 16-channel, bidirectional
level translators (LLTs) provide the level shifting necessary for 100Mbps data transfer in multivoltage systems.
Externally applied voltages, VCC and VL, set the logic
levels on either side of the device. Logic signals present
on the VL side of the device appear as a high-voltage
logic signal on the VCC side of the device and vice versa.
The devices feature a programming frequency input (PF) that
adjusts the one-shot accelerator on-time to guarantee a bit
rate of 100Mbps with a load capacitance < 15pF and VL >
1.1V (MAX14548E) or VL > 1.4V (MAX14548AE) when driven
low. The MAX14548E can drive capacitive loads up to
50/R 1.1pF with a guaranteed bit rate of 40Mbps when
VL > 1.1/R 1.1V and PF is driven high. The MAX14548AE
can drive capacitive loads up to 50pF with a guaranteed
bit rate of 40Mbps when VL > 1.1V and PF is driven high.
Features
S Bidirectional Level Translation
S 100Mbps Guaranteed Data Rate
S +1.7V to +3.6V Supply Voltage Range for VCC
S +1.1V to +3.6V Supply Voltage Range for VL
(VCC > VL)
S -40NC to +85NC Extended Operating Temperature
Range
Applications
CMOS Logic-Level Translation
Low-Voltage ASIC Level Translation
Smart Card Readers
Portable Communication Devices
Cell Phones
The device operate at full speed with external drivers
that source as low as 4mA output current. Each I/O channel is pulled up to VCC or VL by an internal 35FA current
source, allowing both devices to be driven by either
push-pull or open-drain drivers.
The devices feature multiple power-saving features
including an enable input (EN) that places the device
into a low-power shutdown mode when driven low and
an automatic shutdown mode that disables the part
when VCC is less than VL. The MAX14548AE output driver is designed to operate at full speed (100Mbps) with
VL > 1.4V, which reduces the dynamic supply current vs.
the MAX14548E. The state of I/O VCC_and I/O VL_are in
high-impedance state during shutdown.
GPS
Telecommunications Equipment
Typical Operating Circuit appears at end of data sheet.
The devices operate with VCC voltages from +1.7V to
+3.6V and VL voltages from +1.1V to +3.6V, making
them ideal for data transfer between low-voltage ASICs/
PLDs and higher voltage systems. The devices are available in a 40-bump WLP (2.16mm x 3.46mm) package
with 0.4mm ball pitch, and operate over the extended
-40NC to +85NC temperature range.
Ordering Information/Selector Guide
PINPACKAGE
BIT RATE (PF = LOW)
LOAD CAPACITANCE < 15pF
(Mbps)
BIT RATE (PF = HIGH)
LOAD CAPACITANCE < 50pF
(Mbps)
MAX14548EEWL+
40 WLP
100
40
—
MAX14548AEEWL+
40 WLP
100
40
Yes (VL > 1.1V)
PART
LOW DYNAMIC
SUPPLY
CURRENT
Note: All devices operate over the -40°C to +85°C operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX14548E/MAX14548AE
General Description
MAX14548E/MAX14548AE
100Mbps, 16-Channel LLTs
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
VCC, VL, EN, PF.......................................................-0.3V to +4V
I/O VCC_.................................................... -0.3V to (VCC + 0.3V)
I/O VL_.......................................................... -0.3V to (VL + 0.3V)
Short-Circuit Duration I/O VL_,
I/O VCC_ to GND.....................................................Continuous
Continuous Power Dissipation (TA = +70NC)
40-Bump WLP (derate 17.2mW/NC above +70NC).....1379mW
Junction-to-Ambient Thermal Resistance (BJA)
(Note 1).........................................................................58NC/W
Operating Temperature Range........................... -40NC to +85NC
Storage Temperature Range............................. -65NC to +150NC
Junction Temperature......................................................+150NC
Soldering Temperature (reflow).......................................+260NC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, CVCC = 1FF, CVL = 1FF, TA = -40NC to +85NC, unless otherwise
noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
POWER SUPPLIES
VL Supply Range
VCC Supply Range
Supply Current from VCC
Supply Current from VL
VCC Shutdown Supply
Current
VL Shutdown Mode Supply
Current
Dynamic Supply Current
1.1
3.6
1.7
3.6
V
IQVCC
I/O VCC_ = VCC, I/O VL_ = VL
40
FA
IQVL
I/O VCC_ = VCC, I/O VL_ = VL
20
FA
FA
ISHDN-VCC
ISHDN-VL
ID
I/O VCC_, I/O VL_ Three-State
Leakage Current
ILEAK
EN, PF Input Leakage Current
ILEAK_EN_PF
TA = +25NC, EN = GND, unconnected
I/O pins
0.1
1
TA = +25NC, EN = GND, unconnected
I/O pins
0.1
1
TA = +25NC, EN = VL, VCC = GND,
unconnected I/O pins
0.1
2
One I/O switching at
25MHz; all other I/O
connected to VCC or
VL; CLOAD = 0pF
FA
MAX14548E
2.9
MAX14548AE
2.6
mA
0.1
TA = +25NC, EN = GND
TA = +25NC
6
FA
1
FA
VL Shutdown Threshold
VTH_VL
VL - VCC Shutdown Threshold
High
VTH_H
VCC rising (VL = 3.6V) (Note 4)
0.05
0.3
0.65
V
VL - VCC Shutdown Threshold
Low
VTH_L
VCC falling (VL = 3.6V) (Note 4)
0.2
0.52
0.85
V
I/O VL_ Pullup Current
2
VL
VCC
0.3
V
IVL_PU_
I/O VL_ = GND, I/O VCC_ = GND
10
125
FA
I/O VCC_ Pullup Current
IVCC_PU_
I/O VCC_ = GND, I/O VL_ = GND
15
90
FA
I/O VL_ to I/O VCC_ DC
Resistance
RIOVL_IOVCC
(Note 5)
3
kI
100Mbps, 16-Channel LLTs
(VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, CVCC = 1FF, CVL = 1FF, TA = -40NC to +85NC, unless otherwise
noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ESD PROTECTION
Human Body
Model,
CVCC = 1FF,
CVL = 1FF
I/O VCC_, I/O VL_
Unpowered
device
Q12
Powered device
Q5
kV
All Other Pins
kV
Q2
LOGIC LEVELS
I/O VL_ Input-Voltage High
Threshold
VIHL
(Note 6)
I/O VL_ Input-Voltage Low
Threshold
VILL
(Note 6)
I/O VCC_ Input-Voltage High
Threshold
VIHC
(Note 6)
I/O VCC_ Input-Voltage Low
Threshold
VILC
(Note 6)
EN, PF Input-Voltage High
Threshold
VIH
EN, PF Input-Voltage Low
Threshold
VIL
VL 0.2
V
0.15
VCC 0.4
V
0.2
1.1V < VL < 1.3V
VL 0.25
VL = 1.8V
VL 0.4
0.4
VL = 1.8V
0.4
VOHL
I/O VL_ source current = 10FA
I/O VL_ Output-Voltage Low,
Drop to GND
VOLL
I/O VL_ sink current = 20FA,
I/O VCC_ < 0.05V
I/O VCC_ Output-Voltage High
VOHC
I/O VCC_ source current = 10FA
I/O VCC_ Output-Voltage Low,
Drop to GND
VOLC
I/O VCC_ sink current = 20FA,
I/O VL_ < 0.05V
V
V
1.1V < VL < 1.3V
I/O VL_ Output-Voltage High
V
4/5 x
VL
V
V
1/3 x
VL
4/5 x
VCC
V
V
1/3 x
VCC
V
RISE/FALL TIME ACCELERATOR STAGE
PF = low
Accelerator Pulse Duration
PF = high
On rising edge
2.65
On falling edge
2.5
On rising edge
4
On falling edge
3.7
VL Output Accelerator Source
Impedance
VL = 1.62V
7
VL = 3.2V
4.43
VCC Output Accelerator
Source Impedance
VCC = 2.2V
14.2
VCC = 3.6V
11.2
VL Output Accelerator Sink
Impedance
VL = 1.62V
15.3
VL = 3.2V
15.3
VCC Output Accelerator Sink
Impedance
VCC = 2.2V
20.3
VCC = 3.6V
19.5
ns
ns
I
I
I
I
3
MAX14548E/MAX14548AE
ELECTRICAL CHARACTERISTICS (continued)
MAX14548E/MAX14548AE
100Mbps, 16-Channel LLTs
HIGH-SPEED TIMING CHARACTERISTICS—MAX14548E
(VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, PF = low, CVCC = 1FF, CVL = 1FF, CIOVL P 15pF, CIOVCC P 15pF,
TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I/O VCC_ Rise Time
tRVCC
Input rise time < 2ns, Figure 1
2
ns
I/O VCC_ Fall Time
tFVCC
Input fall time < 2ns, Figure 1
2
ns
I/O VL_ Rise Time
tRVL
Input rise time < 2ns, Figure 2
2
ns
I/O VL_ Fall Time
tFVL
Input fall time < 2ns, Figure 2
2
ns
Propagation Delay
(Driving I/O VL_)
tPVL-VCC
Input rise time < 2ns, Figure 1
2.75
ns
Propagation Delay
(Driving I/O VCC_)
tPVCC-VL
Input rise time < 2ns, Figure 2
2.26
ns
tSKEW
Input rise time/fall time < 2ns
0.2
ns
Channel-to-Channel Skew
Propagation Delay from
I/O VL_ to I/O VCC_ After EN
tEN-VCC
RLOAD = 1MI, Figure 3
27
Fs
Propagation Delay from
I/O VCC_ to I/O VL_ After EN
tEN-VL
RLOAD = 1MI, Figure 3
0.05
Fs
Maximum Data Rate
Push-pull operation
100
Open-drain operation
0.3
Mbps
HIGH-SPEED TIMING CHARACTERISTICS—MAX14548AE
(VCC = +1.7V to +3.6V, VL = +1.4V to +3.6V, VCC > VL, EN = VL, PF = low, CVCC = 1FF, CVL = 1FF, CIOVL P 15pF, CIOVCC P 15pF,
TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
MAX
UNITS
I/O VCC_ Rise Time
PARAMETER
tRVCC
Input rise time < 2ns, Figure 1
2
ns
I/O VCC_ Fall Time
tFVCC
Input fall time < 2ns, Figure 1
2
ns
I/O VL_ Rise Time
tRVL
Input rise time < 2ns, Figure 2
2
ns
I/O VL_ Fall Time
tFVL
Input rise time < 2ns, Figure 2
2
ns
Propagation Delay
(Driving I/O VL_)
tPVL-VCC
Input rise time < 2ns, Figure 1
2.75
ns
Propagation Delay
(Driving I/O VCC_)
tPVCC-VL
Input rise time < 2ns, Figure 2
2.26
ns
tSKEW
Input rise time/fall time < 2ns
0.2
ns
Channel-to-Channel Skew
CONDITIONS
MIN
TYP
Propagation Delay from
I/O VL_ to I/O VCC_ After EN
tEN-VCC
RLOAD = 1MI, Figure 3
27
Fs
Propagation Delay from
I/O VCC_ to I/O VL_ After EN
tEN-VL
RLOAD = 1MI, Figure 3
0.05
Fs
Maximum Data Rate
4
SYMBOL
Push-pull operation
100
Open-drain operation
0.3
Mbps
100Mbps, 16-Channel LLTs
(VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, PF = high, CVCC = 1FF, CVL = 1FF, CIOVL P 50pF, CIOVCC P 50pF,
TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I/O VCC_ Rise Time
tRVCC
Input rise time < 6ns, Figure 1
6
ns
I/O VCC_ Fall Time
tFVCC
Input fall time < 6ns, Figure 1
6
ns
I/O VL_ Rise Time
tRVL
Input rise time < 6ns, Figure 2
6
ns
I/O VL_ Fall Time
tFVL
Input rise time < 6ns, Figure 2
6
ns
Propagation Delay
(Driving I/O VL_)
tPVL-VCC
Input rise time < 6ns, Figure 1
4
ns
Propagation Delay
(Driving I/O VCC_)
tPVCC-VL
Input rise time < 6ns, Figure 2
3.37
ns
tSKEW
Input rise time/fall time < 6ns
0.2
Channel-to-Channel Skew
0.5
ns
Propagation Delay from
I/O VL_ to I/O VCC_ After EN
tEN-VCC
RLOAD = 1MI, Figure 3
27
Fs
Propagation Delay from
I/O VCC_ to I/O VL_ After EN
tEN-VL
RLOAD = 1MI, Figure 3
0.06
Fs
Maximum Data Rate
Push-pull operation
40
Open-drain operation
0.3
Mbps
LOW-SPEED TIMING CHARACTERISTICS—MAX14548AE
(VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, PF = high, CVCC = 1FF, CVL = 1FF, CIOVL P 50pF, CIOVCC P 50pF,
TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I/O VCC_ Rise Time
tRVCC
Input rise time < 6ns, Figure 1
6
ns
I/O VCC_ Fall Time
tFVCC
Input fall time < 6ns, Figure 1
6
ns
I/O VL_ Rise Time
tRVL
Input rise time < 6ns, Figure 2
6
ns
I/O VL_ Fall Time
tFVL
Input rise time < 6ns, Figure 2
6
ns
Propagation Delay
(Driving I/O VL_)
tPVL-VCC
Input rise time < 6ns, Figure 1
4
ns
Propagation Delay
(Driving I/O VCC_)
tPVCC-VL
Input rise time < 6ns, Figure 2
3.37
ns
tSKEW
Input rise time/fall time < 6ns
0.2
ns
Channel-to-Channel Skew
Propagation Delay from
I/O VL_ to I/O VCC_ After EN
tEN-VCC
RLOAD = 1MI, Figure 3
27
Fs
Propagation Delay from
I/O VCC_ to I/O VL_ After EN
tEN-VL
RLOAD = 1MI, Figure 3
0.06
Fs
Maximum Data Rate
Push-pull operation
40
Open-drain operation
0.3
Mbps
Note 2: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design and not production tested.
Note 3: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and
shutdown conditions.
Note 4: When VCC is below VL by more than the VL - VCC shutdown threshold, the device turns off its pullup generators and
I/O VCC_ and I/O VL_ enter their respective shutdown states.
Note 5: Guaranteed by design.
Note 6: Input thresholds are referenced to the boost circuit.
5
MAX14548E/MAX14548AE
LOW-SPEED TIMING CHARACTERISTICS—MAX14548E
MAX14548E/MAX14548AE
100Mbps, 16-Channel LLTs
VL
VL
EN
VL
tFVCC
tRVCC
VCC
90%
VCC
90%
I/O VL_
MAX14548E
MAX14548AE VCC
50%
50%
50%
I/O VL_
I/O VCC_
50%
I/O VCC_ 10%
10%
CIOVCC
tPLH
tPLH
tPVL-VCC = tPLH OR tPHL
NOTE: THE INPUT RISE/FALL TIMES ARE < 2ns FOR HIGH SPEED AND < 6ns FOR LOW SPEED.
Figure 1. Push-Pull Driving I/O VL_ Test Circuit and Timing
VL
tRVL
VCC
VL
EN
VL
tFVL
I/O VCC_
VCC
MAX14548E
MAX14548AE VCC
90%
50%
50%
I/O VL_
50%
50%
I/O VCC_
CIOVCC
10%
tPLH
tPLH
tPVCC-VL = tPLH OR tPHL
NOTE: THE INPUT RISE/FALL TIMES ARE < 2ns FOR HIGH SPEED AND < 6ns FOR LOW SPEED.
Figure 2. Push-Pull Driving I/O VCC_ Test Circuit and Timing
6
90%
10%
I/O VL_
100Mbps, 16-Channel LLTs
VL
MAX14548E
VL MAX14548AE VCC
EN
t’EN-VCC
I/O VCC_
SOURCE
RLOAD
VL
CIOVCC
I/O VCC_
O
VCC/2
VCC
RLOAD
SOURCE
EN
t”EN-VCC
O
I/O VCC_
O
VL
I/O VL_
I/O VL_
VCC
VL
EN
MAX14548E
V
MAX14548AE CC
O
VL
I/O VL_
I/O VL_
VL
MAX14548E/MAX14548AE
EN
O
I/O VCC_
VCC/2
CIOVCC
VCC
O
tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
EN
VL
VL
MAX14548E V
CC
MAX14548AE
EN
t’EN-VL
SOURCE
I/O VL_
RLOAD
CIOVL
VCC
I/O VCC_
I/O VCC_
O
VCC
I/O VL_
VL /2
EN
VL
SOURCE
VL
O
VL
MAX14548E
VL
MAX14548AE VCC
EN
RLOAD
I/O VCC_
I/O VL_
CIOVL
O
t”EN-VL
O
VCC
I/O VCC_
O
I/O VL_
VL /2
VL
O
tEN-VL IS WHICHEVER IS LARGER BETWEEN t'EN-VL AND t"EN-VL.
Figure 3. Enable Test and Timing
7
Typical Operating Characteristics
(VCC = 1.8V, VL = 1.4V, CL = 15pF, RSOURCE = 150I, data rate = 100Mbps, push-pull driver, TA = +25NC, unless otherwise noted.)
150
MAX14548AE
100
50
MAX14548E
0
1.700
4.0
MAX14548E
3.5
MAX14548AE
3.0
2.5
2.0
VCC = 3.6V
CLOAD = 15pF
PF = LOW
DATA RATE = 40Mbps
1.5
1.0
0.5
2.650
3.125
3.600
1.1
1.6
2.1
CLOAD = 15pF
PF = HIGH
DATA RATE = 40Mbps
6
5
4
3
MAX14548AE
2
MAX14548E
1
2.6
3.1
0
1.700
3.6
2.175
2.650
3.125
3.600
VCC SUPPLY VOLTAGE (V)
VCC SUPPLY CURRENT vs. VL SUPPLY
VOLTAGE (DRIVING ONE I/O VCC_)
VL SUPPLY CURRENT vs. CAPACITIVE LOAD
(DRIVING ONE I/O VCC)
VCC SUPPLY CURRENT vs. CAPACITIVE
LOAD (DRIVING ONE I/O VL_)
3
VCC = 3.6V
CLOAD = 15pF
PF = HIGH
DATA RATE = 40Mbps
2
1
1000
MAX14548E
PF LOW
800
600
MAX14548AE
PF LOW
400
DATA RATE = 40Mbps
0
2.1
2.6
3.1
MAX14548E
PF LOW
1000
MAX14548AE
PF LOW
20
30
DATA RATE = 40Mbps
0
40
10
50
20
30
40
CAPACITIVE LOAD (pF)
RISE TIME vs. CAPACITIVE LOAD
ON I/O VCC (DRIVING ONE I/O VL)
FALL TIME vs. CAPACITIVE LOAD
ON I/O VCC (DRIVING ONE I/O VL)
RISE TIME vs. CAPACITIVE LOAD
ON I/O VL (DRIVING ONE I/O VCC)
1.5
1.0
tRVCC
MAX14548AE
(PF LOW)
0.5
2.5
tRVCC
MAX14548E
(PF LOW)
tFVCC
MAX14548AE (PF HIGH)
2.0
1.0
tRVCC
MAX14548E
(PF LOW)
0.5
DATA RATE = 40Mbps
0
30
40
CAPACITIVE LOAD (pF)
50
10
20
30
tRVL
MAX14548AE (PF LOW)
2.0
1.5
tFVL
MAX14548E
(PF HIGH)
1.0
0.5
DATA RATE = 40Mbps
0
20
tFVCC
MAX14548E
(PF HIGH)
tRVL
MAX14548E (PF LOW) DATA RATE = 40Mbps
0
40
CAPACITIVE LOAD (pF)
50
50
tFVL
MAX14548AE (PF HIGH)
3.0
2.5
tRVCC
MAX14548AE (PF LOW)
1.5
3.5
RISE TIME (ns)
tFVCC
MAX14548E (PF HIGH)
10
1500
CAPACITIVE LOAD (pF)
tFVCC
MAX14548AE (PF HIGH)
2.0
10
3.6
2000
VL SUPPLY VOLTAGE (V)
FALL TIME (ns)
2.5
1.6
MAX14548E toc07
1.1
2500
500
200
0
MAX14548E
PF HIGH
MAX14548AE
PF HIGH
MAX14548E toc09
MAX14548AE
MAX14548AE
PF HIGH
1200
3000
MAX14548E toc08
4
1400
3500
VL SUPPLY CURRENT (µA)
MAX14548E
MAX14548E
PF HIGH
1600
VL SUPPLY CURRENT (µA)
MAX14548E toc04
5
1800
MAX14548E toc06
VL SUPPLY VOLTAGE (V)
MAX14548E toc05
VCC SUPPLY VOLTAGE (V)
6
8
7
0
2.175
7
VCC SUPPLY CURRENT (mA)
4.5
VCC SUPPLY CURRENT (mA)
200
5.0
VCC SUPPLY CURRENT vs. VCC SUPPLY
VOLTAGE (DRIVING ONE I/O VL_)
MAX14548E toc02
CLOAD = 15pF
PF = LOW
VCC SUPPLY CURRENT (mA)
MAX14548E toc01
VL SUPPLY CURRENT (µA)
250
VCC SUPPLY CURRENT vs. VL SUPPLY
VOLTAGE (DRIVING ONE I/O VCC_)
MAX14548E toc03
VL SUPPLY CURRENT vs. VCC SUPPLY
VOLTAGE (DRIVING ONE I/O VL_)
RISE TIME (ns)
MAX14548E/MAX14548AE
100Mbps, 16-Channel LLTs
10
20
30
40
CAPACITIVE LOAD (pF)
50
100Mbps, 16-Channel LLTs
FALL TIME vs. CAPACITIVE LOAD
ON I/O VL (DRIVING ONE I/O VCC)
FALL TIME (ns)
1.5
1.0
tRVL
MAX14548AE
(PF LOW)
0.5
tRVL
MAX14548E
(PF LOW)
MAX14548E toc11
tFVL
MAX14548E (PF HIGH)
tPVL-VCC
MAX14548E
(PF LOW)
3.5
PROPAGATION DELAY (ns)
tFVL
MAX14548AE (PF HIGH)
2.0
4.0
MAX14548E toc10
2.5
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O VCC (DRIVING ONE I/O VL)
3.0
tPVL-VCC
MAX14548AE
(PF LOW)
2.5
2.0
tPVL-VCC
MAX14548E
(PF HIGH)
tPVL-VCC
MAX14548AE
(PF HIGH)
1.5
1.0
0.5
DATA RATE = 40Mbps
0
10
30
40
10
50
20
30
40
50
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
PROPAGATION DELAY vs. CAPACITIVE LOAD
ON I/O VL (DRIVING ONE I/O VCC)
TYPICAL I/O VL_ DRIVING
(DATA RATE = 100Mbps, CIOVCC = 10pF),
PF = LOW, MAX14548E
tPVCC-VL
MAX14548E
(PF HIGH)
4.0
3.5
3.0
tPVCC-VL
MAX14548E
(PF LOW)
2.5
2.0
MAX14548E toc13
MAX14548E toc12
4.5
PROPAGATION DELAY (ns)
20
DATA RATE = 40Mbps
0
I/O VL
1V/div
tPVCC-VL
MAX14548AE
(PF HIGH)
I/O VCC
1V/div
tPVCC-VL
MAX14548AE
(PF LOW)
1.5
1.0
0.5
DATA RATE = 40Mbps
0
10
20
30
40
50
10ns/div
CAPACITIVE LOAD (pF)
TYPICAL I/O VL_ DRIVING
(DATA RATE = 40Mbps, CIOVCC = 47pF),
PF = HIGH, MAX14548E
TYPICAL I/O VCC_ DRIVING
(DATA RATE = 100Mbps, CIOVL = 10pF),
PF = LOW, MAX14548E
MAX14548E toc14
20ns/div
MAX14548E toc15
I/O VL
1V/div
I/O VCC
1V/div
I/O VCC
1V/div
I/O VL
1V/div
10ns/div
9
MAX14548E/MAX14548AE
Typical Operating Characteristics (continued)
(VCC = 1.8V, VL = 1.4V, CL = 15pF, RSOURCE = 150I, data rate = 100Mbps, push-pull driver, TA = +25NC, unless otherwise noted.)
MAX14548E/MAX14548AE
100Mbps, 16-Channel LLTs
Typical Operating Characteristics (continued)
(VCC = 1.8V, VL = 1.4V, CL = 15pF, RSOURCE = 150I, data rate = 100Mbps, push-pull driver, TA = +25NC, unless otherwise noted.)
TYPICAL I/O VCC_ DRIVING
(DATA RATE = 40Mbps, CIOVL = 47pF),
PF = HIGH, MAX14548E
TYPICAL I/O VL_ DRIVING
(DATA RATE = 100Mbps, CIOVCC = 10pF),
PF = LOW, MAX14548AE
MAX14548E toc16
MAX14548E toc17
I/O VCC
1V/div
I/O VL
1V/div
I/O VCC
1V/div
I/O VL
1V/div
20ns/div
10ns/div
TYPICAL I/O VL_ DRIVING
(DATA RATE = 40Mbps, CIOVCC = 47pF),
PF = HIGH, MAX14548AE
TYPICAL I/O VCC_ DRIVING
(DATA RATE = 100Mbps, CIOVL = 10pF),
PF = LOW, MAX14548AE
MAX14548E toc18
MAX14548E toc19
I/O VL
1V/div
I/O VCC
1V/div
I/O VCC
1V/div
I/O VL
1V/div
20ns/div
10ns/div
TYPICAL I/O VCC_ DRIVING
(DATA RATE = 40Mbps, CIOVL = 47pF),
PF = HIGH, MAX14548AE
MAX14548E toc20
I/O VCC
1V/div
I/O VL
1V/div
20ns/div
10
100Mbps, 16-Channel LLTs
TOP VIEW
(BUMPS ON BOTTOM)
MAX14548E
MAX14548AE
1
2
3
4
5
6
7
8
I/O VL1
I/O VL2
I/O VL3
I/O VL4
I/O VL5
I/O VL6
I/O VL7
I/O VL8
I/O VL9
I/O VL10
I/O VL11
I/O VL12
I/O VL13
I/O VL14
I/O VL15
I/O VL16
GND
VL
VCC
EN
PF
VCC
VL
GND
I/O VCC1
I/O VCC2
I/O VCC3
I/O VCC4
I/O VCC5
I/O VCC6
I/O VCC7
I/O VCC8
I/O VCC9
I/O VCC10
I/O VCC11
I/O VCC12
I/O VCC13
I/O VCC14
I/O VCC15
I/O VCC16
+
A
B
C
D
E
WLP
(2.16mm × 3.46mm)
Pin Description
PIN
NAME
FUNCTION
A1
I/O VL1
Input/Output 1. Referenced to VL.
A2
I/O VL2
Input/Output 2. Referenced to VL.
A3
I/O VL3
Input/Output 3. Referenced to VL.
A4
I/O VL4
A5
I/O VL5
Input/Output 4. Referenced to VL.
Input/Output 5. Referenced to VL.
A6
I/O VL6
Input/Output 6. Referenced to VL.
A7
I/O VL7
Input/Output 7. Referenced to VL.
A8
I/O VL8
Input/Output 8. Referenced to VL.
B1
I/O VL9
B2
I/O VL10
Input/Output 9. Referenced to VL.
Input/Output 10. Referenced to VL.
B3
I/O VL11
Input/Output 11. Referenced to VL.
B4
I/O VL12
Input/Output 12. Referenced to VL.
B5
I/O VL13
B6
I/O VL14
Input/Output 13. Referenced to VL.
Input/Output 14. Referenced to VL.
B7
I/O VL15
Input/Output 15. Referenced to VL.
B8
I/O VL16
Input/Output 16. Referenced to VL.
C1, C8
GND
Ground
11
MAX14548E/MAX14548AE
Pin Configuration
100Mbps, 16-Channel LLTs
MAX14548E/MAX14548AE
Pin Description (continued)
12
PIN
NAME
FUNCTION
C2, C7
VL
C3, C6
VCC
Power-Supply Voltage, +1.7V to +3.6V. Bypass VCC to GND with a 0.1FF ceramic capacitor. For full
ESD protection, connect an additional 1FF ceramic capacitor from VCC to GND as close as possible
to the VCC input.
C4
EN
Enable Input. Drive EN to GND for shutdown mode, or drive EN to VL or VCC for normal operation.
C5
PF
Programmable Frequency Input. Drive PF low for high-frequency operation. Drive PF high for lower
frequency operation.
D1
I/O VCC1
Input/Output 1. Referenced to VCC.
D2
I/O VCC2
Input/Output 2. Referenced to VCC.
D3
I/O VCC3
Input/Output 3. Referenced to VCC.
D4
I/O VCC4
D5
I/O VCC5
Input/Output 4. Referenced to VCC.
Input/Output 5. Referenced to VCC.
D6
I/O VCC6
Input/Output 6. Referenced to VCC.
D7
I/O VCC7
Input/Output 7. Referenced to VCC.
D8
I/O VCC8
Logic Supply Voltage, +1.1V to +3.6V. Bypass VL to GND with a 1FF capacitor placed as close as
possible to the device.
E1
I/O VCC9
Input/Output 8. Referenced to VCC.
Input/Output 9. Referenced to VCC.
E2
I/O VCC10
Input/Output 10. Referenced to VCC.
E3
I/O VCC11
Input/Output 11. Referenced to VCC.
E4
I/O VCC12
Input/Output 12. Referenced to VCC.
E5
I/O VCC13
E6
I/O VCC14
Input/Output 13. Referenced to VCC.
Input/Output 14. Referenced to VCC.
E7
I/O VCC15
Input/Output 15. Referenced to VCC.
E8
I/O VCC16
Input/Output 16. Referenced to VCC.
100Mbps, 16-Channel LLTs
VL
VCC
MAX14548E
MAX14548AE
I/O VCC1
I/O VL1
I/O VL2
I/O VCC2
I/O VL15
I/O VCC15
I/O VL16
I/O VCC16
EN
PF
GND
Detailed Description
The MAX14548E/MAX14548AE 16-channel, bidirectional
level translators (LLTs) provide the level shifting necessary for 100Mbps data transfer in multivoltage systems.
Externally applied voltages, VCC and VL, set the logic
levels on either side of the device. Logic signals present
on the VL side of the device appear as a high-voltage
logic signal on the VCC side of the device and vice versa.
The devices operate at full speed with external drivers
that source as little as 4mA output current (min). Each
I/O channel is pulled up to VCC or VL by an internal
35FA current source, allowing the devices to be driven
by either push-pull or open-drain drivers.
The devices feature an enable input (EN) that places the
device into a low-power shutdown mode when driven
low. They also feature an automatic shutdown mode that
disables the part when VCC is less than VL.
The devices feature a programmable frequency input
(PF) that guarantees a bit rate of 100Mbps with a load
capacitance < 15pF and VL > 1.1V (MAX14548E) or VL >
1.4V (MAX14548AE) when driven low. The MAX14548E
can drive capacitive loads up to 50pF with a guaranteed
bit rate of 40Mbps when VL R 1.1V and PF is driven high.
The MAX14548AE can drive capacitive loads up to 50pF
with a guaranteed bit rate of 40Mbps when VL R 1.1V and
PF is driven high.
Level Translation
For proper operation, ensure that 1.7V P VCC P 3.6V,
1.1V P VL P VCC. When power is supplied to VL while
VCC is less than VL, the devices automatically enter a
low-power mode and the I/Os are in high-impedance
mode. The devices also enter shutdown mode when
EN = 0. In both conditions where EN = 0 or VL > VCC,
there is a known high-impedance state on I/O VL_and
I/O VCC_. The maximum data rate depends heavily on
the load capacitance (see the rise/fall time graphs in the
Typical Operating Characteristics), output impedance of
the driver, and the operating voltage range.
Input Driver Requirements
The device architecture is based on an nMOS pass gate
and output accelerator stages (Figure 4). The accelerators are active only when there is a rising/falling edge on
a given I/O. A short pulse is then generated where the
output accelerator stages become active and charge/
discharge the capacitances at the I/Os. Due to its architecture, both input stages become active during the
one-shot pulse. This can lead to some current feeding
into the external source that is driving the translator.
However, this behavior helps speed up the transition on
the driven side.
The devices have internal current sources capable of
sourcing 35FA to pull up the I/O lines. These internal
pullup current sources allow the inputs to be driven with
open-drain drivers and push-pull drivers. It is not recommended to use external pullup resistors on the I/O lines.
The architecture of the devices permit either side to be
driven with a minimum of 4mA drivers or larger.
Output Load Requirements
The device I/Os are designed to drive CMOS inputs.
Do not load the I/O lines with a resistive load less than
25kI and do not place an RC circuit at the input of
these devices to slow down the edges. If a slower rise/
fall time is required, refer to the MAX3000E/MAX3001E/
MAX3002–MAX3012 data sheet.
13
MAX14548E/MAX14548AE
Functional Diagram
MAX14548E/MAX14548AE
100Mbps, 16-Channel LLTs
VCC
VL
ENABLE
ENABLE
ENABLE
30µA
30µA
I/O VL_
I/O VCC_
VCC
VL
BOOST
CIRCUIT
VCC
VL
BOOST
CIRCUIT
NOTE 1: THE MAX14548E/MAX14548AE ARE ENABLED WHEN VL < VCC - 0.2V AND EN = VL.
Figure 4. Simplified Functional Diagram for One I/O Line
Shutdown Mode
The EN input places the devices into a low-power shutdown mode when driven low. The automatic shutdown
mode disables the devices when VCC is unconnected or
less than VL. When VCC is less than VL or EN = GND, the
devices enter shutdown mode.
Data Rate and Capacitive Load (PF Input)
The programmable frequency input (PF) adjusts the oneshot accelerator to guarantee a 100Mbps bit rate with a
load capacitance <15pF and VL > 1.1V (MAX14548E)
or VL > 1.4V (MAX14548AE) when driven low. The
MAX14548E can drive capacitive loads up to 50pF with
a guaranteed 40Mbps bit rate when VL > 1.1V and PF
is driven high. The MAX14548AE can drive capacitive
loads up to 50pF with a guaranteed 40Mbps bit rate
when VL > 1.1V and PF is driven high.
14
Applications Information
Layout Recommendations
Use standard high-speed layout practices when laying
out a board with the MAX14548E/MAX14548AE. For
example, to minimize line coupling, place all other signal
lines not connected to the devices at least 1x the substrate height of the PCB away from the input and output
lines of the devices.
Power-Supply Decoupling
To reduce ripple and the chance of introducing data
errors, bypass VL and VCC to ground with 0.1FF ceramic
capacitors. Place all capacitors as close as possible to
the power-supply inputs. For full ESD protection, bypass
VCC with a 1FF ceramic capacitor located as close as
possible to the VCC input.
100Mbps, 16-Channel LLTs
CHARGE-CURRENTLIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
Cs
100pF
RD
1500Ω
IP 100%
90%
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPS
DEVICE
UNDER
TEST
36.8%
10%
0
0
Figure 5a. Human Body ESD Test Model
tRL
TIME
tDL
CURRENT WAVEFORM
Figure 5b. Human Body Current Waveform
Unidirectional vs. Bidirectional Level
Translator
The devices bidirectional level translators can operate as
a unidirectional device by selecting one I/O as the input
and the corresponding I/O as an output. These devices
provide the smallest solution (WLP package) for level
translation applications.
ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The I/O VL_ and I/O VCC_ pins have extra protection
against static electricity.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
Human Body Model
Figure 5a shows the Human Body Model, and Figure
5b shows the current waveform it generates when discharged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through a
1.5kI resistor.
Use with External Pullup/Pulldown
Resistors
Due to the architecture of the devices, it is not recommended to use external pullup or pulldown resistors
on the bus. In certain applications, the use of external
pullup or pulldown resistors is desired to have a known
bus state when there is no active driver on the bus. The
devices include internal pullup current sources that set
the bus state when the device is enabled. In shutdown
mode, the state of I/O VCC_ and I/O VL_ is high impedance.
Open-Drain Signaling
The devices are designed to pass open-drain as well
as CMOS push-pull signals. When used with open-drain
signaling, the rise time is dominated by the interaction
of the internal pullup current source and the parasitic
load capacitance. The devices include internal rise time
accelerators to speed up transitions, eliminating any
need for external pullup resistors. For applications such
as I2C or 1-WireM that require an external pullup resistor,
refer to the MAX13046E and MAX13047E data sheets.
1-Wire is a registered trademark of Maxim Integrated
Products, Inc.
15
MAX14548E/MAX14548AE
RC
1MΩ
MAX14548E/MAX14548AE
100Mbps, 16-Channel LLTs
Typical Operating Circuit
+2.8V
+1.8V
1µF
1µF
VL
+1.8V
SYSTEM
CONTROLLER
PF
PF
0.1µF
VCC
+2.8V
SYSTEM
MAX14548A
MAX14548AE
EN
EN
DATA
16
I/O VL_
GND
I/O VCC_
DATA
16
GND
GND
Chip Information
PROCESS: BiCMOS
16
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
40 WLP
W402B3+1
21-0437
100Mbps, 16-Channel LLTs
REVISION
NUMBER
REVISION
DATE
0
4/10
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010
Maxim Integrated Products 17
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX14548E/MAX14548AE
Revision History