MAXIM MAX16070

19-5003; Rev 3; 8/11
12-Channel/8-Channel, Flash-Configurable System
Monitors with Nonvolatile Fault Registers
Features
The MAX16070/MAX16071 flash-configurable system monitors supervise multiple system voltages. The
MAX16070/MAX16071 can also accurately monitor
(Q2.5%) one current channel using a dedicated highside current-sense amplifier. The MAX16070 monitors
up to twelve system voltages simultaneously, and the
MAX16071 monitors up to eight supply voltages. These
devices integrate a selectable differential or single-ended analog-to-digital converter (ADC). Device configuration information, including overvoltage and undervoltage
limits and timing settings are stored in nonvolatile flash
memory. During a fault condition, fault flags and channel
voltages can be automatically stored in the nonvolatile
flash memory for later read-back.
S Operate from 2.8V to 14V
The internal 1% accurate 10-bit ADC measures each
input and compares the result to one overvoltage, one
undervoltage, and one early warning limit that can be
configured as either undervoltage or overvoltage. A fault
signal asserts when a monitored voltage falls outside the
set limits. Up to three independent fault output signals
are configurable to assert under various fault conditions.
S Eight General-Purpose Inputs/Outputs
Because the MAX16070/MAX16071 support a powersupply voltage of up to 14V, they can be powered
directly from the 12V intermediate bus in many systems.
S Flash Configurable Time Delays and Thresholds
The MAX16070/MAX16071 include eight/six programmable general-purpose inputs/outputs (GPIOs). GPIOs
are flash configurable as dedicated fault outputs, as a
watchdog input or output, or as a manual reset.
The MAX16070/MAX16071 feature nonvolatile fault memory for recording information during system shutdown
events. The fault logger records a failure in the internal
flash and sets a lock bit protecting the stored fault data
from accidental erasure. An SMBus™ or a JTAG serial
interface configures the MAX16070/MAX16071. The
MAX16070/MAX16071 are available in a 40-pin, 6mm x
6mm, TQFN package. Both devices are fully specified
from -40NC to +85NC.
S ±2.5% Current-Monitoring Accuracy
S 1% Accurate 10-Bit ADC Monitors 12/8 Voltage
Inputs
S Single-Ended or Differential ADC for System
Voltage/Current Monitoring
S Integrated High-Side, Current-Sense Amplifier
S 12/8 Monitored Inputs with Overvoltage/
Undervoltage/Early Warning Limit
S Nonvolatile Fault Event Logger
S Two Programmable Fault Outputs and One Reset
Output
Configurable as:
Dedicated Fault Outputs
Watchdog Timer Function
Manual Reset
Margin Enable
S SMBus (with Timeout) or JTAG Interface
S -40NC to +85NC Operating Temperature Range
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX16070ETL+
PART
-40NC to +85NC
40 TQFN-EP*
MAX16071ETL+
-40NC to +85NC
40 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Applications
Networking Equipment
Telecom Equipment (Base Stations, Access)
Storage/RAID Systems
Servers
Pin Configuration and Typical Operating Circuits appear at
end of data sheet.
SMBus is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX16070/MAX16071
General Description
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
ABSOLUTE MAXIMUM RATINGS
VCC, CSP, CSM to GND.........................................-0.3V to +15V
CSP to CSM...........................................................-0.7V to +0.7V
MON_, GPIO_, SCL, SDA, A0, RESET to GND
(programmed as open-drain outputs)..................-0.3V to +6V
EN, TCK, TMS, TDI to GND.....................................-0.3V to +4V
DBP, ABP to GND....-0.3V to the lower of +3V and (VCC + 0.3V)
TDO, GPIO_, RESET
(programmed as push-pull outputs)..... -0.3V to (VDBP + 0.3V)
Input/Output Current ..........................................................20mA
Continuous Power Dissipation (TA = +70NC)
40-Pin TQFN (derate 26.3mW/NC above +70NC)........2105mW
Operating Temperature Range........................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at VABP = VDBP = VCC = 3.3V, TA = +25NC.)
(Note 1)
PARAMETER
Operating Voltage Range
Undervoltage Lockout (Rising)
Undervoltage Lockout Hysteresis
Minimum Flash Operating
Voltage
Supply Current
SYMBOL
VCC
VUVLO
CONDITIONS
MIN
Reset output asserted low
1.2
(Note 2)
2.8
ICC
MAX
14
Minimum voltage on VCC to ensure the
device is flash configurable
2.7
VUVLO_HYS
Vflash
TYP
100
Minimum voltage on VCC to ensure flash
erase and write operations
UNITS
V
V
mV
2.7
V
No load on output pins
4.5
7
During flash writing cycle
10
14
mA
ABP Regulator Voltage
VABP
CABP = 1μF, no load, VCC = 5V
2.85
3
3.15
DBP Regulator Voltage
VDBP
CDBP = 1μF, no load, VCC = 5V
2.8
3
3.1
V
Boot Time
tBOOT
VCC > VUVLO
200
350
μs
Flash Writing Time
8-byte word
Internal Timing Accuracy
(Note 3)
EN Input Voltage
EN Input Current
Input Voltage Range
VTH_EN_R
EN voltage rising
VTH_EN_F
EN voltage falling
IEN
122
-8
ms
+8
1.41
1.365
1.39
V
1.415
%
V
-0.5
+0.5
μA
0
5.5
V
2 _______________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at VABP = VDBP = VCC = 3.3V, TA = +25NC.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
LSB
ADC DC ACCURACY
Resolution
Gain Error
ADCGAIN
Offset Error
ADCOFF
10
0.35
0.70
1
Integral Nonlinearity
ADCINL
1
LSB
Differential Nonlinearity
ADCDNL
1
LSB
50
μs
ADC Total Monitoring Cycle Time
tCYCLE
ADC IN_ Ranges
TA = +25°C
TA = -40°C to +85°C
No MON_ fault detected
40
1 LSB = 5.43mV
5.56
1 LSB = 2.72mV
2.78
1 LSB = 1.36mV
1.39
%
V
CURRENT SENSE
CSP Input-Voltage Range
VCSP
3
ICSP
Input Bias Current
ICSM
CSP Total Unadjusted Error
Overcurrent Differential
Threshold
VSENSE Fault Threshold
Hysteresis
CSPERR
OVCTH
VCSP = VCSM
VSENSE Ranges
VCSP VCSM
46
51
56
Gain = 12
94
101
108
Gain = 6
190
202
210
0.5
CMRRSNS
PSRRSNS
μA
%FSR
mV
0
3
4
5
r73h[6:5] = ‘10’
12
16
20
r73h[6:5] = ‘11’
50
64
60
Gain = 6
232
Gain = 12
116
Gain = 24
58
ms
mV
29
-2.5
Q0.2
+2.5
-4
Q0.2
+4
VSENSE = 25mV, gain = 24
Q0.5
VSENSE = 10mV, gain = 48
Q1
VCSP > 4V
V
%OVCTH
r73h[6:5] = ‘01’
VSENSE = 20mV to 100mV, VCSP = 5V,
gain = 6
Power-Supply Rejection Ratio
30.5
Gain = 24
VSENSE = 50mV, gain = 12
Common-Mode Rejection Ratio
25
2
VSENSE = 150mV (gain = 6 only)
Gain Accuracy
5
21.5
Gain = 48
ADC Current Measurement
Accuracy
3
Gain = 48
OVCHYS
OVCDEL
25
(Note 4)
r73h[6:5] = ‘00’
Secondary Overcurrent Threshold
Timeout
14
14
-1.5
+1.5
%
%
80
dB
80
dB
_______________________________________________________________________________________ 3
MAX16070/MAX16071
ELECTRICAL CHARACTERISTICS (continued)
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at VABP = VDBP = VCC = 3.3V, TA = +25NC.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUTS (RESET, GPIO_)
ISINK = 2mA
0.4
ISINK = 10mA, GPIO_ only
0.7
VCC = 1.2V, ISINK = 100μA (RESET only)
0.3
Maximum Output Sink Current
Total current into RESET, GPIO_,
VCC = 3.3V
30
mA
Output-Voltage High (Push-Pull)
ISOURCE = 100μA
1
μA
0.8
V
+1
μA
0.4
V
35
ms
0.8
V
Output-Voltage Low
VOL
2.4
V
V
Output Leakage (Open Drain)
SMBus INTERFACE
Logic-Input Low Voltage
VIL
Input voltage falling
Logic-Input High Voltage
VIH
Input voltage rising
2.0
IN = GND or VCC
-1
Input Leakage Current
Output Sink Current
Input Capacitance
SMBus Timeout
VOL
ISINK = 3mA
CIN
tTIMEOUT
V
5
SCL time low for reset
25
pF
INPUTS (A0, GPIO_)
Input Logic-Low
VIL
Input Logic-High
VIH
2.0
V
WDI Pulse Width
tWDI
100
ns
MR Pulse Width
tMR
1
μs
MR to RESET Delay
0.5
μs
MR Glitch Rejection
SMBus TIMING
100
ns
Serial Clock Frequency
fSCL
Bus Free Time Between STOP
and START Condition
tBUF
1.3
μs
START Condition Setup Time
tSU:STA
0.6
μs
START Condition Hold Time
tHD:STA
0.6
μs
STOP Condition Setup Time
tSU:STO
0.6
μs
tLOW
1.3
μs
tHIGH
0.6
μs
tSU:DAT
100
ns
Clock Low Period
Clock High Period
Data Setup Time
400
4 _______________________________________________________________________________________
kHz
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at VABP = VDBP = VCC = 3.3V, TA = +25NC.)
(Note 1)
PARAMETER
SYMBOL
Output Fall Time
tOF
Data Hold Time
tHD:DAT
Pulse Width of Spike Suppressed
CONDITIONS
MIN
TYP
CBUS = 10pF to 400pF
From 50% SCL falling to SDA change
0.3
tSP
MAX
UNITS
250
ns
0.9
μs
30
ns
JTAG INTERFACE
TDI, TMS, TCK Logic-Low Input
Voltage
VIL
Input voltage falling
TDI, TMS, TCK Logic-High Input
Voltage
VIH
Input voltage rising
TDO Logic-Output Low Voltage
VOL
ISINK = 3mA
TDO Logic-Output High Voltage
VOH
ISOURCE = 200μA
2.4
TDI, TMS Pullup Resistors
RPU
Pullup to DBP
40
I/O Capacitance
CI/O
TCK Clock Period
0.8
2
V
0.4
V
60
kω
V
50
5
t1
TCK High/Low Time
V
pF
1000
500
ns
t2, t3
50
TCK to TMS, TDI Setup Time
t4
15
ns
TCK to TMS, TDI Hold Time
t5
10
TCK to TDO Delay
t6
500
ns
TCK to TDO High-Z Delay
t7
500
ns
ns
ns
Note 1: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at TA =
+25NC and TA = +85NC. Specifications at TA = -40NC are guaranteed by design.
Note 2: For 3.3V VCC applications, connect VCC, DBP, and ABP together. For higher supply applications, connect VCC only to the
supply rail.
Note 3: Applies to RESET, fault, autoretry, sequence delays, and watchdog timeout.
Note 4: Total unadjusted error is a combination of gain, offset, and quantization error.
_______________________________________________________________________________________ 5
MAX16070/MAX16071
ELECTRICAL CHARACTERISTICS (continued)
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
SDA
tSU:DAT
tHD:DAT
tLOW
tBUF
tSU:STA
tHD:STA
tSU:STO
SCL
tHIGH
tHD:STA
tR
tF
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
Figure 1. SMBus Timing Diagram
t1
t2
t3
TCK
t4
t5
TDI, TMS
t6
t7
TDO
Figure 2. JTAG Timing Diagram
6 _______________________________________________________________________________________
START
CONDITION
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
NORMALIZED MON_ THRESHOLD
vs. TEMPERATURE
+25NC
3
-40NC
ABP AND DBP
REGULATORS ACTIVE
2
FOR LOW-VOLTAGE APPLICATIONS
VCC < 3.6V CONNECT ABP AND
DBP TO VCC
1
0
2
4
6
8
10
5.6V RANGE,
HALF SCALE,
PUV THRESHOLD
0.2
-40
14
-20
0
20
40
60
MAX16070 toc03
1.002
1.000
0.998
0.996
0.994
0.992
80
-40
-20
0
20
40
60
VCC (V)
TEMPERATURE (NC)
TEMPERATURE (NC)
TRANSIENT DURATION
vs. THRESHOLD OVERDRIVE (EN)
NORMALIZED TIMING ACCURACY
vs. TEMPERATURE
MON_ DEGLITCH
vs. TRANSIENT DURATION
100
80
60
40
0.984
0.982
0.980
0.978
0.976
120
100
0
10
1
100
80
60
40
20
0.974
20
80
MAX16070 toc06
120
0.986
TRANSIENT DURATION (µs)
MAX16070 toc04
140
0.972
-40
-20
0
20
40
60
0
80
2
4
8
16
EN OVERDRIVE (mV)
TEMPERATURE (NC)
DEGLITCH VALUE
MR TO RESET PROPAGATION DELAY
vs. TEMPERATURE
OUTPUT VOLTAGE
vs. SINK CURRENT (OUT = LOW)
OUTPUT-VOLTAGE HIGH vs.
SOURCE CURRENT (PUSH-PULL OUTPUT)
MAX
0.40
0.35
1.4
0.30
VOUT (V)
1.2
1.0
MIN
0.8
3.3
3.2
3.1
GPIO_
0.25
0.20
0.15
0.6
3.4
3.0
2.8
2.7
RESET
0.10
2.6
0.2
0.05
2.5
0
0
2.4
-20
0
20
40
TEMPERATURE (NC)
60
80
0
5
10
IOUT (mA)
GPIO_
2.9
0.4
-40
MAX16070 toc09
1.8
1.6
0.45
MAX16070 toc07
2.0
VOUT (V)
TRANSIENT DURATION (µs)
0.4
0
12
160
DELAY (µs)
0.6
MAX16070 toc05
0
0.8
1.004
MAX16070 toc08
ICC (mA)
4
1.0
1.006
NORMALIZED EN THRESHOLD
+85NC
MAX16070 toc02
5
NORMALIZED EN THRESHOLD
vs. TEMPERATURE
1.2
NORMALIZED MON_ THRESHOLD
ABP AND DBP CONNECTED TO VCC
NORMALIZED SLOT DELAY
6
MAX16070 toc01
VCC SUPPLY CURRENT
vs. VCC SUPPLY VOLTAGE
15
20
RESET
0
500
1000
1500
IOUT (µA)
_______________________________________________________________________________________ 7
MAX16070/MAX16071
Typical Operating Characteristics
(Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE
DIFFERENTIAL NONLINEARITY vs. CODE
0.6
0.8
0.6
0.4
0.2
0.2
DNL (LSB)
0.4
0
-0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
128 256 384 512 640 768 896 1024
0
128 256 384 512 640 768 896 1024
CODE (LSB)
CODE (LSB)
NORMALIZED CURRENT-SENSE
ACCURACY vs. TEMPERATURE
CURRENT-SENSE ACCURACY
vs. CSP-CSM VOLTAGE
1.0
MAX16070 toc12
1.05
1.03
200mV
MAX16070 toc13
0
0.8
0.6
0.4
25mV
ERROR (mV)
1.01
0.99
0.2
0
-0.2
-0.4
100mV
-0.6
0.97
-0.8
-1.0
0.95
-40
10
0
60
5
10
15
20
25
TEMPERATURE (NC)
CSP-CSM VOLTAGE (mV)
CURRENT-SENSE TRANSIENT DURATION
vs. CSP-CSM OVERDRIVE
RESET OUTPUT CURRENT
vs. SUPPLY VOLTAGE
18
MAX16070 toc14
1.8
1.6
1.2
1.0
0.8
0.6
14
12
8
6
4
0.2
2
0
0
20
40
60
80
CSP-CSM OVERDRIVE (mV)
100
ABP AND DBP
REGULATORS ACTIVE
10
0.4
0
ABP AND DBP
CONNECTED TO VCC
16
OUTPUT CURRENT (mA)
1.4
30
MAX16070 toc15
NORMALIZED CURRENT-SENSE ACCURACY
MAX16070 toc11
0.8
INL (LSB)
1.0
MAX16070 toc10
1.0
TRANSIENT DURATION (Fs)
MAX16070/MAX16071
12-Channel/8-Channel Flash-Configurable System
Monitors with Nonvolatile Fault Registers
VRESET = 0.3V
0
2
4
6
8
10
SUPPLY VOLTAGE (V)
12
8 _______________________________________________________________________________________
14
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
PIN
NAME
FUNCTION
MAX16070
MAX16071
1–5, 34, 35,
40
1–5, 36, 37,
40
MON2–MON6,
MON7, MON8,
MON1
6
6
CSP
Current-Sense Amplifier Positive Input. Connect CSP to the source side of the
external sense resistor.
7
7
CSM
Current-Sense Amplifier Negative Input. Connect CSM to the load side of the
external sense resistor.
8
8
RESET
9
9
TMS
JTAG Test Mode Select
10
10
TDI
JTAG Test Data Input
11
11
TCK
JTAG Test Clock
12
12
TDO
JTAG Test Data Output
13
13
SDA
SMBus Serial-Data Open-Drain Input/Output
14
14
A0
15
15
SCL
SMBus Serial Clock Input
16, 33
16, 35
GND
Ground
Monitor Voltage Input 1–Monitor Voltage Input 8. Set monitor voltage range
through configuration registers. Measured value written to the ADC register
can be read back through the SMBus or JTAG interface.
Configurable Reset Output
Four-State SMBus Address. Address sampled upon POR.
17, 18
—
GPIO7, GPIO8
General-Purpose Input/Output 7 and General-Purpose Input/Output 8.
GPIO_s can be configured to act as a TTL input, a push-pull, open-drain, or
high-impedance output or a pulldown circuit during a fault event or reverse
sequencing.
19–24
17–22
GPIO1–GPIO6
General-Purpose Input/Output 1–General-Purpose Input/Output 6. GPIO_s
can be configured to act as a TTL input, a push-pull, open-drain, or highimpedance output or a pulldown circuit during a fault event.
25, 26, 27, 29
23–28,
30, 38, 39
N.C.
28
29
EN
30
31, 32
DBP
Digital Bypass. All push-pull outputs are referenced to DBP. Bypass DBP with
a 1FF capacitor to GND.
31
33
VCC
Device Power Supply. Connect VCC to a voltage from 2.8V to 14V. Bypass
VCC with a 10FF capacitor to GND.
32
34
ABP
Analog Bypass. Bypass ABP with a 1FF ceramic capacitor to GND.
36–39
—
MON9–
MON12
Monitor Voltage Input 9–Monitor Voltage Input 12. Set monitor voltage range
through configuration registers. Measured value written to the ADC register
can be read back through the SMBus or JTAG interface.
—
—
EP
Exposed Pad. Internally connected to GND. Connect to ground, but do not
use as the main ground connection.
No Connection. Not internally connected.
Analog Enable Input. All outputs deassert when VEN is below the enable
threshold.
_______________________________________________________________________________________ 9
MAX16070/MAX16071
Pin Description
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Functional Diagram
VCC
ABP
DBP
OVERC
RESET
MAX16070
MAX16071
ANY_FAULT
FAULT1
DECODE
LOGIC
FAULT2
MR
EN
MARGIN
1.4V
CSP
WDI
WATCHDOG
TIMER
AV
CSM
WDO
VCSTH
GPIO1–GPIO8
RESET
G
P
I
O
C
O
N
T
R
O
L
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
REF
MON1–
MON12
VOLTAGE
SCALING
AND
MUX
10-BIT ADC
(SAR)
ADC
REGISTERS
DIGITAL
COMPARATORS
RAM
REGISTERS
SMBus INTERFACE
AO
SCL
SDA
JTAG
INTERFACE
FLASH
MEMORY
GND
TDO
TDI
TCK
TMS
10 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
The MAX16070 monitors up to twelve system power supplies and the MAX16071 can monitor up to eight system
power supplies. After boot-up, if EN is high and the software enable bit is set to ‘1,’ monitoring begins based on
the configuration stored in flash. An internal multiplexer
cycles through each MON_ input. At each multiplexer
stop, the 10-bit ADC converts the monitored analog voltage to a digital result and stores the result in a register.
Each time a conversion cycle (50Fs, max) completes,
internal logic circuitry compares the conversion results
to the overvoltage and undervoltage thresholds stored in
memory. When a result violates a programmed threshold,
the conversion can be configured to generate a fault.
GPIO_ can be programmed to assert on combinations
of faults. Additionally, faults can be configured to shut off
the system and trigger the nonvolatile fault logger, which
writes all fault information automatically to the flash and
write-protects the data to prevent accidental erasure.
The MAX16070/MAX16071 contain both SMBus and
JTAG serial interfaces for accessing registers and flash.
Use only one interface at any given time. For more information on how to access the internal memory through
these interfaces, see the SMBus-Compatible Interface
and JTAG Serial Interface sections. The memory map
is divided into three pages with access controlled by
special SMBus and JTAG commands.
The factory-default values at POR (power-on reset) for all
RAM registers are ‘0’s. POR occurs when VCC reaches
the undervoltage-lockout threshold (UVLO) of 2.8V (max).
At POR, the device begins a boot-up sequence. During
the boot-up sequence, all monitored inputs are masked
from initiating faults and flash contents are copied to
the respective register locations. During boot-up, the
MAX16070/MAX16071 are not accessible through the
serial interface. The boot-up sequence takes up to
150Fs, after which the device is ready for normal operation. RESET is asserted low up to the boot-up phase and
remains asserted for its programmed timeout period once
sequencing is completed and all monitored channels
are within their respective thresholds. Up to the boot-up
phase, the GPIO_s are high impedance.
Power
Apply 2.8V to 14V to VCC to power the MAX16070/
MAX16071. Bypass VCC to ground with a 10FF capacitor. Two internal voltage regulators, ABP and DBP,
supply power to the analog and digital circuitry within
the device. For operation at 3.6V or lower, disable the
regulators by connecting ABP and DBP to VCC.
ABP is a 3.0V (typ) voltage regulator that powers the internal analog circuitry. Bypass ABP to GND with a 1FF ceramic capacitor installed as close to the device as possible.
DBP is an internal 3.0V (typ) voltage regulator. DBP powers flash and digital circuitry. All push-pull outputs refer to
DBP. Bypass the DBP output to GND with a 1FF ceramic
capacitor installed as close as possible to the device.
Do not power external circuitry from ABP or DBP.
Enable
To enable monitoring, the voltage at EN must be above
1.4V and the software enable bit in r73h[0] must be set
to ‘1.’ To power down and disable monitoring, either pull
EN below 1.35V or set the Software Enable bit to ‘0.’
See Table 1 for the software enable bit configurations.
Connect EN to ABP if not used.
Table 1. Software Enable Configurations
REGISTER
ADDRESS
73h
FLASH
ADDRESS
273h
BIT RANGE
DESCRIPTION
[0]
Software enable
[1]
Reserved
[2]
1 = Margin mode enabled
[3]
Early warning threshold select
0 = Early warning is undervoltage
1 = Early warning is overvoltage
[4]
Independent watchdog mode enable
1 = Watchdog timer is independent of sequencer
0 = Watchdog timer boots after sequence completes
______________________________________________________________________________________ 11
MAX16070/MAX16071
Detailed Description
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
When in the monitoring state, a register bit, ENRESET,
is set to a ‘1’ when EN falls below the undervoltage
threshold. This register bit latches and must be cleared
through software. This bit indicates if RESET asserted
low due to EN going under the threshold. The POR state
of ENRESET is ‘0’. The bit is only set on a falling edge
of the EN comparator output or the software enable bit.
Voltage/Current Monitoring
The MAX16070/MAX16071 feature an internal 10-bit
ADC that monitors the MON_ voltage inputs. An internal
multiplexer cycles through each of the enabled inputs,
taking less than 40Fs for a complete monitoring cycle.
Each acquisition takes approximately 3.2Fs. At each
multiplexer stop, the 10-bit ADC converts the analog
input to a digital result and stores the result in a register.
ADC conversion results are stored in registers r00h to
r1Ah (see Table 6). Use the SMBus or JTAG serial interface to read ADC conversion results.
The MAX16070 provides twelve inputs, MON1 to MON12,
for voltage monitoring. The MAX16071 provides eight
inputs, MON1 to MON8, for voltage monitoring. Each
input voltage range is programmable in registers r43h to
r45h (see Table 5). When MON_ configuration registers
are set to ’11,’ MON_ voltages are not monitored, and
the multiplexer does not stop at these inputs, decreasing
the total cycle time. These inputs cannot be configured
to trigger fault conditions.
RS
POWER
SUPPLY
The three programmable thresholds for each monitored
voltage include an overvoltage, an undervoltage, and a
secondary warning threshold that can be set in r73h[3]
to be either an undervoltage or overvoltage threshold.
See the Faults section for more information on setting
overvoltage and undervoltage thresholds. All voltage
thresholds are 8 bits wide. The 8 MSBs of the 10-bit ADC
conversion result are compared to these overvoltage
and undervoltage thresholds.
Inputs that are not enabled are not converted by the
ADC; they contain the last value acquired before that
channel was disabled.
The ADC conversion result registers are reset to 00h at
boot-up. These registers are not reset when a reboot
command is executed.
Configure the MAX16070/MAX16071 for differential
mode in r46h (Table 5). The possible differential pairs
are MON1/MON2, MON3/MON4, MON5/MON6, MON7/
MON8, MON9/MON10, MON11/MON12 with the first
input always being at a higher voltage than the second.
Use differential voltage sensing to eliminate voltage offsets or measure supply current. See Figure 3. In differential mode, the odd-numbered MON_ input measures
the absolute voltage with respect to GND while the result
of the even input is the difference between the odd and
even inputs. See Figure 3 for the typical differential measurement circuit.
ILOAD
VMON
CSP
MONEVEN
MONODD
RSENSE
-
CSM
TO ADC MUX
*AV
+
MAX16070
MAX16071
MAX16070
LOAD
MONODD
-
MONEVEN
OVERC
+
+
-
POWER
SUPPLY
*VCSTH
LOAD
*ADJUSTABLE BY r47h [3:2]
Figure 3. Differential Measurement Connections
Figure 4. Current-Sense Amplifier
12 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Internal Current-Sense Amplifier
The current-sense inputs, CSP/CSM, and a currentsense amplifier facilitate power monitoring (see Figure
4). The voltage on CSP relative to GND is also monitored
by the ADC when the current-sense amplifier is enabled
with r47h[0]. The conversion results are located in registers r19h and r1Ah (see Table 6). There are two selectable voltage ranges for CSP set by r47h[1], see Table
4. Although the voltage can be monitored over SMBus
or JTAG, this voltage has no threshold comparators and
cannot trigger any faults. Regarding the current-sense
amplifier, there are four selectable ranges and the ADC
output for a current-sense conversion is:
XADC = (VSENSE x AV)/1.4V x (28 - 1)
where XADC is the 8-bit decimal ADC result in register
r18h, VSENSE is VCSP - VCSM, and AV is the currentsense voltage gain set by r47h[3:2].
In addition, there are two programmable current-sense
trip thresholds: primary overcurrent and secondary overcurrent. For fast fault detection, the primary overcurrent
threshold is implemented with an analog comparator
connected to the internal OVERC signal. The OVERC
signal can be output on one of the GPIO_s. See the
General-Purpose Inputs/Outputs section for configuring the GPIO_ to output the OVERC signal. The primary
threshold is set by:
ITH = VCSTH/RSENSE
where ITH is the current threshold to be set, VCSTH is
the threshold set by r47h[3:2], and RSENSE is the value
of the sense resistor. See Table 4 for a description of
r47h. OVERC depends only on the primary overcurrent
threshold. The secondary overcurrent threshold is implemented through ADC conversions and digital comparison set by r6Ch. The secondary overcurrent threshold
includes programmable time delay options located in
r73h[6:5]. Primary and secondary current-sense faults
are enabled/disabled through r47h[0].
Table 2. Boot-Up Delay Register
REGISTER
ADDRESS
FLASH
ADDRESS
77h
277h
BIT RANGE
DESCRIPTION
[3:0]
Boot-up delay
[7:0]
Reserved
Table 3. Boot-Up Delay Values
CODE
VALUE
0000
25Fs
0001
500Fs
0010
1ms
0011
2ms
0100
3ms
0101
4ms
0110
6ms
0111
8ms
1000
10ms
1001
12ms
1010
25ms
1011
100ms
1100
200ms
1101
400ms
1110
800ms
1111
1.6s
______________________________________________________________________________________ 13
MAX16070/MAX16071
Boot-Up Delay
Once EN is above its threshold and the software-enable
bit is set, a boot-up delay occurs before monitoring
begins. This delay is configured in register r77h[3:0] as
shown in Tables 2 and 3.
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 4. Overcurrent Primary Threshold and Current-Sense Control
REGISTER
ADDRESS
47h
FLASH
ADDRESS
BIT
RANGE
[0]
1 = Current sense is enabled
0 = Current sense is disabled
[1]
1 = CSP full-scale range is 14V
0 = CSP full-scale range is 7V
247h
73h
273h
DESCRIPTION
[3:2]
Overcurrent primary threshold and current-sense gain setting
00 = 200mV threshold, AV = 6V/V
01 = 100mV threshold, AV = 12V/V
10 = 50mV threshold, AV = 24V/V
11 = 25mV threshold, AV = 48V/V
[6:5]
Overcurrent secondary threshold deglitch
00 = No delay
01 = 14ms
10 = 15ms
11 = 60ms
Table 5. ADC Configuration Registers
REGISTER ADDRESS
43h
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
[1:0]
ADC1 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
[3:2]
ADC2 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
[5:4]
ADC3 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
[7:6]
ADC4 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
243h
14 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
REGISTER ADDRESS
44h
45h
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
[1:0]
ADC5 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
[3:2]
ADC6 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
[5:4]
ADC7 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
[7:6]
ADC8 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
[1:0]
ADC9 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
[3:2]
ADC10 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
[5:4]
ADC11 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
[7:6]
ADC12 full-scale range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = Channel not converted
244h
245h
______________________________________________________________________________________ 15
MAX16070/MAX16071
Table 5. ADC Configuration Registers (continued)
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 5. ADC Configuration Registers (continued)
REGISTER ADDRESS
46h
FLASH
ADDRESS
BIT RANGE
DESCRIPTION
[0]
Differential conversion ADC1, ADC2
0 = Disabled
1 = Enabled
[1]
Differential conversion ADC3, ADC4
0 = Disabled
1 = Enabled
[2]
Differential conversion ADC5, ADC6
0 = Disabled
1 = Enabled
[3]
Differential conversion ADC7, ADC8
0 = Disabled
1 = Enabled
[4]
Differential conversion ADC9, ADC10
0 = Disabled
1 = Enabled
[5]
Differential conversion ADC11, ADC12
0 = Disabled
1 = Enabled
246h
16 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
REGISTER ADDRESS
BIT RANGE
00h
[7:0]
ADC1 result (MSB) bits 9–2
DESCRIPTION
01h
[7:6]
ADC1 result (LSB) bits 1, 0
02h
[7:0]
ADC2 result (MSB) bits 9–2
03h
[7:6]
ADC2 result (LSB) bits 1, 0
04h
[7:0]
ADC3 result (MSB) bits 9–2
05h
[7:6]
ADC3 result (LSB) bits 1, 0
06h
[7:0]
ADC4 result (MSB) bits 9–2
07h
[7:6]
ADC4 result (LSB) bits 1, 0
08h
[7:0]
ADC5 result (MSB) bits 9–2
09h
[7:6]
ADC5 result (LSB) bits 1, 0
0Ah
[7:0]
ADC6 result (MSB) bits 9–2
0Bh
[7:6]
ADC6 result (LSB) bits 1, 0
0Ch
[7:0]
ADC7 result (MSB) bits 9–2
0Dh
[7:6]
ADC7 result (LSB) bits 1, 0
0Eh
[7:0]
ADC8 result (MSB) bits 9–2
0Fh
[7:6]
ADC8 result (LSB) bits 1, 0
10h
[7:0]
ADC9 result (MSB) bits 9–2
11h
[7:6]
ADC9 result (LSB) bits 1, 0
12h
[7:0]
ADC10 result (MSB) bits 9–2
13h
[7:6]
ADC10 result (LSB) bits 1, 0
14h
[7:0]
ADC11 result (MSB) bits 9–2
15h
[7:6]
ADC11 result (LSB) bits 1, 0
16h
[7:0]
ADC12 result (MSB) bits 9–2
17h
[7:6]
ADC12 result (LSB) bits 1, 0
18h
[7:0]
Current-sense ADC result
19h
[7:0]
CSP ADC output (MSB) bits 9–2
1Ah
[7:6]
CSP ADC output (LSB) bits 1, 0
______________________________________________________________________________________ 17
MAX16070/MAX16071
Table 6. ADC Conversion Results (Read Only)
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
General-Purpose Inputs/Outputs
GPIO1 to GPIO8 are programmable general-purpose
inputs/outputs. GPIO1–GPIO8 are configurable as a
manual reset input, a watchdog timer input and output,
logic inputs/outputs, fault-dependent outputs. When programmed as outputs, GPIO_s are open drain or pushpull. See Tables 8 and 9 for more detailed information on
configuring GPIO1 to GPIO8.
When GPIO1 to GPIO8 are configured as general-purpose inputs/outputs, read values from the GPIO_ ports
through r1Eh and write values to GPIO_s through r3Eh.
Note that r3Eh has a corresponding flash register, which
programs the default state of a general-purpose output.
See Table 7 for more information on reading and writing
to the GPIO_.
Table 7. GPIO_ State Registers
REGISTER
ADDRESS
1Eh
3Eh
FLASH
ADDRESS
—
23Eh
BIT RANGE
DESCRIPTION
[0]
GPIO1 input state
[1]
GPIO2 input state
[2]
GPIO3 input state
[3]
GPIO4 input state
[4]
GPIO5 input state
[5]
GPIO6 input state
[6]
GPIO7 input state
[7]
GPIO8 input state
[0]
GPIO1 output state
[1]
GPIO2 output state
[2]
GPIO3 output state
[3]
GPIO4 output state
[4]
GPIO5 output state
[5]
GPIO6 output state
[6]
GPIO7 output state
[7]
GPIO8 output state
Table 8. GPIO_ Configuration Registers
REGISTER
ADDRESS
FLASH
ADDRESS
3Fh
23Fh
40h
41h
240h
241h
BIT RANGE
DESCRIPTION
[2:0]
GPIO1 configuration
[5:3]
GPIO2 configuration
[7:6]
GPIO3 configuration (LSB)
[0]
GPIO3 configuration (MSB)
[3:1]
GPIO4 configuration
[6:4]
GPIO5 configuration
[7]
GPIO6 configuration (LSB)
[1:0]
GPIO6 configuration (MSB)
[4:2]
GPIO7 configuration
[7:5]
GPIO8 configuration
18 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
[0]
[1]
[2]
[3]
42h
242h
[4]
[5]
[6]
[7]
MAX16070/MAX16071
Table 8. GPIO_ Configuration Registers (continued)
DESCRIPTION
Output configuration for GPIO1
0 = Push-pull
1 = Open drain
Output configuration for GPIO2
0 = Push-pull
1 = Open drain
Output configuration for GPIO3
0 = Push-pull
1 = Open drain
Output configuration for GPIO4
0 = Push-pull
1 = Open drain
Output configuration for GPIO5
0 = Push-pull
1 = Open drain
Output configuration for GPIO6
0 = Push-pull
1 = Open drain
Output configuration for GPIO7
0 = Push-pull
1 = Open drain
Output configuration for GPIO8
0 = Push-pull
1 = Open drain
Table 9. GPIO_ Function Configuration Bits
CODE
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
000
Logic input
Logic
input
Logic input
Logic input
Logic input
Logic
input
Logic input
Logic input
001
Logic output
Logic
output
Logic output
Logic output
Logic output
Logic
output
Logic output
Logic output
010
Fault2 output
Fault2
output
Fault2 output
Fault2 output
Fault2 output
Fault2
output
Fault2 output
Fault2
output
011
Fault1 output
Fault1
output
—
Fault1 output
Fault1 output
Fault1
output
Fault1 output
—
100
ANY_FAULT
output
—
ANY_FAULT
output
ANY_FAULT
output
ANY_FAULT
output
—
ANY_FAULT
output
—
101
OVERC
output
OVERC
output
OVERC
output
OVERC
output
OVERC
output
OVERC
output
OVERC
output
OVERC
output
110
MR input
WDO
output
MR input
WDO output
MR input
WDO
output
MR input
WDO output
111
WDI input
—
—
EXTFAULT
input/output
—
MARGIN
input
—
EXTFAULT
input/output
______________________________________________________________________________________ 19
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Fault1 and Fault2
GPIO1 to GPIO8 are configurable as dedicated fault outputs, Fault1 or Fault2. Fault outputs can assert on one or
more overvoltage, undervoltage, or early warning conditions for selected inputs, as well as the secondary overcurrent comparator. Fault1 and Fault2 dependencies
are set using registers r36h to r3Ah. See Table 10. When
a fault output depends on more than one MON_, the
fault output asserts when one or more MON_ exceeds a
programmed threshold voltage. These fault outputs act
independently of the critical fault system, described in
the Critical Faults section.
Table 10. Fault1 and Fault2 Dependencies
REGISTER
ADDRESS
36h
37h
38h
FLASH
ADDRESS
236h
BIT
RANGE
0
1 = Fault1 depends on MON1
1
1 = Fault1 depends on MON2
2
1 = Fault1 depends on MON3
3
1 = Fault1 depends on MON4
4
1 = Fault1 depends on MON5
5
1 = Fault1 depends on MON6
6
1 = Fault1 depends on MON7
7
1 = Fault1 depends on MON8
0
1 = Fault1 depends on MON9
1
1 = Fault1 depends on MON10
2
1 = Fault1 depends on MON11
3
1 = Fault1 depends on MON12
4
1 = Fault1 depends on the overvoltage thresholds of the inputs selected by
r36h and r37h[3:0]
5
1 = Fault1 depends on the undervoltage thresholds of the inputs selected by
r36h and r37h[3:0]
6
1 = Fault1 depends on the early warning thresholds of the inputs selected by
r36h and r37h[3:0]
7
0 = Fault1 is an active-low digital output
1 = Fault1 is an active-high digital output
237h
238h
DESCRIPTION
[0]
1 = Fault2 depends on MON1
[1]
1 = Fault2 depends on MON2
[2]
1 = Fault2 depends on MON3
[3]
1 = Fault2 depends on MON4
[4]
1 = Fault2 depends on MON5
[5]
1 = Fault2 depends on MON6
[6]
1 = Fault2 depends on MON7
[7]
1 = Fault2 depends on MON8
20 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
REGISTER
ADDRESS
39h
3Ah
FLASH
ADDRESS
BIT
RANGE
[0]
1 = Fault2 depends on MON9
[1]
1 = Fault2 depends on MON10
[2]
1 = Fault2 depends on MON11
[3]
1 = Fault2 depends on MON12
[4]
1 = Fault2 depends on the overvoltage thresholds of the inputs selected by
r38h and r39h[3:0]
[5]
1 = Fault2 depends on the undervoltage thresholds of the inputs selected by
r38h and r39h[3:0]
[6]
1 = Fault2 depends on the early warning thresholds of the inputs selected by
r38h and r39h[3:0]
[7]
0 = Fault2 is an active-low digital output
1 = Fault2 is an active-high digital output
[0]
1 = Fault1 depends on secondary overcurrent comparator
[1]
1 = Fault2 depends on secondary overcurrent comparator
239h
23Ah
DESCRIPTION
[7:2]
Reserved
ANY_FAULT
GPIO1, GPIO3, GPIO4, GPIO5, and GPIO7 are configurable to assert low during any fault condition.
Overcurrent Comparator (OVERC)
GPIO1 to GPIO8 are configurable to assert low when
the voltage across CSP and CSM exceed the primary
overcurrent threshold. See the Internal Current-Sense
Amplifier section for more details.
Manual Reset (MR)
GPIO1, GPIO3, GPIO5, and GPIO7 are configurable to act
as an active-low manual reset input, MR. Drive MR low to
assert RESET. RESET remains asserted for the selected
reset timeout period after MR transitions from low to high.
Watchdog Input (WDI) and Output (WDO)
GPIO2, GPIO4, GPIO6, and GPIO8 are configurable as
the watchdog timer output, WDO. GPIO1 is configurable
as WDI. See Table 17 for configuration details. WDO is an
active-low output. See the Watchdog Timer section for more
information about the operation of the watchdog timer.
External Fault (EXTFAULT)
GPIO4 and GPIO8 are configurable as the external fault
input/output. When configured as push-pull, EXTFAULT
signals that a critical fault has occurred on one or more
monitored voltages or current. When configured as
open-drain, EXTFAULT can be asserted low by an external circuit to trigger a critical fault. This signal can be
used to cascade multiple MAX16070/MAX16071s.
One configuration bit determines the behavior of the
MAX16070/MAX16071 when EXTFAULT is pulled low by
some other device. If register bit r6Dh[2] is set, EXTFAULT
going low triggers a nonvolatile fault log operation.
Faults
The MAX16070/MAX16071 monitor the input (MON_)
channels and compare the results with an overvoltage
threshold, an undervoltage threshold, and a selectable
overvoltage or undervoltage early warning threshold.
Based on these conditions, the MAX16070/MAX16071
assert various fault outputs and save specific information about the channel conditions and voltages into the
nonvolatile flash. Once a critical fault event occurs, the
failing channel condition, ADC conversions at the time of
the fault, or both can be saved by configuring the event
logger. The event logger records a single failure in the
internal flash and sets a lock bit that protects the stored
fault data from accidental erasure on a subsequent
power-up.
An overvoltage event occurs when the voltage at a monitored input exceeds the overvoltage threshold for that
input. An undervoltage event occurs when the voltage
at a monitored input falls below the undervoltage threshold. Fault thresholds are set in registers r48h to r6Ch as
shown in Table 11. Disabled inputs are not monitored for
fault conditions and are skipped over by the input multiplexer. Only the upper 8 bits of a conversion result are
compared with the programmed fault thresholds.
______________________________________________________________________________________ 21
MAX16070/MAX16071
Table 10. Fault1 and Fault2 Dependencies (continued)
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 11. Fault Threshold Registers
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
48h
248h
[7:0]
MON1 secondary threshold
49h
249h
[7:0]
MON1 overvoltage threshold
4Ah
24Ah
[7:0]
MON1 undervoltage threshold
4Bh
24Bh
[7:0]
MON2 secondary threshold
4Ch
24Ch
[7:0]
MON2 overvoltage threshold
4Dh
24Dh
[7:0]
MON2 undervoltage threshold
4Eh
24Eh
[7:0]
MON3 secondary threshold
4Fh
24Fh
[7:0]
MON3 overvoltage threshold
50h
250h
[7:0]
MON3 undervoltage threshold
51h
251h
[7:0]
MON4 secondary threshold
52h
252h
[7:0]
MON4 overvoltage threshold
53h
253h
[7:0]
MON4 undervoltage threshold
54h
254h
[7:0]
MON5 secondary threshold
55h
255h
[7:0]
MON5 overvoltage threshold
56h
256h
[7:0]
MON5 undervoltage threshold
57h
257h
[7:0]
MON6 secondary threshold
58h
258h
[7:0]
MON6 overvoltage threshold
59h
259h
[7:0]
MON6 undervoltage threshold
5Ah
25Ah
[7:0]
MON7 secondary threshold
5Bh
25Bh
[7:0]
MON7 overvoltage threshold
5Ch
25Ch
[7:0]
MON7 undervoltage threshold
5Dh
25Dh
[7:0]
MON8 secondary threshold
5Eh
25Eh
[7:0]
MON8 overvoltage threshold
5Fh
25Fh
[7:0]
MON8 undervoltage threshold
60h
260h
[7:0]
MON9 secondary threshold
61h
261h
[7:0]
MON9 overvoltage threshold
62h
262h
[7:0]
MON9 undervoltage threshold
63h
263h
[7:0]
MON10 secondary threshold
64h
264h
[7:0]
MON10 overvoltage threshold
65h
265h
[7:0]
MON10 undervoltage threshold
66h
266h
[7:0]
MON11 secondary threshold
67h
267h
[7:0]
MON11 overvoltage threshold
68h
268h
[7:0]
MON11 undervoltage threshold
69h
269h
[7:0]
MON12 secondary threshold
6Ah
26Ah
[7:0]
MON12 overvoltage threshold
6Bh
26Bh
[7:0]
MON12 undervoltage threshold
6Ch
26Ch
[7:0]
Secondary overcurrent threshold
DESCRIPTION
22 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Deglitch
Fault conditions are detected at the end of each conversion. When the voltage on an input falls outside a monitored threshold for one acquisition, the input multiplexer
remains on that channel and performs several successive conversions. To trigger a fault, the input must stay
outside the threshold for a certain number of acquisitions
as determined by the deglitch setting in r73h[6:5] and
r74h[6:5] (see Table 12).
Fault Flags
Fault flags indicate the fault status of a particular input.
The fault flag of any monitored input in the device can be
read at any time from registers r1Bh and r1Ch, as shown
in Table 13. Clear a fault flag by writing a ‘1’ to the appropriate bit in the flag register. Unlike the fault signals sent
to the fault outputs, these bits are masked by the Critical
Fault Enable bits (see Table 14). The fault flag is only set
when the matching enable bit in the critical fault enable
register is also set.
Table 12. Deglitch Configuration
REGISTER
ADDRESS
FLASH
ADDRESS
73h
273h
74h
274h
BIT RANGE
DESCRIPTION
[6:5]
Overcurrent comparator deglitch time
00 = No deglitch
01 = 4ms
10 = 15ms
11 = 60ms
[6:5]
Voltage comparator deglitch configuration
00 = 2 cycles
01 = 4 cycles
10 = 8 cycles
11 = 16 cycles
Table 13. Fault Flags
REGISTER
ADDRESS
1Bh
1Ch
BIT RANGE
DESCRIPTION
[0]
MON1
[1]
MON2
[2]
MON3
[3]
MON4
[4]
MON5
[5]
MON6
[6]
MON7
[7]
MON8
[0]
MON9
[1]
MON10
[2]
MON11
[3]
MON12
[4]
Overcurrent
[5]
External fault (EXTFAULT)
SMB alert
[6]
______________________________________________________________________________________ 23
MAX16070/MAX16071
The general-purpose inputs/outputs (GPIO1 to GPIO8)
can be configured as ANY_FAULT outputs or dedicated
Fault1 and Fault2 outputs to indicate fault conditions.
These fault outputs are not masked by the critical fault
enable bits shown in Table 14. See the General-Purpose
Inputs/Outputs section for more information on configuring GPIO_s as fault outputs.
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 14. Critical Fault Configuration
REGISTER
ADDRESS
FLASH
ADDRESS
BIT
RANGE
[1:0]
6Dh
26Dh
[2]
[7:3]
6Eh
6Fh
70h
71h
26Eh
26Fh
270h
271h
DESCRIPTION
Fault information to log
00 = Save failed line flags and ADC values in flash
01 = Save only failed line flags in flash
10 = Save only ADC values in flash
11 = Do not save anything
1 = Fault log triggered when EXTFAULT is pulled low externally
Not used
[0]
1 = Fault log triggered when MON1 is below its undervoltage threshold
[1]
1 = Fault log triggered when MON2 is below its undervoltage threshold
[2]
1 = Fault log triggered when MON3 is below its undervoltage threshold
[3]
1 = Fault log triggered when MON4 is below its undervoltage threshold
[4]
1 = Fault log triggered when MON5 is below its undervoltage threshold
[5]
1 = Fault log triggered when MON6 is below its undervoltage threshold
[6]
1 = Fault log triggered when MON7 is below its undervoltage threshold
[7]
1 = Fault log triggered when MON8 is below its undervoltage threshold
[0]
1 = Fault log triggered when MON9 is below its undervoltage threshold
[1]
1 = Fault log triggered when MON10 is below its undervoltage threshold
[2]
1 = Fault log triggered when MON11 is below its undervoltage threshold
[3]
1 = Fault log triggered when MON12 is below its undervoltage threshold
[4]
1 = Fault log triggered when MON1 is above its overvoltage threshold
[5]
1 = Fault log triggered when MON2 is above its overvoltage threshold
[6]
1 = Fault log triggered when MON3 is above its overvoltage threshold
[7]
1 = Fault log triggered when MON4 is above its overvoltage threshold
[0]
1 = Fault log triggered when MON5 is above its overvoltage threshold
[1]
1 = Fault log triggered when MON6 is above its overvoltage threshold
[2]
1 = Fault log triggered when MON7 is above its overvoltage threshold
[3]
1 = Fault log triggered when MON8 is above its overvoltage threshold
[4]
1 = Fault log triggered when MON9 is above its overvoltage threshold
[5]
1 = Fault log triggered when MON10 is above its overvoltage threshold
[6]
1 = Fault log triggered when MON11 is above its overvoltage threshold
[7]
1 = Fault log triggered when MON12 is above its overvoltage threshold
[0]
1 = Fault log triggered when MON1 is above/below the early threshold warning
[1]
1 = Fault log triggered when MON2 is above/below the early threshold warning
[2]
1 = Fault log triggered when MON3 is above/below the early threshold warning
[3]
1 = Fault log triggered when MON4 is above/below the early threshold warning
[4]
1 = Fault log triggered when MON5 is above/below the early threshold warning
[5]
1 = Fault log triggered when MON6 is above/below the early threshold warning
[6]
1 = Fault log triggered when MON7 is above/below the early threshold warning
[7]
1 = Fault log triggered when MON8 is above/below the early threshold warning
24 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
REGISTER
ADDRESS
72h
FLASH
ADDRESS
BIT
RANGE
272h
DESCRIPTION
[0]
1 = Fault log triggered when MON9 is above/below the early threshold warning
[1]
1 = Fault log triggered when MON10 is above/below the early threshold warning
[2]
1 = Fault log triggered when MON11 is above/below the early threshold warning
[3]
1 = Fault log triggered when MON12 is above/below the early threshold warning
[4]
1 = Fault log triggered when overcurrent early threshold is exceeded
[5]
[7:6]
Reserved, must be set to ‘1’
Reserved
If a GPIO_ is configured as an open-drain EXTFAULT
input/output, and EXTFAULT is pulled low by an external
circuit, bit r1Ch[5] is set.
The SMB Alert bit is set if the MAX16070/MAX16071
have asserted the SMBus Alert output. Clear by writing a
‘1’. See SMBALERT section for more details.
Critical Faults
During normal operation, a fault condition can be configured to store fault information in the flash memory by
setting the appropriate critical fault enable bits. Set the
appropriate critical fault enable bits in registers r6Eh to r72h
(see Table 14) for a fault condition to trigger a critical fault.
Logged fault information is stored in flash registers r200h
to r20Fh (see Table 15). After fault information is logged,
the flash is locked and must be unlocked to enable a
new fault log to be stored. Write a ‘0’ to r8Ch[1] to unlock
the fault flash. Fault information can be configured to
store ADC conversion results and/or fault flags in registers. Select the critical fault configuration in r6Dh[1:0].
Set r6Dh[1:0] to ‘11’ to turn off the fault logger. All stored
ADC results are 8 bits wide.
Table 15. Nonvolatile Fault Log Registers
FLASH ADDRESS
200h
201h
202h
BIT RANGE
DESCRIPTION
—
Reserved
[0]
Fault log triggered on MON1
[1]
Fault log triggered on MON2
[2]
Fault log triggered on MON3
[3]
Fault log triggered on MON4
[4]
Fault log triggered on MON5
[5]
Fault log triggered on MON6
[6]
Fault log triggered on MON7
[7]
Fault log triggered on MON8
[0]
Fault log triggered on MON9
[1]
Fault log triggered on MON10
[2]
Fault log triggered on MON11
[3]
Fault log triggered on MON12
[4]
Fault log triggered on overcurrent
[5]
Fault log triggered on EXTFAULT
Not used
[7:6]
______________________________________________________________________________________ 25
MAX16070/MAX16071
Table 14. Critical Fault Configuration (continued)
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 15. Nonvolatile Fault Log Registers (continued)
FLASH ADDRESS
BIT RANGE
203h
[7:0]
MON1 ADC output
DESCRIPTION
204h
[7:0]
MON2 ADC output
205h
[7:0]
MON3 ADC output
206h
[7:0]
MON4 ADC output
207h
[7:0]
MON5 ADC output
208h
[7:0]
MON6 ADC output
209h
[7:0]
MON7 ADC output
20Ah
[7:0]
MON8 ADC output
20Bh
[7:0]
MON9 ADC output
20Ch
[7:0]
MON10 ADC output
20Dh
[7:0]
MON11 ADC output
20Eh
[7:0]
MON12 ADC output
20Fh
[7:0]
Current-sense ADC output
Reset Output
The reset output, RESET, indicates the status of the monitored inputs.
During normal monitoring, RESET can be configured to
assert when any combination of MON_ inputs violates
configurable combinations of thresholds: undervoltage,
overvoltage, or early warning. Select the combination of
thresholds using r3Bh[1:0], and select the combination
of MON_ inputs using r3Ch[7:1] and r3Dh[4:0]. Note that
MON_ inputs configured as critical faults will always cause
RESET to assert regardless of these configuration bits.
RESET can be configured as push-pull or open drain
using r3Bh[3], and active-high or active-low using
r3Bh[2]. Select the reset timeout by loading a value from
Table 16 into r3Bh[7:4]. RESET can be forced to assert
by writing a ‘1’ into r3Ch[0]. RESET remains asserted
for the reset timeout period after a ‘0’ is written into
r3Ch[0]. See Table 16. The current state of RESET can
be checked by reading r20h[0].
Watchdog Timer
The watchdog timer operates together with or independently of the MAX16070/MAX16071. When operating in
dependent mode, the watchdog is not activated until EN
goes high and RESET is deasserted. When operating in
independent mode, the watchdog timer activates immediately after VCC exceeds the UVLO threshold and the
boot phase is complete. Set r73h[4] to ‘0’ to configure
the watchdog in dependent mode. Set r73h[4] to ‘1’ to
configure the watchdog in independent mode. See Table
17 for more information on configuring the watchdog
timer in dependent or independent mode.
Dependent Watchdog Timer Operation
Use the watchdog timer to monitor FP activity in two
modes. Flexible timeout architecture provides an adjustable watchdog startup delay of up to 300s, allowing complicated systems to complete lengthy boot-up
routines. An adjustable watchdog timeout allows the
supervisor to provide quick alerts when processor activity fails. After each reset event (VCC drops below UVLO
then returns above UVLO, software reboot, manual reset
(MR), EN input going low then high, or watchdog reset),
the watchdog startup delay provides an extended time
for the system to power up and fully initialize all FP and
system components before assuming responsibility for
routine watchdog updates. Set r76h[6:4] to a value other
than ‘000’ to enable the watchdog startup delay. Set
r76h[6:4] to ‘000’ to disable the watchdog startup delay.
26 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
[1:0]
3Bh
0 = Active-low
1 = Active-high
[3]
1 = Push-pull
0 = Open drain
23Bh
3Dh
23Ch
23Dh
Reset output depends on:
00 = Undervoltage threshold violations
01 = Early warning threshold violations
10 = Overvoltage threshold violations
11 = Undervoltage or overvoltage threshold violations
[2]
[7:4]
3Ch
DESCRIPTION
Reset timeout period
0000 = 25μs
0001 = 1.5ms
0010 = 2.5ms
0011 = 4ms
0100 = 6ms
0101 = 10ms
0110 = 15ms
0111 = 25ms
1000 = 40ms
1001 = 60ms
1010 = 100ms
1011 = 150ms
1100 = 250ms
1101 = 400ms
1110 = 600ms
1111 = 1s
[0]
Reset soft trigger
0 = Normal RESET behavior
1 = Force RESET to assert
[1]
1 = RESET depends on MON1
[2]
1 = RESET depends on MON2
[3]
1 = RESET depends on MON3
[4]
1 = RESET depends on MON4
[5]
1 = RESET depends on MON5
[6]
1 = RESET depends on MON6
[7]
1 = RESET depends on MON7
[0]
1 = RESET depends on MON8
[1]
1 = RESET depends on MON9
[2]
1 = RESET depends on MON10
[3]
1 = RESET depends on MON11
[4]
1 = RESET depends on MON12
[7:5]
Reserved
______________________________________________________________________________________ 27
MAX16070/MAX16071
Table 16. Reset Output Configuration
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 17. Watchdog Configuration
REGISTER
ADDRESS
FLASH
ADDRESS
BIT RANGE
73h
273h
[4]
1 = Independent mode
0 = Dependent mode
[7]
1 = Watchdog affects RESET output
0 = Watchdog does not affect RESET output
76h
DESCRIPTION
[6:4]
Watchdog startup delay
000 = No initial timeout
001 = 30s
010 = 40s
011 = 80s
100 = 120s
101 = 160s
110 = 220s
111 = 300s
[3:0]
Watchdog timeout
0000 = Watchdog disabled
0001 = 1ms
0010 = 2ms
0011 = 4ms
0100 = 8ms
0101 = 14ms
0110 = 27ms
0111 = 50ms
1000 = 100ms
1001 = 200ms
1010 = 400ms
1011 = 750ms
1100 = 1.4s
1101 = 2.7s
1110 = 5s
1111 = 10s
276h
The normal watchdog timeout period, tWDI, begins after
the first transition on WDI before the conclusion of the
long startup watchdog period, tWDI_STARTUP (Figure 5).
During the normal operating mode, WDO asserts if the
FP does not toggle WDI with a valid transition (high-tolow or low-to-high) within the standard timeout period,
tWDI. WDO remains asserted until WDI is toggled or
RESET is asserted (Figure 6).
While EN is low, the watchdog timer is in reset. The
watchdog timer does not begin counting until RESET is
deasserted. The watchdog timer is reset and WDO deasserts any time RESET is asserted (Figure 7). The watchdog timer will be held in reset while RESET is asserted.
The watchdog can be configured to control the RESET
output as well as the WDO output. RESET asserts for
the reset timeout, tRP, when the watchdog timer expires
and the Watchdog Reset Output Enable bit (r76h[7]) is
set to ‘1.’ When RESET is asserted, the watchdog timer
is cleared and WDO is deasserted, therefore, WDO
pulses low for a short time (approximately 1Fs) when
the watchdog timer expires. RESET is not affected by
the watchdog timer when the Watchdog Reset Output
Enable bit (r76h[7]) is set to ‘0.’ If a RESET is asserted
by the watchdog timeout, the WDRESET bit is set to ‘1’. A
connected processor can check this bit to see the reset
was due to a watchdog timeout. See Table 17 for more
information on configuring watchdog functionality.
28 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
MAX16070/MAX16071
VTH
LAST MON_
< tWDI
tWDI_STARTUP
WDI
< tWDI
tRP
RESET
Figure 5. Normal Watchdog Startup Sequence
VCC
WDI
< tWDI
< tWDI
> tWDI
< tWDI
< tWDI
< tWDI
< tWDI
0V
tWDI
VCC
WDO
0V
Figure 6. Watchdog Timer Operation
VCC
< tWDI
WDI
tWDI
tRP
< tWDI_STARTUP
< tWDI
0V
VCC
RESET
0V
VCC
WDO
0V
1µs
Figure 7. Watchdog Startup Sequence with Watchdog Reset Output Enable Bit Set to ‘1’
______________________________________________________________________________________ 29
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Independent Watchdog Timer Operation
When r73h[4] is ‘1’ the watchdog timer operates in
the independent mode. In the independent mode, the
watchdog timer operates as if it were a separate device.
The watchdog timer is activated immediately upon VCC
exceeding UVLO and once the boot-up sequence is finished. When RESET is asserted, the watchdog timer and
WDO are not affected.
There will be a startup delay if r76h[6:4] is set to a value
different than ‘000.’ If r76h[6:4] is set to ‘000,’ there will
not be a startup delay. See Table 17 for delay times.
In independent mode, if the Watchdog Reset Output
Enable bit r76h[7] is set to ‘1,’ when the watchdog timer
expires, WDO asserts then RESET asserts. WDO will
then deassert. WDO will be low for approximately 1Fs.
If the Watchdog Reset Output Enable bit (r76h[7]) is set
to ‘0,’ when the WDT expires, WDO asserts but RESET
is not affected.
User-Defined Register
Register r8Ah provides storage space for a user-defined
configuration or firmware version number. Note that this
register controls the contents of the JTAG USERCODE
register bits 7:0. The user-defined register is stored at
r28Ah in the flash memory.
Memory Lock Bits
SMBus-Compatible Interface
The MAX16070/MAX16071 feature an SMBuscompatible, 2-wire serial interface consisting of a serialdata line (SDA) and a serial-clock line (SCL). SDA and
SCL facilitate bidirectional communication between the
MAX16070/MAX16071 and the master device at clock
rates up to 400kHz. Figure 1 shows the 2-wire interface
timing diagram. The MAX16070/MAX16071 are transmit/
receive slave-only devices, relying upon a master device
to generate a clock signal. The master device (typically
a microcontroller) initiates a data transfer on the bus and
generates SCL to permit that transfer.
A master device communicates to the MAX16070/
MAX16071 by transmitting the proper address followed
by a command and/or data words. The slave address
input, A0, is capable of detecting four different states,
allowing multiple identical devices to share the same
serial bus. The slave address is described further in
the Slave Address section. Each transmit sequence is
framed by a START (S) or REPEATED START (SR) condition and a STOP (P) condition. Each word transmitted
over the bus is 8 bits long and is always followed by an
acknowledge pulse. SCL is a logic input, while SDA is
an open-drain input/output. SCL and SDA both require
external pullup resistors to generate the logic-high voltage. Use 4.7kI for most applications.
Register r8Ch contains the lock bits for the configuration
registers, configuration flash, user flash, and fault register lock. See Table 18 for details.
Table 18. Memory Lock Bits
REGISTER
ADDRESS
8Ch
FLASH ADDRESS
BIT RANGE
DESCRIPTION
0
Configuration register lock
1 = Locked
0 = Unlocked
1
Flash fault register lock
1 = Locked
0 = Unlocked
2
Flash configuration lock
1 = Locked
0 = Unlocked
3
User flash lock
1 = Locked
0 = Unlocked
28Ch
30 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
SDA
SCL
SCL
DATA LINE STABLE, CHANGE OF
DATA ALLOWED
DATA VALID
S
P
START
CONDITION
STOP
CONDITION
Figure 8. Bit Transfer
Figure 9. START and STOP Conditions
Bit Transfer
Each clock pulse transfers one data bit. The data on
SDA must remain stable while SCL is high (Figure 8);
otherwise the MAX16070/MAX16071 register a START or
STOP condition (Figure 9) from the master. SDA and SCL
idle high when the bus is not busy.
Acknowledge
The acknowledge bit (ACK) is the 9th bit attached to any
8-bit data word. The receiving device always generates
an ACK. The MAX16070/MAX16071 generate an ACK
when receiving an address or data by pulling SDA low
during the 9th clock period (Figure 10). When transmitting data, such as when the master device reads data
back from the MAX16070/MAX16071, the device waits for
the master device to generate an ACK. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if the receiving device
is busy or if a system fault has occurred. In the event of an
unsuccessful data transfer, the bus master can reattempt
communication at a later time. The MAX16070/MAX16071
generate a NACK after the command byte received during a software reboot, while writing to the flash, or when
receiving an illegal memory address.
START and STOP Conditions
Both SCL and SDA idle high when the bus is not busy.
A master device signals the beginning of a transmission
with a START condition by transitioning SDA from high to
low while SCL is high. The master device issues a STOP
condition by transitioning SDA from low to high while
SCL is high. A STOP condition frees the bus for another
transmission. The bus remains active if a REPEATED
START condition is generated, such as in the block read
protocol (see Figure 1).
Early STOP Conditions
The MAX16070/MAX16071 recognize a STOP condition
at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition.
This condition is not a legal SMBus format; at least one
clock pulse must separate any START and STOP condition.
REPEATED START Conditions
A REPEATED START can be sent instead of a STOP
condition to maintain control of the bus during a read
operation. The START and REPEATED START conditions
are functionally identical.
Slave Address
Use the slave address input, A0, to allow multiple identical devices to share the same serial bus. Connect A0 to
GND, DBP (or an external supply voltage greater than
2V), SCL, or SDA to set the device address on the bus.
See Table 20 for a listing of all possible 7-bit addresses.
The slave address can also be set to a custom value by
loading the address into register r8Bh[6:0]. See Table
19. If r8Bh[6:0] is loaded with 00h, the address is set by
input A0. Do not set the address to 09h or 7Fh to avoid
address conflicts. The slave address setting takes effect
immediately after writing to the register.
______________________________________________________________________________________ 31
MAX16070/MAX16071
SDA
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
CLOCK PULSE FOR ACKNOWLEDGE
2
1
SCL
8
9
SDA BY
TRANSMITTER
S
NACK
SDA BY
RECEIVER
ACK
Figure 10. Acknowledge
Table 19. SMBus Settings Register
REGISTER
ADDRESS
FLASH ADDRESS
8Bh
28Bh
BIT RANGE
[6:0]
[7]
DESCRIPTION
I2C Slave Address Register. Set to 00h to use A0 pin
address setting.
1 = Enable PEC (packet error check).
Table 20. Setting the SMBus Slave Address
SLAVE ADDRESSES
A0
SLAVE ADDRESS
0
1010 000R
1
1010 001R
SCL
1010 010R
SDA
1010 011R
R = Read/Write select bit
32 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
The CRC-8 byte is calculated using the polynomial
C = X8 + X2 + X + 1
The PEC calculation includes all bytes in the transmission, including address, command, and data. The PEC
calculation does not include ACK, NACK, START, STOP,
or REPEATED START.
Command Codes
The MAX16070/MAX16071 use eight command codes
for block read, block write, and other commands. See
Table 21 for a list of command codes.
To initiate a software reboot, send A7h using the send byte
format. A software-initiated reboot is functionally the same
as a hardware-initiated power-on reset. During boot-up,
flash configuration data in the range of 230h to 28Ch is
copied to r30h to r8Ch registers in the default page.
Restrictions When Writing to Flash
Flash must be written to 8 bytes at a time. The initial
address must be aligned to 8-byte boundaries—the
three LSBs of the initial address must be ‘000.’ Write the
8 bytes using a single block-write command or using 8
successive Write Byte commands.
Send Byte
The send byte protocol allows the master device to send
one byte of data to the slave device (see Figure 11). The
send byte presets a register pointer address for a subsequent read or write. The slave sends a NACK instead of
an ACK if the master tries to send a memory address or
command code that is not allowed. If the master sends
A5h or A6h, the data is ACK, because this could be the
start of the write block or read block. If the master sends
a STOP condition before the slave asserts an ACK, the
internal address pointer does not change. If the master
sends A7h, this signifies a software reboot. The send
byte procedure is the following:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a write
bit (low).
Send command code A8h to trigger a fault store to flash.
Configure the Critical Fault Log Control register (r6Dh) to
store ADC conversion results and/or fault flags.
3) The addressed slave asserts an ACK on SDA.
While in the flash page, send command code A9h to
access the flash page (addresses from 200h to 28Dh).
Once command code A9h has been sent, all addresses
are recognized as flash addresses only. Send command
code AAh to return to the default page (addresses from
000h to 08Dh). Send command code ABh to access
the user flash-page (addresses from 300h to 39Fh and
3B0h–3FFh), and send command code ACh to return to
the flash page.
5) The addressed slave asserts an ACK (or NACK) on SDA.
4) The master sends an 8-bit memory address or command code.
6) The master sends a STOP condition.
Table 21. Command Codes
COMMAND
CODE
ACTION
A5h
Block write
A6h
Block read
A7h
Reboot flash in register file
A8h
Trigger emergency save to flash
A9h
Flash page access ON
AAh
Flash page access OFF
ABh
User flash access ON (must be in flash page already)
ACh
User flash access OFF (return to flash page)
______________________________________________________________________________________ 33
MAX16070/MAX16071
Packet Error Checking (PEC)
The MAX16070/MAX16071 feature a PEC mode that is
useful for improving the reliability of the communication
bus by detecting bit errors. By enabling PEC, an extra
CRC-8 error check byte is added in the data string during each read and/or write sequence. Enable PEC by
writing a ‘1’ to r8Bh[7].
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Send Byte Format
S
ADDRESS
Receive Byte Format
R/W ACK
7 bits
0
0
Slave Address: Address
of the slave on the serial
interface bus.
COMMAND
ACK
8 bits
0
P
ADDRESS
S
Data Byte: Presets the internal
address pointer or represents
a command.
ADDRESS
7 bits
SLAVE
ADDRESS
0
DATA
NACK
8 bits
1
P
Data Byte: Data is read from
the location pointed to by the
internal address pointer.
SMBALERT#
R/W ACK
0
0
Slave Address: Address
of the slave on the serial
interface bus.
Read Byte Format
S
1
Slave Address: Address
of the slave on the serial
interface bus.
Write Byte Format
S
R/W ACK
7 bits
ACK
8 bits
0
0
0
Slave Address: Address
of the slave on the serial
interface bus.
DATA
ACK
8 bits
0
P
S
COMMAND
ACK
8 bits
0
SR
SLAVE
ADDRESS
R/W ACK
0001100
D.C.
DATA BYTE NACK
R/W ACK
7 bits
ADDRESS
0
Alert Response Address:
Only the device that
interrupted the master
responds to this address.
Data Byte: Data is written to
the locations set by the
internal address pointer.
Command Byte:
Sets the internal
address pointer.
R/W ACK
7 bits
COMMAND
1
8 bits
0
DATA
NACK
8 bits
1
P
Slave Address: Slave places
its own address on the
serial bus.
P
1
Data Byte: Data is read from
the locations set by the
internal address pointer.
Command Byte:
Sets the internal
address pointer.
Block Write Format
S
ADDRESS
R/W ACK
7 bits
0
0
Slave Address: Address
of the slave on the
serial interface bus.
COMMAND
ACK
BYTE
COUNT = N
8 bits
0
8 bits
ACK DATA BYTE 1 ACK DATA BYTE … ACK DATA BYTE N ACK
8 bits
0
Command Byte:
A5h
8 bits
0
0
8 bits
Slave to master
P
0
Master to slave
Data Byte: Data is written to the locations
set by the internal address pointer.
Block Read Format
S
ADDRESS
R/W ACK
7 bits
0
0
Slave Address: Address
of the slave on the
serial interface bus.
COMMAND
ACK
8 bits
0
SR
ADDRESS
7 bits
1
0
Slave Address: Address
of the slave on the
serial interface bus.
Command Byte:
A6h
BYTE
COUNT = N
R/W ACK
ACK DATA BYTE 1 ACK DATA BYTE … ACK DATA BYTE N NACK
8 bits
0
8 bits
0
8 bits
0
8 bits
P
1
Data Byte: Data is read from the locations
set by the internal address pointer.
Write Byte Format with PEC
S
ADDRESS
R/W A
7 BITS
0
COMMAND
A
DATA
A
PEC
A
8 BITS
0
8 BITS
0
8 BITS
0
COMMAND
A
0
0
P
Read Byte Format with PEC
S
ADDRESS
R/W A
7 BITS
0
0
8 BITS
ADDRESS
R/W
A
COMMAND
7 BITS
0
0
ADDRESS
R/W
7 BITS
0
SR
ADDRESS
R/W
A
DATA
A
PEC
N
7 BITS
1
0
8 BITS
0
8 BITS
1
P
Block Write with PEC
S
A BYTE COUNT N
A
DATA BYTE 1
A
DATA BYTE
A
DATA N
A
PEC
A
8 BITS
0
0
8 BITS
0
8 BITS
0
8 BITS
0
8 BITS
0
A
COMMAND
A
A
DATA BYTE N
A
PEC
N
0
8 BITS
0
0
8 BITS
0
8 BITS
1
8 BITS
P
Block Read with PEC
S
S = START Condition
P = STOP Condition
Sr = Repeated START Condition
D.C. = Don’t Care
SR
ADDRESS
R/W
A
BYTE COUNT N
A
DATA BYTE 1
A
7 BITS
1
0
8 BITS
0
8 BITS
0
ACK = Acknowledge, SDA pulled low during rising edge of SCL.
NACK = Not acknowledge, SDA left high during rising edge of SCL.
All data is clocked in/out of the device on rising edges of SCL.
DATA BYTE
8 BITS
= SDA transitions from high to low during period of SCL.
= SDA transitions from low to high during period of SCL.
Figure 11. SMBus Protocols
34 ��
P
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
7) The slave asserts an ACK on the data line.
8) The master sends an 8-bit PEC byte.
9) The slave asserts an ACK on the data line (if PEC is
good, otherwise NACK).
10) The master generates a STOP condition.
2) The master sends the 7-bit slave address and a read
bit (high).
Read Byte
The read byte protocol (see Figure 11) allows the master
device to read a single byte located in the default page,
extended page, or flash page depending on which page
is currently selected. The read byte procedure is the
following:
3) The addressed slave asserts an ACK on SDA.
1) The master sends a START condition.
4) The slave sends 8 data bits.
2) The master sends the 7-bit slave address and a
write bit (low).
1) The master sends a START condition.
5 The master asserts a NACK on SDA.
6) The master generates a STOP condition.
Write Byte
The write byte protocol (see Figure 11) allows the master
device to write a single byte in the default page, extended page, or flash page, depending on which page is currently selected. The write byte procedure is the following:
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit memory address.
5) The addressed slave asserts an ACK on SDA.
6) The master sends a REPEATED START condition.
7) The master sends the 7-bit slave address and a
read bit (high).
1) The master sends a START condition.
8) The addressed slave asserts an ACK on SDA.
2) The master sends the 7-bit slave address and a write
bit (low).
9) The slave sends an 8-bit data byte.
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit memory address.
10) The master asserts a NACK on SDA.
11) The master sends a STOP condition.
5) The addressed slave asserts an ACK on SDA.
If the memory address is not valid, it is NACKed by the
slave at step 5 and the address pointer is not modified.
6) The master sends an 8-bit data byte.
When PEC is enabled, the Read Byte protocol becomes:
7) The addressed slave asserts an ACK on SDA.
1) The master sends a START condition.
8) The master sends a STOP condition.
2) The master sends the 7-bit slave ID plus a write
bit (low).
To write a single byte, only the 8-bit memory address
and a single 8-bit data byte are sent. The data byte is
written to the addressed location if the memory address
is valid. The slave asserts a NACK at step 5 if the memory address is not valid.
3) The addressed slave asserts an ACK on the data line.
4) The master sends 8-bit memory address.
5) The active slave asserts an ACK on the data line.
When PEC is enabled, the Write Byte protocol becomes:
6) The master sends a REPEATED START condition.
1) The master sends a START condition.
7) The master sends the 7-bit slave ID plus a read bit (high).
2) The master sends the 7-bit slave ID plus a write
bit (low).
8) The addressed slave asserts an ACK on the data line.
3) The addressed slave asserts an ACK on the data line.
10) The master asserts an ACK on the data line.
4) The master sends an 8-bit memory address.
11) The slave sends an 8-bit PEC byte.
5) The active slave asserts an ACK on the data line.
12) The master asserts a NACK on the data line.
6) The master sends an 8-bit data byte.
13) The master generates a STOP condition.
9) The slave sends 8 data bits.
______________________________________________________________________________________ 35
MAX16070/MAX16071
Receive Byte
The receive byte protocol allows the master device to
read the register content of the MAX16070/MAX16071
(see Figure 11). The flash or register address must be
preset with a send byte or write word protocol first. Once
the read is complete, the internal pointer increases by
one. Repeating the receive byte protocol reads the contents of the next address. The receive byte procedure
follows:
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Block Write
The block write protocol (see Figure 11) allows the master device to write a block of data (1 byte to 16 bytes) to
memory. Preload the destination address by a previous
send byte command; otherwise the block write command begins to write at the current address pointer.
After the last byte is written, the address pointer remains
preset to the next valid address. If the number of bytes
to be written causes the address pointer to exceed 8Fh
for configuration registers or configuration flash or FFh
for user flash, the address pointer stays at 8Fh or FFh,
respectively, overwriting this memory address with the
remaining bytes of data. The slave generates a NACK at
step 5 if the command code is invalid or if the device is
busy, and the address pointer is not altered.
The block write procedure is the following:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends the 8-bit command code for block
write (A5h).
5) The addressed slave asserts an ACK on SDA.
6) The master sends the 8-bit byte count (1 byte to 16
bytes), n.
7) The addressed slave asserts an ACK on SDA.
8) The master sends 8 bits of data.
9) The addressed slave asserts an ACK on SDA.
10) Repeat steps 8 and 9 n - 1 times.
11)
The
master
sends
a
STOP
condition.
When PEC is enabled, the Block Write protocol
becomes:
9) The slave asserts an ACK on the data line.
10) Repeat 8 and 9 n - 1 times.
11) The master sends an 8-bit PEC byte. 12) The slave asserts an ACK on the data line (if PEC is
good, otherwise NACK).
13) The master generates a STOP condition.
Block Read
The block read protocol (see Figure 11) allows the
master device to read a block of up to 16 bytes from
memory. Read fewer than 16 bytes of data by issuing
an early STOP condition from the master, or by generating a NACK with the master. The destination address
should be preloaded by a previous send byte command;
otherwise the block read command begins to read at
the current address pointer. If the number of bytes to
be read causes the address pointer to exceed 8Fh for
the configuration register or configuration flash or FFh
in user flash, the address pointer stays at 8Fh or FFh,
respectively. The block read procedure is the following:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a write
bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends 8 bits of the block read command (A6h).
5) The slave asserts an ACK on SDA, unless busy.
6) The master generates a REPEATED START condition.
7) The master sends the 7-bit slave address and a read
bit (high).
8) The slave asserts an ACK on SDA.
9) The slave sends the 8-bit byte count (16).
1) The master sends a START condition.
10)The master asserts an ACK on SDA.
2) The master sends the 7-bit slave ID plus a write
bit (low).
11)The slave sends 8 bits of data.
3) The addressed slave asserts an ACK on the data line.
13)Repeat steps 11 and 12 up to fifteen times.
4) The master sends 8 bits of the block write command code.
14)The master asserts a NACK on SDA.
12)The master asserts an ACK on SDA.
5) The slave asserts an ACK on the data line.
15)The master sends a STOP condition.When PEC is
enabled, the Block Read protocol becomes:
6) The master sends an 8-bit byte count (min 1, max
16), n. 1) The master sends a START condition.
7) The slave asserts an ACK on the data line.
2) The master sends the 7-bit slave ID plus a write
bit (low).
8) The master sends 8 bits of data.
3) The addressed slave asserts an ACK on the data line.
36 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
REGISTER
ADDRESS
35h
FLASH
ADDRESS
235h
BIT RANGE
[1:0]
DESCRIPTION
SMBus Alert Configuration
00 = Disabled
01 = Fault1 is SMBus ALERT
10 = Fault2 is SMBus ALERT
11 = ANY_FAULT is SMBus ALERT
4) The master sends 8 bits of the block read command code.
5) The slave asserts an ACK on the data line unless busy.
6) The master sends a REPEATED START condition.
7) The master sends the 7-bit slave ID plus a read
bit (high).
8) The slave asserts an ACK on the data line.
9) The slave sends an 8-bit byte count (16).
10) The master asserts an ACK on the data line.
11) The slave sends 8 bits of data.
12) The master asserts an ACK on the data line.
13) Repeat steps 11 and 12 up to 15 times.
14) The slave sends an 8-bit PEC byte.
15) The master asserts a NACK on the data line.
16) The master generates a STOP condition.
SMBALERT
The MAX16070/MAX16071 support the SMBus alert
protocol. To enable the SMBus alert output, set r35h[1:0]
according to Table 22, which configures a Fault1, Fault2,
or ANY_FAULT output to act as the SMBus alert. This
output is open-drain and uses the wired-OR configuration with other devices on the SMBus. During a fault,
the MAX16070/MAX16071 assert ALERT low, signaling
the master that an interrupt has occurred. The master
responds by sending the ARA (Alert Response Address)
protocol on the SMBus. This protocol is a read byte with
09h as the slave address. The slave acknowledges the
ARA (09h) address and sends its own SMBus address to
the master. The slave then deasserts ALERT. The master
can then query the slave and determine the cause of the
fault. By checking r1Ch[6], the master can confirm that
the MAX16070/MAX16071 triggered the SMBus alert.
The master must send the ARA before clearing r1Ch[6].
Clear r1Ch[6] by writing a ‘1’.
JTAG Serial Interface
The MAX16070/MAX16071 feature a JTAG port that
complies with a subset of the IEEE® 1149.1 specification. Either the SMBus or the JTAG interface can be used
to access internal memory; however, only one interface
is allowed to run at a time. The MAX16070/MAX16071
do not support IEEE 1149.1 boundary-scan functionality.
The MAX16070/MAX16071 contain extra JTAG instructions and registers not included in the JTAG specification that provide access to internal memory. The extra
instructions include LOAD ADDRESS, WRITE DATA,
READ DATA, REBOOT, SAVE.
IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.
______________________________________________________________________________________ 37
MAX16070/MAX16071
Table 22. SMBus Alert Configuration
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
REGISTERS
AND FLASH
01100
01011
01010
01001
01000
00111
MEMORY WRITE REGISTER
[LENGTH = 8 BITS]
00110
MEMORY READ REGISTER
[LENGTH = 8 BITS]
00101
MEMORY ADDRESS REGISTER
[LENGTH = 8 BITS]
00100
USER CODE REGISTER
[LENGTH = 32 BITS]
00011
IDENTIFICATION REGISTER
[LENGTH = 32 BITS]
BYPASS REGISTER
[LENGTH = 1 BIT]
MUX 1
00000
11111
COMMAND
DECODER
01001
SETFLSHADD
01010
RSTFLSHADD
01011
SETUSRFLSH
01100
RSTUSRFLSH
01000
SAVE
00111
REBOOT
VDB
INSTRUCTION REGISTER
[LENGTH = 5 BITS]
RPU
TDI
MUX 2
TMS
TDO
TEST ACCESS PORT
(TAP) CONTROLLER
TCK
Figure 12. JTAG Block Diagram
Test Access Port (TAP)
Controller State Machine
The TAP controller is a finite state machine that responds
to the logic level at TMS on the rising edge of TCK. See
Figure 13 for a diagram of the finite state machine. The
possible states are described in the following:
Test-Logic-Reset: At power-up, the TAP controller
is in the test-logic-reset state. The instruction register
contains the IDCODE instruction. All system logic of the
device operates normally. This state can be reached
from any state by driving TMS high for five clock cycles.
Run-Test/Idle: The run-test/idle state is used between
scan operations or during specific tests. The instruction
register and test data registers remain idle.
Select-DR-Scan: All test data registers retain their previous state. With TMS low, a rising edge of TCK moves the
controller into the capture-DR state and initiates a scan
sequence. TMS high during a rising edge on TCK moves
the controller to the select-IR-scan state.
Capture-DR: Data can be parallel-loaded into the test
data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected
test data register does not allow parallel loads, the test
38 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
TEST-LOGIC-RESET
0
0
RUN-TEST/IDLE
1
SELECT-DR-SCAN
1
SELECT-IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
PAUSE-IR
0
1
0
1
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
SHIFT-IR
0
1
0
1
UPDATE-IR
0
1
0
Figure 13. Tap Controller State Diagram
data register remains at its current value. On the rising
edge of TCK, the controller goes to the shift-DR state if
TMS is low or it goes to the exit1-DR state if TMS is high.
Shift-DR: The test data register selected by the current
instruction connects between TDI and TDO and shifts
data one stage toward its serial output on each rising
edge of TCK while TMS is low. On the rising edge of TCK,
the controller goes to the exit1-DR state if TMS is high.
Exit1-DR: While in this state, a rising edge on TCK puts
the controller in the update-DR state. A rising edge on TCK
with TMS low puts the controller in the pause-DR state.
Pause-DR: Shifting of the test data registers halts while
in this state. All test data registers retain their previous
state. The controller remains in this state while TMS is
low. A rising edge on TCK with TMS high puts the controller in the exit2-DR state.
Exit2-DR: A rising edge on TCK with TMS high while in
this state puts the controller in the update-DR state. A rising edge on TCK with TMS low enters the shift-DR state.
Update-DR: A falling edge on TCK while in the updateDR state latches the data from the shift register path of
the test data registers into a set of output latches. This
prevents changes at the parallel output because of
changes in the shift register. On the rising edge of TCK,
the controller goes to the run-test/idle state if TMS is low
or goes to the select-DR-scan state if TMS is high.
Select-IR-Scan: All test data registers retain the previous states. The instruction register remains unchanged
during this state. With TMS low, a rising edge on TCK
moves the controller into the capture-IR state. TMS high
during a rising edge on TCK puts the controller back into
the test-logic-reset state.
Capture-IR: Use the capture-IR state to load the shift
register in the instruction register with a fixed value. This
value is loaded on the rising edge of TCK. If TMS is high
on the rising edge of TCK, the controller enters the exit1IR state. If TMS is low on the rising edge of TCK, the
controller enters the shift-IR state.
Shift-IR: In this state, the shift register in the instruction
register connects between TDI and TDO and shifts data
one stage for every rising edge of TCK toward the TDO
serial output while TMS is low. The parallel outputs of
the instruction register as well as all test data registers
remain at the previous states. A rising edge on TCK with
TMS high moves the controller to the exit1-IR state. A
rising edge on TCK with TMS low keeps the controller in
the shift-IR state while moving data one stage through
the instruction shift register.
______________________________________________________________________________________ 39
MAX16070/MAX16071
1
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Exit1-IR: A rising edge on TCK with TMS low puts the
controller in the pause-IR state. If TMS is high on the
rising edge of TCK, the controller enters the update-IR
state.
register connects between TDI and TDO. While in the
shift-IR state, a rising edge on TCK with TMS low shifts
the data one stage toward the serial output at TDO. A
rising edge on TCK in the exit1-IR state or the exit2-IR
state with TMS high moves the controller to the updateIR state. The falling edge of that same TCK latches the
data in the instruction shift register to the instruction register parallel output. Table 23 shows the instructions supported by the MAX16070/MAX16071 and the respective
operational binary codes.
Pause-IR: Shifting of the instruction shift register halts
temporarily. With TMS high, a rising edge on TCK puts
the controller in the exit2-IR state. The controller remains
in the pause-IR state if TMS is low during a rising edge
on TCK.
Exit2-IR: A rising edge on TCK with TMS high puts the
controller in the update-IR state. The controller loops
back to shift-IR if TMS is low during a rising edge of TCK
in this state.
BYPASS: When the BYPASS instruction is latched into
the instruction register, TDI connects to TDO through the
1-bit bypass test data register. This allows data to pass
from TDI to TDO without affecting the device’s operation.
Update-IR: The instruction code that has been shifted
into the instruction shift register latches to the parallel
outputs of the instruction register on the falling edge of
TCK as the controller enters this state. Once latched,
this instruction becomes the current instruction. A rising
edge on TCK with TMS low puts the controller in the runtest/idle state. With TMS high, the controller enters the
select-DR-scan state.
IDCODE: When the IDCODE instruction is latched into the
parallel instruction register, the identification data register
is selected. The device identification code is loaded into
the identification data register on the rising edge of TCK
following entry into the capture-DR state. Shift-DR can be
used to shift the identification code out serially through
TDO. During test-logic-reset, the IDCODE instruction
is forced into the instruction register. The identification
code always has a ‘1’ in the LSB position. The next 11 bits
identify the manufacturer’s JEDEC number and number
of continuation bytes followed by 16 bits for the device
and 4 bits for the version. See Table 24.
Instruction Register
The instruction register contains a shift register as well
as a latched 5-bit-wide parallel output. When the TAP
controller enters the shift-IR state, the instruction shift
Table 23. JTAG Instruction Set
INSTRUCTION
CODE
NOTES
BYPASS
0x1F
Mandatory instruction code
IDCODE
0x00
Load manufacturer ID code/part number
USERCODE
0x03
Load user code
LOAD ADDRESS
0x04
Load address register content
READ DATA
0x05
Read data pointed by current address
WRITE DATA
0x06
Write data pointed by current address
REBOOT
0x07
Reboot FLASH data content into register file
SAVE
0x08
Trigger emergency save to flash
SETFLSHADD
0x09
Flash page access ON
RSTFLSHADD
0x0A
Flash page access OFF
SETUSRFLSH
0x0B
User flash access ON (must be in flash page already)
RSTUSRFLSH
0x0C
User flash access OFF (return to flash page)
Table 24. 32-Bit Identification Code
MSB
LSB
VERSION
PART NUMBER (16 BITS)
MANUFACTURER (11 BITS)
FIXED VALUE (1 BIT)
MAX16070
REV
1000000000000011
00011001011
1
MAX16071
REV
1000000000000100
00011001011
1
40 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
MSBLSB
Don’t Care
00000000000000000
SMBus slave ID
See Table 20
USERCODE: When the USERCODE instruction latches
into the parallel instruction register, the user-code data
register is selected. The device user-code loads into the
user-code data register on the rising edge of TCK following entry into the capture-DR state. Shift-DR can be
used to shift the user-code out serially through TDO. See
Table 25. This instruction can be used to help identify
multiple MAX16070/MAX16071 devices connected in a
JTAG chain.
LOAD ADDRESS: This is an extension to the standard
IEEE 1149.1 instruction set to support access to the
memory in the MAX16070/MAX16071. When the LOAD
ADDRESS instruction latches into the instruction register,
TDI connects to TDO through the 8-bit memory address
test data register during the shift-DR state.
READ DATA: This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the MAX16070/MAX16071. When the READ DATA
instruction latches into the instruction register, TDI connects to TDO through the 8-bit memory read test data
register during the shift-DR state.
WRITE DATA: This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the MAX16070/MAX16071. When the WRITE DATA
instruction latches into the instruction register, TDI connects to TDO through the 8-bit memory write test data
register during the shift-DR state.
REBOOT: This is an extension to the standard IEEE
1149.1 instruction set to initiate a software-controlled
reset to the MAX16070/MAX16071. When the REBOOT
instruction latches into the instruction register, the
MAX16070/MAX16071 reset and immediately begin the
boot-up sequence.
SAVE: This is an extension to the standard IEEE 1149.1
instruction set that triggers a fault log. The current ADC
conversion results along with fault information are saved
to flash depending on the configuration of the Critical
Fault Log Control register (r6Dh).
SETFLSHADD: This is an extension to the standard IEEE
1149.1 instruction set that allows access to the flash
page. Flash registers include ADC conversion results
User ID (r8Ah[7:0])
and GPIO_ input/output data. Use this page to access
registers 200h to 2FFh
RSTFLSHADD: This is an extension to the standard
IEEE 1149.1 instruction set. Use RSTFLSHADD to return
to the default page and disable access to the flash page.
SETUSRFLSH: This is an extension to the standard IEEE
1149.1 instruction set that allows access to the user flash
page. When on the configuration flash page, send the
SETUSRFLSH command, all addresses are recognized
as flash addresses only. Use this page to access registers 300h to 3FFh.
RSTUSRFLSH: This is an extension to the standard IEEE
1149.1 instruction set. Use RSTUSRFLSH to return to the
configuration flash page and disable access to the user
flash.
Restrictions When Writing to Flash
Flash must be written to 8 bytes at a time. The initial
address must be aligned to 8-byte boundaries—the 3
LSBs of the initial address must be ‘000’. Write the 8
bytes using eight successive WRITE DATA commands.
Applications Information
Device Behavior at Power-Up
When VCC is ramped from 0, the RESET output is high
impedance until VCC reaches 1.4V, at which point RESET
goes low. All other outputs are high impedance until VCC
reaches 2.7V, when the flash contents are copied into
register memory. This takes 150Fs (max), after which the
outputs assume their programmed states.
Maintaining Power
During a Fault Condition
Power to the MAX16070/MAX16071 must be maintained
for a specific period of time to ensure a successful flash
fault log operation during a fault that removes power to
the circuit. Table 26 shows the amount of time required
depends on the settings in the fault control register
(r6Dh[1:0]).
Maintain power for shutdown during fault conditions in
applications where the always-on power supply cannot
be relied upon by placing a diode and a large capacitor
between the voltage source, VIN, and VCC (Figure 14).
______________________________________________________________________________________ 41
MAX16070/MAX16071
Table 25. 32-Bit User-Code Data
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
The capacitor value depends on VIN and the time delay
required, tFAULT_SAVE. Use the following formula to calculate the capacitor size:
across the diode, and VUVLO is 2.7V. For example, with
a VIN of 14V, a diode drop of 0.7V, and a tFAULT_SAVE
of 153ms, the minimum required capacitance is 202FF.
C = (tFAULT_SAVE x ICC(MAX))/(VIN - VDIODE - VUVLO)
where the capacitance is in Farads and tFAULT_SAVE is in
seconds, ICC(MAX) is 14mA, VDIODE is the voltage drop
DESCRIPTION
VCC
C
Table 26. Maximum Write Time
r6Dh[1:0]
VALUE
VIN
MAXIMUM
WRITE TIME
(ms)
00
Save flags and ADC
readings
153
01
Save flags
102
10
Save ADC readings
153
11
Do not save anything
—
MAX16070
MAX16071
GND
Figure 14. Power Circuit for Shutdown During Fault Conditions
Figure 15. Graphical User Interface Screenshot
42 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Cascading Multiple MAX16070/MAX16071s
Multiple MAX16070/MAX16071s can be cascaded to
increase the number of monitored rails. There are many
ways to cascade the devices depending on the desired
behavior. In general, there are several techniques:
U Configure a GPIO_ on each device to be EXTFAULT
(open drain). Externally wire them together with a
single pullup resistor. Set register bits r72h[5] and
r6Dh[2] to ‘1’ so that all faults will propagate between
devices. If a critical fault occurs on one device,
EXTFAULT will assert, triggering the nonvolatile fault
logger in all cascaded devices and recording a snapshot of all system voltages.
UConnect open-drain RESET outputs together to obtain
a master system reset signal.
UConnect all EN inputs together for a master enable
signal.
Monitoring Current Using
the Differential Inputs
The MAX16070/MAX16071 can monitor up to seven
currents using the dedicated current-sense amplifier as
well as up to six pairs of inputs configured in differential
mode. The accuracy of the differential pairs is limited by
the voltage range and the 10-bit conversions. Each input
pair uses an odd-numbered MON_ input in combination
with an even-numbered MON_ input to monitor both the
voltage from the odd-numbered MON_ to ground and
the voltage difference between the two MON_ inputs.
This way a single pair of inputs can monitor the voltage
and the current of a power-supply rail. The overvoltage
threshold on the even numbered MON_ input can be
used as an overcurrent flag.
RS
POWER
SUPPLY
MONODD
ILOAD
MONEVEN
MAX16070
MAX16071
Figure 16. Current Monitoring Connection
Figure 16 shows how to connect a current-sense resistor to a pair of MON_ inputs for monitoring both current
and voltage.
For best accuracy, set the voltage range on the evennumbered MON_ to 1.4V. Since the ADC conversion
results are 10 bits, the monitoring precision is 1.4V/1024
= 1.4mV. For more accurate current measurements,
use larger current-sense resistors. The application
requirements should determine the balance between
accuracy and voltage drop across the current-sense
resistor.
Layout and Bypassing
Bypass DBP and ABP each with a 1FF ceramic capacitor
to GND. Bypass VCC with a 10FF capacitor to ground.
Avoid routing digital return currents through a sensitive
analog area, such as an analog supply input return path
or ABP’s bypass capacitor ground connection. Use
dedicated analog and digital ground planes. Connect
the capacitors as close as possible to the device.
______________________________________________________________________________________ 43
MAX16070/MAX16071
Configuring the Device
An evaluation kit and a graphical user interface (GUI) is
available to create a custom configuration for the device.
Refer to the MAX16070/MAX16071 evaluation kit for configuration.
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Register Map
FLASH
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
DESCRIPTION
ADC VALUES, FAULT REGISTERS, GPIO_S AS INPUT PORTS–NOT IN FLASH
—
000
R
MON1 ADC output, MSBs
—
001
R
MON1 ADC output, LSBs
—
002
R
MON2 ADC output, MSBs
—
003
R
MON2 ADC output, LSBs
—
004
R
MON3 ADC output, MSBs
—
005
R
MON3 ADC output, LSBs
—
006
R
MON4 ADC output, MSBs
—
007
R
MON4 ADC output, LSBs
—
008
R
MON5 ADC output, MSBs
—
009
R
MON5 ADC output, LSBs
—
00A
R
MON6 ADC output, MSBs
—
00B
R
MON6 ADC output, LSBs
—
00C
R
MON7 ADC output, MSBs
—
00D
R
MON7 ADC output, LSBs
—
00E
R
MON8 ADC output, MSBs
—
00F
R
MON8 ADC output, LSBs
—
010
R
MON9 ADC output, MSBs
—
011
R
MON9 ADC output, LSBs
—
012
R
MON10 ADC output, MSBs
—
013
R
MON10 ADC output, LSBs
—
014
R
MON11 ADC output, MSBs
—
015
R
MON11 ADC output, LSBs
—
016
R
MON12 ADC output, MSBs
—
017
R
MON12 ADC output, LSBs
—
018
R
Current-sense ADC output
—
019
R
CSP ADC output, MSBs
—
01A
R
CSP ADC output, LSBs
—
01B
R/W
Fault register--failed line flags
—
01C
R/W
Fault register—failed line flags/overcurrent
—
01D
R
Reserved
—
01E
R
GPIO data in (read only)
—
01F
R
Reserved
—
020
R/W
—
021
R
Flash status/reset output monitor
Reserved
44 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
FLASH
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
DESCRIPTION
GPIO AND OUTPUT DEPENDENCIES/CONFIGURATIONS
230
030
R/W
Reserved
231
031
R/W
Reserved
232
032
R/W
Reserved
233
033
R/W
Reserved
234
034
R/W
Reserved
235
035
R/W
SMBALERT pin configuration
236
036
R/W
Fault1 dependencies
237
037
R/W
Fault1 dependencies
238
038
R/W
Fault2 dependencies
239
039
R/W
Fault2 dependencies
23A
03A
R/W
Fault1/Fault2 secondary overcurrent dependencies
23B
03B
R/W
RESET output configuration
23C
03C
R/W
RESET output dependencies
23D
03D
R/W
RESET output dependencies
23E
03E
R/W
GPIO data out
23F
03F
R/W
GPIO configuration
240
040
R/W
GPIO configuration
241
041
R/W
GPIO configuration
242
042
R/W
GPIO push-pull/open drain
ADC—CONVERSIONS
243
043
R/W
ADCs voltage ranges—MON_ monitoring
244
044
R/W
ADCs voltage ranges—MON_ monitoring
245
045
R/W
ADCs voltage ranges—MON_ monitoring
246
046
R/W
Differential pairs enables
247
047
R/W
Current-sense gain-setting (CSP, HV or LV)
048
R/W
MON1 secondary selectable UV/OV
INPUT THRESHOLDS
248
249
049
R/W
MON1 primary OV
24A
04A
R/W
MON1 primary UV
24B
04B
R/W
MON2 secondary selectable UV/OV
24C
04C
R/W
MON2 primary OV
24D
04D
R/W
MON2 primary UV
24E
04E
R/W
MON3 secondary selectable UV/OV
24F
04F
R/W
MON3 primary OV
250
050
R/W
MON3 primary UV
251
051
R/W
MON4 secondary selectable UV/OV
252
052
R/W
MON4 primary OV
253
053
R/W
MON4 primary UV
______________________________________________________________________________________ 45
MAX16070/MAX16071
Register Map (continued)
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Register Map (continued)
FLASH
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
254
054
R/W
MON5 secondary selectable UV/OV
255
055
R/W
MON5 primary OV
256
056
R/W
MON5 primary UV
257
057
R/W
MON6 secondary selectable UV/OV
258
058
R/W
MON6 primary OV
259
059
R/W
MON6 primary UV
25A
05A
R/W
MON7 secondary selectable UV/OV
25B
05B
R/W
MON7 primary OV
25C
05C
R/W
MON7 primary UV
25D
05D
R/W
MON8 secondary selectable UV/OV
25E
05E
R/W
MON8 primary OV
25F
05F
R/W
MON8 primary UV
260
060
R/W
MON9 secondary selectable UV/OV
261
061
R/W
MON9 primary OV
262
062
R/W
MON9 primary UV
263
063
R/W
MON10 secondary selectable UV/OV
264
064
R/W
MON10 primary OV
265
065
R/W
MON10 primary UV
266
066
R/W
MON11 secondary selectable UV/OV
267
067
R/W
MON11 primary OV
268
068
R/W
MON11 primary UV
DESCRIPTION
269
069
R/W
MON12 secondary selectable UV/OV
26A
06A
R/W
MON12 primary OV
26B
06B
R/W
MON12 primary UV
26C
06C
R/W
Secondary overcurrent threshold
26D
06D
R/W
Save after EXTFAULT fault control
26E
06E
R/W
Faults causing store in flash
26F
06F
R/W
Faults causing store in flash
270
070
R/W
Faults causing store in flash
271
071
R/W
Faults causing store in flash
272
072
R/W
Faults causing store in flash
273
073
R/W
Overcurrent debounce, watchdog mode, secondary threshold type, software
enables
274
074
R/W
ADC fault deglitch configuration
275
075
R/W
WDI toggle
276
076
R/W
Watchdog reset output enable, watchdog timers
277
077
R/W
Boot-up delay
FAULT SETUP
TIMEOUTS
46 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
FLASH
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
278
078
R/W
Reserved
279
079
R/W
Reserved
27A
07A
R/W
Reserved
27B
07B
R/W
Reserved
27C
07C
R/W
Reserved
27D
07D
R/W
Reserved
27E
07E
R/W
Reserved
27F
07F
R/W
Reserved
280
080
R/W
Reserved
281
081
R/W
Reserved
282
082
R/W
Reserved
283
083
R/W
Reserved
284
084
R/W
Reserved
285
085
R/W
Reserved
286
086
R/W
Reserved
287
087
R/W
Reserved
288
088
R/W
Reserved
289
089
R/W
Reserved
28A
08A
R/W
Customer use (version)
28B
08B
R/W
PEC enable/I2C address
28C
08C
R/W
Lock bits
28D
08D
R
DESCRIPTION
MISCELLANEOUS
Revision code
NONVOLATILE FAULT LOG
200
—
R/W
Reserved
201
—
R/W
FAULT flags, MON1–MON8
202
—
R/W
FAULT flags, MON9–MON12, EXTFAULT
203
—
R/W
MON1 ADC output
204
—
R/W
MON2 ADC output
205
—
R/W
MON3 ADC output
206
—
R/W
MON4 ADC output
207
—
R/W
MON5 ADC output
208
—
R/W
MON6 ADC output
209
—
R/W
MON7 ADC output
20A
—
R/W
MON8 ADC output
20B
—
R/W
MON9 ADC output
20C
—
R/W
MON10 ADC output
20D
—
R/W
MON11 ADC output
20E
—
R/W
MON12 ADC output
20F
—
R/W
Current-sense ADC output
______________________________________________________________________________________ 47
MAX16070/MAX16071
Register Map (continued)
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Register Map (continued)
FLASH
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
DESCRIPTION
USER FLASH
300
39F
R/W
User flash
3A0
3AF
—
Reserved
3B0
3FF
R/W
User flash
Typical Operating Circuits
VSUPPLY
+3.3V
OUT
IN
DC-DC
GND
VCC
MON1
MAX16070
MAX16071
OUT
IN
MON2–MON11
DC-DC
SCL
SDA
GND
OUT
IN
µC
MON12
RESET
RESET
FAULT
INT
WDI
I/O
WDO
INT
DC-DC
GND
AO
GND
48 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
VSUPPLY
+3.3V
OUT
IN
DC-DC
GND
MON1
VCC
MON2
LOAD
OUT
IN
µC
MAX16070
MAX16071
SDA
MONODD
DC-DC
GND
MONEVEN
LOAD
OUT
IN
SCL
RESET
RESET
FAULT
INT
WDI
I/O
WDO
INT
MON11
DC-DC
GND
AO
MON12
LOAD
GND
NOTE: MONODD = MON1, MON3, MON5, MON7, MON9, MON11
MONEVEN = MON2, MON4, MON6, MON8, MON10, MON12
______________________________________________________________________________________ 49
MAX16070/MAX16071
Typical Operating Circuits (continued)
GPIO3
GPIO4
GPIO5
GPIO6
N.C.
N.C.
N.C.
EN
TOP VIEW
N.C.
DBP
Pin Configurations
30 29 28 27 26 25 24 23 22 21
VCC 31
20 GPIO2
ABP 32
19 GPIO1
GND 33
18 GPIO8
MON7 34
17 GPIO7
16 GND
MON8 35
MAX16070
MON9 36
15 SCL
14 AO
MON10 37
MON11 38
13 SDA
EP
+
MON12 39
12 TDO
11 TCK
TDI
10
GPIO5
9
TMS
8
GPIO6
MON5
7
RESET
MON4
6
N.C.
MON3
5
CSM
4
N.C.
3
CSP
2
MON6
1
MON2
MON1 40
N.C.
N.C.
N.C.
N.C.
EN
N.C.
TQFN
30 29 28 27 26 25 24 23 22 21
DBP 31
20 GPIO4
DBP 32
19 GPIO3
VCC 33
18 GPIO2
ABP 34
17 GPIO1
16 GND
GND 35
MAX16071
MON7 36
15 SCL
14 AO
MON8 37
N.C. 38
13 SDA
EP
+
N.C. 39
12 TDO
11 TCK
7
8
9
10
TDI
MON5
6
TMS
MON4
5
RESET
4
CSM
3
CSP
2
MON6
1
MON3
MON1 40
MON2
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
TQFN
50 ��
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
PROCESS: BiCMOS
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND PATTERN
NO.
40 TQFN-EP
T4066+5
21-0141
90-0055
______________________________________________________________________________________ 51
MAX16070/MAX16071
Package Information
Chip Information
MAX16070/MAX16071
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Revision History
REVISION
NUMBER
REVISION
DATE
0
10/09
Initial release
1
6/10
Updated Absolute Maximum Ratings and various sections to match current
style
2
2/11
Made correction to Table 16
3
8/11
Revised Pin Description and Pin Configuration
DESCRIPTION
PAGES
CHANGED
—
1–5, 8, 10, 12, 13,
14, 19, 23–26,
29–31, 33–37,
41–43, 48–51
27
9, 50
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
52
© Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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