19-1313; Rev 0; 11/97 KIT ATION EVALU E L B AVAILA High-Speed Step-Down Controller with Synchronous Rectification for CPU Power ____________________________Features The MAX1638 is an ultra-high-performance, step-down DC-DC controller for CPU power in high-end computer systems. Designed for demanding applications in which output voltage precision and good transient response are critical for proper operation, it delivers over 35A from 1.3V to 3.5V with ±1% total accuracy from a +5V ±10% supply. Excellent dynamic response corrects output transients caused by the latest dynamically clocked CPUs. This controller achieves over 90% efficiency by using synchronous rectification. Flying-capacitor bootstrap circuitry drives inexpensive, external N-channel MOSFETs. ♦ Better than ±1% Output Accuracy Over Line and Load ♦ Greater than 90% Efficiency Using N-Channel MOSFETs ♦ Pin-Selected High Switching Frequency (300kHz, 600kHz, or 1MHz) ♦ Over 35A Output Current ♦ Digitally Programmable Output from 1.3V to 3.5V ♦ Current-Mode Control for Fast Transient Response and Cycle-by-Cycle Current-Limit Protection ♦ Short-Circuit Protection with Foldback Current Limiting ♦ Glitch-Catcher Circuit for Fast Load-Transient Response ♦ Crowbar Overvoltage Protection ♦ Power-Good (PWROK) Output ♦ Digital Soft-Start ♦ High-Current (2A) Drive Outputs ♦ Complies with Intel VRM 8.2 Specification The switching frequency is pin-selectable for 300kHz, 600kHz, or 1MHz. High switching frequencies allow the use of a small surface-mount inductor and decrease output filter capacitor requirements, reducing board area and system cost. The MAX1638 is available in 24-pin SSOP and QSOP (future package) packages, and offers additional features such as a digitally programmable output; adjustable transient response; and selectable 0.5%, 1%, or 2% AC load regulation. Fast recovery from load transients is ensured by a GlitchCatcher™ current-boost circuit that eliminates delays caused by the buck inductor. Output overvoltage protection is enforced by a crowbar circuit that turns on the low-side MOSFET with 100% duty factor when the output is 200mV above the normal regulation point. Other features include internal digital soft-start, a power-good output, and a 3.5V ±1% reference output. __________Typical Operating Circuit INPUT +5V ________________________Applications Pentium Pro™, Pentium II™, PowerPC™, Alpha™, and K6™ Systems Workstations Desktop Computers LAN Servers GTL Bus Termination ______________Ordering Information PART MAX1638EAG MAX1638EEG* TEMP. RANGE PIN-PACKAGE -40°C to +85°C 24 SSOP -40°C to +85°C 24 QSOP Pin Configuration appears at end of data sheet. *Future product—contact factory for package availability. TO VDD VCC VDD AGND BST MAX1638 DH LX OUTPUT 1.3V TO 4.5V PWROK D0 D1 D2 D3 D4 DL PGND REF CSH LG CSL FREQ CC1 FB CC2 Pentium Pro and Pentium II are trademarks of Intel Corp. PowerPC is a trademark of IBM Corp. Alpha is a trademark of Digital Equipment Corp. K6 is a trademark of Advanced Micro Devices. GlitchCatcher is a trademark of Maxim Integrated Products. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX1638 _______________General Description MAX1638 High-Speed Step-Down Controller with Synchronous Rectification for CPU Power ABSOLUTE MAXIMUM RATINGS VDD, VCC, PWROK to AGND ......................................-0.3V to 6V PGND to AGND ..................................................................±0.3V CSH, CSL to AGND ....................................-0.3V to (VCC + 0.3V) NDRV, PDRV, DL to PGND.........................-0.3V to (VDD + 0.3V) REF, CC1, CC2, LG, D0–D4, FREQ, FB to AGND.............................................-0.3V to (VCC + 0.3V) BST to PGND ............................................................-0.3V to 12V BST to LX ....................................................................-0.3V to 6V DH to LX.............................................(LX - 0.3V) to (BST + 0.3V) Continuous Power Dissipation (TA = +70°C) QSOP (derate 8.70mW/°C above +70°C) .....................696mW QSOP θJC ..................................................................40°C/W SSOP (derate 8.00mW/°C above +70°C) .....................640mW SSOP θJC ..................................................................45°C/W Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = VCC = D4 = +5V, PGND = AGND = D0–D3 = 0V, FREQ = REF, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP TA = +25°C to +85°C MAX ±1 UNITS Output Voltage (FB) Accuracy Over line and load (Note 1) Input Voltage Range VCC = VDD 4.5 5.5 V Input Undervoltage Lockout VCC rising edge, 1% hysteresis 4.0 4.2 V VCC Supply Current VCC = VDD = 5.5V VDD Supply Current VCC = VDD = 5.5V, FB forced 200mV above regulation point, operating or standby mode Reference Voltage No load Reference Load Regulation 0µA < IREF < 100µA Reference Undervoltage Lockout Rising edge, 1% hysteresis Reference Short-Circuit Current VREF = 0V AC Load Regulation (Note 2) DC Load Regulation (Note 2) TA = 0°C to +85°C Operating mode FB overdrive = 200mV Shutdown mode DAC code = 11111 CSH - CSL = 0mV to 80mV CSH - CSL = 0mV to 80mV ±1.5 2.5 FB overdrive = 0V 5 0.3 VREF = 0V 3.6 3.465 2.7 0.5 LG = GND 0.5 LG = REF 1 LG = VCC 2 LG = GND 0.05 LG = REF 0.1 mV 3.0 V 4.0 mA % % 0.2 -6 -4.5 Falling FB, 1% hysteresis with respect to VREF 6.5 8 9.5 ISINK = 2mA, VCC = 4.5V PWROK = 5.5V 2 V 10 -7.5 PWROK Output Current High mA 3.535 Rising FB, 1% hysteresis with respect to VREF PWROK Output Voltage Low Switching Frequency 3.5 mA 10 0.1 LG = VCC PWROK Trip Level % 0.4 V 1 µA FREQ = VCC 850 1000 1150 FREQ = REF 540 600 660 FREQ = AGND 255 300 345 _______________________________________________________________________________________ % kHz High-Speed Step-Down Controller with Synchronous Rectification for CPU Power MAX1638 ELECTRICAL CHARACTERISTICS (continued) (VDD = VCC = D4 = +5V, PGND = AGND = D0–D3 = 0V, FREQ = REF, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER Maximum Duty Cycle CONDITIONS FREQ = VCC MIN TYP 85 90 GND (low) LG, FREQ Input Voltage 3.3 VCC (high) VCC - 0.1 D0–D4, VCC = 4.5V Logic Input Voltage High D0–D4, VCC = 5.5V D0–D4 Source Current D0–D4 = 0V % 3.7 V 0.8 V 10 µA 4 µA 50 µA 2.0 2 V 5 LG, FREQ Input Current CSH, CSL Input Current CSH = CSL = 1.3V, D0–D3 = 5V, D4 = 0V FB Input Current ±0.1 CC1 Output Resistance 10 CC2 Transconductance CC2 Clamp Voltage UNITS 0.2 REF (mid) Logic Input Voltage Low MAX µA kΩ 1 mmho Minimum 2.4 3.0 Maximum 4 VCC V CC2 Source/Sink Current 100mV overdrive 100 DH On-Resistance BST - LX = 4.5V 0.7 2 Ω DL On-Resistance VDD = 4.5V 0.7 2 Ω DH, DL Source/Sink Current DH = DL = 2.5V DH, DL Dead Time 2 A 0 30 ns -2.75 -2 PDRV Trip Level With respect to VREF, FB going low TA = +25°C NDRV Trip Level With respect to VREF, FB going high TA = +25°C PDRV, NDRV Response Time FB overdrive = 5% 75 PDRV, NDRV On-Resistance VDD = 4.5V 2 PDRV, NDRV Source/Sink Current PDRV = NDRV = 2.5V TA = 0°C to +85°C TA = 0°C to +85°C -3 1.25 -1.25 -1 2 1 2.75 3 100 100 115 FB = 0V (Foldback) 15 38 70 To full current limit BST = 12V, LX = 7V, REF = GND Ω ns 85 BST Leakage Current % A FB = 3.5V Soft-Start Time % ns 5 0.5 PDRV, NDRV Minimum On-Time Current-Limit Trip Voltage µA 1536 mV 1 / fOSC 50 µA _______________________________________________________________________________________ 3 MAX1638 High-Speed Step-Down Controller with Synchronous Rectification for CPU Power ELECTRICAL CHARACTERISTICS (VDD = VCC = D4 = +5V, PGND = AGND = D0–D3= 0V, FREQ = REF, TA = -40°C to +85°C, unless otherwise noted.) (Note 3) MAX UNITS Input Voltage Range PARAMETER VCC = VDD CONDITIONS MIN 4.5 TYP 5.5 V Input Undervoltage Lockout VCC rising edge, 1% hysteresis 3.9 4.3 V VCC Supply Current VCC = VDD = 5.5V, FB overdrive = 200mV Operating mode 3 DAC code = 11111 0.4 VREF = 0V 12 VDD Supply Current VCC = VDD = 5.5V, FB forced 200mV above regulation point, operating or shutdown mode 0.2 Reference Voltage No load Output Voltage (FB) Accuracy Over line and load (Note 1) PWROK Trip Level Switching Frequency Shutdown mode 3.448 3.5 V mA mA 3.553 V ±2.5 % Rising FB, 1% hysteresis with respect to VREF -8 -6 -4 Falling FB, 1% hysteresis with respect to VREF 6 8 10 FREQ = VCC 800 1000 1200 FREQ = REF 510 600 690 360 % kHz FREQ = AGND 240 300 Maximum Duty Cycle FREQ = VCC 84 90 DH On-Resistance BST - LX = 4.5V 0.7 2 Ω DL On-Resistance VDD = 4.5V 0.7 2 Ω Current-Limit Trip Voltage FB = 3.5V 100 130 mV 70 % Note 1: FB accuracy is 100% tested at FB = 3.5V (code 10000) with VCC = VDD = 4.5V to 5.5V and CSH - CSL = 0mV to 80mV. The other DAC codes are tested with VCC = VDD = 5V and CSH - CSL = 0. Note 2: AC load regulation sets the AC loop gain, to make tradeoffs between output filter capacitor size and transient response, and has only a slight effect on DC accuracy or DC load-regulation error. Note 3: Specifications from 0°C to -40°C are guaranteed by design, not production tested. 4 _______________________________________________________________________________________ High-Speed Step-Down Controller with Synchronous Rectification for CPU Power (TA = +25°C, using the MAX1638 evaluation kit, unless otherwise noted.) LOAD-TRANSIENT RESPONSE WITHOUT GLITCHCATCHER (COUT = 880µF) LOAD-TRANSIENT RESPONSE WITH GLITCHCATCHER MAX1638-03 MAX1638-02 MAX1638-01 LOAD-TRANSIENT RESPONSE WITHOUT GLITCHCATCHER (COUT = 440µF) A A A B C B D B 10µs/div 10µs/div 10µs/div VIN = 5V, VOUT = 2.0V, LOAD = 14A, 3A/µs A: VOUT, 50mV/div, AC COUPLED B: INDUCTOR CURRENT, 10A/div COUT = 440µF, VIN = 5V, VOUT = 2.0V, LOAD = 14A, 30A/µs C: NDRV, 5V/div A: VOUT, 100mV/div, AC COUPLED D: INDUCTOR CURRENT, B: PDRV, 5V/div 10A/div VIN = 5V, VOUT = 2.0V, LOAD = 14A, 3A/µs A: VOUT, 100mV/div, AC COUPLED B: INDUCTOR CURRENT, 10A/div FOLDBACK CURRENT LIMIT SWITCHING WAVEFORMS MAX1638-06 MAX1638-05 MAX1638-04 START-UP WAVEFORMS A A B A C B B 0 10µs/div 400µs/div VO = 2.0V NOMINAL A: VOUT = 0.5V/div B: INDUCTOR CURRENT, 5A/div VOUT = 1.3V VOUT = 2.0V 60 50 3.094 2.594 30 1.094 0.001 10 OUTPUT CURRENT (A) 100 SOURCING CURRENT 2.094 MAX1638-09 100 MAX1638-08 3.594 1.594 1 SINKING CURRENT 4.094 40 0.1 MAXIMUM DUTY CYCLE vs. SWITCHING FREQUENCY 95 MAXIMUM DUTY CYCLE (%) EFFICIENCY (%) 80 70 4.594 REFERENCE VOLTAGE (V) 90 5.094 MAX1638-07 VOUT = 3.5V VIN = 5V, VOUT = 2.5V, LOAD = 5A A: LX, 5V/div C: INDUCTOR CURRENT, 5A/div B: VOUT, 20mV/div, AC COUPLED REFERENCE VOLTAGE vs. OUTPUT CURRENT EFFICIENCY vs. OUTPUT CURRENT 100 1µs/div A: VOUT = 0.5V/div B: INDUCTOR CURRENT, 5A/div 90 85 80 75 70 65 60 55 50 0.01 0.1 1 OUTPUT CURRENT (mA) 10 0 200 400 600 800 1000 1200 SWITCHING FREQUENCY (kHz) _______________________________________________________________________________________ 5 MAX1638 __________________________________________Typical Operating Characteristics MAX1638 High-Speed Step-Down Controller with Synchronous Rectification for CPU Power ______________________________________________________________Pin Description 6 PIN NAME FUNCTION 1 BST Boost-Capacitor Bypass for High-Side MOSFET Gate Drive. Connect a 0.1µF capacitor and low-leakage Schottky diode as a bootstrapped charge-pump circuit to derive a 5V gate drive from VDD for DH. 2 PWROK 3 CSL Current-Sense Amplifier’s Inverting Input. Place the current-sense resistor very close to the controller IC, and use a Kelvin connection. 4 CSH Current-Sense Amplifier’s Noninverting Input 5, 6, 7 D2, D1, D0 Digital Inputs for Programming the Output Voltage. D0–D4 are logic inputs that set the output to a voltage between 1.3V and 3.5V (Table 2). D0–D4 are internally pulled up to VCC with 5µA current sources. 8 LG Loop Gain-Control Input. LG is a three-level input that is used to trade off loop gain vs. AC load-regulation and load-transient response. Connect LG to VCC, REF, or AGND for 2%, 1%, or 0.5% AC load-regulation errors, respectively. 9 VCC Analog Supply Input, 5V. Use an RC filter network, as shown in Figure 1. 10 REF Reference Output, 3.5V. Bypass REF to AGND with 0.1µF (min). Sources up to 100µA for external loads. Force REF below 2V to turn off the controller. 11 AGND 12 FB 13 CC1 Fast-Loop Compensation Capacitor Input. Connect a ceramic capacitor and resistor in series from CC1 to AGND. See the section Compensating the Feedback Loop. 14 CC2 Slow-Loop Compensation Capacitor Input. Connect a ceramic capacitor from CC2 to AGND. See the section Compensating the Feedback Loop. 15 FREQ Frequency-Select Input. FREQ = VCC: 1MHz FREQ = REF: 600kHz FREQ = AGND: 300kHz 16, 17 D4, D3 Digital Inputs for Programming the Output Voltage 18 NDRV GlitchCatcher N-Channel MOSFET Driver Output. NDRV swings between VDD and PGND. 19 PDRV GlitchCatcher P-Channel MOSFET Driver Output. PDRV swings between VDD and PGND. 20 VDD 5V Power Input for MOSFET Drivers. Bypass VDD to PGND within 0.2 in. (5mm) of the VDD pin using a 0.1µF capacitor and 4.7µF capacitor connected in parallel. 21 DL Low-Side Synchronous Rectifier Gate-Drive Output. DL swings between PGND and VDD. See the section BST High-Side Gate-Driver Supply and MOSFET Drivers. 22 PGND 23 LX Switching Node. Connect LX to the high-side MOSFET source and inductor. 24 DH High-Side Main MOSFET Switch Gate-Drive Output. DH is a floating driver output that swings from LX to BST, riding on the LX switching-node voltage. See the section BST High-Side Gate-Driver Supply and MOSFET Drivers. Open-Drain Logic Output. PWROK is high when the voltage on FB is within +8% and -6% of its setpoint. Analog Ground Voltage-Feedback Input. Connect FB to the CPU’s remote voltage-sense point. The voltage at this input is regulated to a value determined by D0–D4. Power Ground _______________________________________________________________________________________ High-Speed Step-Down Controller with Synchronous Rectification for CPU Power C5 0.1µF VIN = 5V C7 0.1µF C6 10µF C1 D2 CMPSH-3 VDD VCC TO VDD MAX1638 R5 10Ω R6 100k BST PWROK D0 R4 (OPTIONAL) D2 P1 LX D3 D4 N1 DH D1 C8 1µF C3 0.1µF VOUT = 1.3V TO 3.5V R1 MAX1638 R3 (OPTIONAL) LG DL N2 D1 (OPTIONAL) C2 FREQ N3 REF C4, 1.0µF CERAMIC LOCAL BYPASSING LOAD PGND CSH CC2 TO AGND R2 L1 CC2 RC1 0.056µF 1k CSL NDRV PDRV CC1 CC1 1000pF FB AGND Figure 1. Standard Application Circuit _____Standard Application Circuits The predesigned MAX1638 circuit shown in Figure 1 meets a wide range of applications with output currents up to 19A and higher. Use Table 1 to select components appropriate for the desired output current range, and adapt the evaluation kit PC board layout as necessary. This circuit represent a good set of trade-offs between cost, size, and efficiency while staying within the worst-case specification limits for stress-related parameters, such as capacitor ripple current. The MAX1638 circuit was designed for the specified frequency. Do not change the switching frequency without first recalculating component values—particularly the inductance, output filter capacitance, and RC1 resistance values. Table 2 lists the voltage adjustment DAC codes. _______________Detailed Description The MAX1638 is a BiCMOS power-supply controller designed for use in switch-mode, step-down (buck) topology DC-DC converters. Synchronous rectification provides high efficiency. It is intended to provide the high precision, low noise, excellent transient response, and high efficiency required in today’s most demanding applications. _______________________________________________________________________________________ 7 MAX1638 High-Speed Step-Down Controller with Synchronous Rectification for CPU Power REF REF1 REF4 REF3 REF2 + - AGND MAX1638 VCC CSL CSH LG SLOPE COMPENSATION BST DH RESET OSCILLATOR FREQ Q LX CONTROL AND DRIVE LOGIC REF Q SET VDD DL CC1 40k PGND CC2 10k + - gm WINDOW REF3 REF2 REF4 REF REF1 5 N FB D0–D4 PWROK PDRV NDRV Figure 2. Simplified Block Diagram 8 _______________________________________________________________________________________ High-Speed Step-Down Controller with Synchronous Rectification for CPU Power MAX1638 Table 1. Component List for Standard Applications LOAD REQUIREMENT COMPONENT 2.0V, 14A 2.0V, 19A 1.3V, 19A C1 (x3) Sanyo OS-CON 10SA220M (220µF) (x4) Sanyo/OS-CON 10SA220M (220µF) (x4) Sanyo/OS-CON 10SA220M (220µF) C2 (x4) Sanyo OS-CON 4SP220M (220µF) (x6) Sanyo OS-CON 4SP220M (220µF) (x7) Sanyo OS-CON 4SP220M (220µF) D1 (optional) Nihon NSQ03A02 Schottky diode or Motorola MBRS340 Nihon NSQ03A02 Schottky diode or Motorola MBRS340 Nihon NSQ03A02 Schottky diode or Motorola MBRS340 D2 Central Semiconductor CMPSH-3 Central Semiconductor CMPSH-3 Central Semiconductor CMPSH-3 L1 Coiltronics UP4-R47 (0.47µH, 19A, SMD) or Panasonic ETQP1F0R7H (0.70µH, 19A, 1.6mΩ, SMD) Panasonic ETQP2F1R0S (0.70µH, 23A, 0.94mΩ, SMD) Panasonic ETQP2F1R0S (0.70µH, 23A, 0.94mΩ, SMD) N1 Fairchild FDB7030L (10mΩ) or Int’l Rectifier IRL3803S (9mΩ) (x2) Fairchild FDB7030L (10mΩ) or (x2) Int’l Rectifier IRL3803S (9mΩ) (x2) Fairchild FDB7030L (10mΩ) or (x2) Int’l Rectifier IRL3803S (9mΩ) N2 Fairchild FDB7030L (10mΩ) or Int’l Rectifier IRL3803S (9mΩ) (x2) Fairchild FDB7030L (10mΩ) or (x2) Int’l Rectifier IRL3803S (9mΩ) (x2) Fairchild FDB7030L (10mΩ) or (x2) Int’l Rectifier IRL3803S (9mΩ) P1/N3 (optional) Int’l Rectifier IRF7105 (0.4Ω/0.16Ω) R1 (x2) Dale WSL-2512-R009-F (10mΩ) (x2) Dale WSR-20.007 ±1% (7mΩ) (x2) Dale WSR-20.007 ±1% (7mΩ) R2 (optional) Dale WSL-2512-R120-J (120mΩ) — — Int’l Rectifier IRF7307 (0.09Ω/0.05Ω) Int’l Rectifier IRF7307 (0.09Ω/0.05Ω) Note: Parts used in evaluation board are shown in bold. PWM Controller Block and Integrator The heart of the current-mode PWM controller is a multi-input open-loop comparator that sums three signals (Figure 2): the buffered feedback signal, the current-sense signal, and the slope-compensation ramp. This direct-summing configuration approaches ideal cycle-by-cycle control over the output voltage. The output voltage error signal is generated by an error amplifier that compares the amplified feedback voltage to an internal reference. Each pulse from the oscillator sets the main PWM latch that turns on the high-side switch for a period determined by the duty factor (approximately VOUT / VIN). The current-mode feedback system regulates the peak inductor current as a function of the output voltage error signal. Since average inductor current is nearly the same as peak current (assuming the inductor value is set relatively high to minimize ripple current), the circuit acts as a switch-mode transconductance amplifier. It pushes the second output LC filter pole, normally found in a duty-factor-controlled (voltage-mode) PWM, to a higher frequency. To preserve inner-loop stability and eliminate regenerative inductor current staircasing, a slope-compensation ramp is summed into the main PWM comparator. Under fault conditions where the inductor current exceeds the maximum current-limit threshold, the high-side latch resets, and the high-side switch turns off. Internal Reference The internal 3.5V reference (REF) is accurate to ±1% from 0°C to +85°C, making REF useful as a system reference. Bypass REF to AGND with a 0.1µF (min) ceramic capacitor. A larger value (such as 2.2µF) is recommended for high-current applications. Load regulation is 10mV for loads up to 100µA. Reference undervoltage lockout is between 2.7V and 3V. Shortcircuit current is less than 4mA. _______________________________________________________________________________________ 9 MAX1638 High-Speed Step-Down Controller with Synchronous Rectification for CPU Power Synchronous-Rectifier Driver Synchronous rectification reduces conduction losses in the rectifier by shunting the normal Schottky diode or MOSFET body diode with a low-on-resistance MOSFET switch. The synchronous rectifier also ensures proper start-up by precharging the boost-charge pump used for the high-side switch gate-drive circuit. Thus, if you must omit the synchronous power MOSFET for cost or other reasons, replace it with a small-signal MOSFET, such as a 2N7002. The DL drive waveform is simply the complement of the DH high-side drive waveform (with typical controlled dead time of 30ns to prevent cross-conduction or shoot-through). The DL output’s on-resistance is 0.7Ω (typ) and 2Ω (max). VIN = 5V D2 LEVEL TRANSLATOR GlitchCatcher Current-Boost Driver Drivers for an optional GlitchCatcher current-boost circuit are included in the MAX1638 to improve transient response in applications where several amperes of load current are required in a matter of a few tens of nanoseconds. The GlitchCatcher can be used to offset the fast drop in output voltage due to the ESR of the output capacitance. The current-boost circuit improves transient response by providing a direct path from the input to the output that circumvents the buck inductor’s filtering action. When the output drops out of regulation by more than 2%, the P-channel or N-channel switch turns on and injects current directly into the output from VIN or ground, forcing the output back into regulation. The driver’s response time is typically 75ns, and minimum on-time is typically 100ns. GlitchCatcher provides the greatest benefit when the output voltage is less than 2V, and in applications using minimum output capacitance. 10 DH N1 CONTROL AND DRIVE LOGIC C3 R4 LX VDD L1 DL N2 R3 PGND BST High-Side Gate-Driver Supply and MOSFET Drivers Gate-drive voltage for the high-side N-channel switch is generated using a flying-capacitor boost circuit (Figure 3). The capacitor is alternately charged from the +5V supply and placed in parallel with the highside MOSFET’s gate and source terminals. Gate-drive resistors (R3 and R4) can often be useful to reduce jitter in the switching waveforms by slowing down the fast-slewing LX node and reducing ground bounce at the controller IC. However, switching loss may increase. Low-value resistors from around 1Ω to 5Ω are sufficient for many applications. C1 BST MAX1638 R3 AND R4 ARE OPTIONAL Figure 3. Boost Supply for Gate Drivers Current Sense and Overload Current Limiting The current-sense circuit resets the main PWM latch and turns off the high-side MOSFET switch whenever the voltage difference between CSH and CSL from current through the sense resistor (R1) exceeds the peak current limit (100mV typical). Current-mode control provides cycle-by-cycle currentlimit capability for maximum overload protection. During normal operation, the peak current limit set by the current-sense resistor determines the maximum output current. When the output is shorted, the peak current may be higher than the set current limit due to delays in the current-sense comparator. Thus, foldback current limiting is employed where the set current-limit point is reduced from 100mV to 38mV as the output (feedback) voltage falls (Figure 4). When the short-circuit condition is removed, the feedback voltage will rise and the current-limit voltage will revert to 100mV. The foldback current-limit circuit is designed to ensure startup into a resistive load. ______________________________________________________________________________________ High-Speed Step-Down Controller with Synchronous Rectification for CPU Power 100 90 80 ILIM (%) 70 60 50 Internal Soft-Start 40 Soft-start allows a gradual increase of the internal current limit at start-up to reduce input surge currents. An internal DAC raises the current-limit threshold from 0V to 100mV in four steps (25mV, 50mV, 75mV, and 100mV) over the span of 1536 oscillator cycles. 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 VFB (%) Figure 4. Foldback Current Limit High-Side Current Sensing The common-mode input range of the current-sense inputs (CSH and CSL) extends to VCC, so it is possible to configure the circuit with the current-sense resistor on the input side rather than on the load side (Figure 5). This configuration improves efficiency by reducing the power dissipation in the sense resistor according to the duty ratio. In the high-side configuration, if the output is shorted directly to GND through a low-resistance path, the current-sense comparator may be unable to enforce a current limit. Under such conditions, circuit parasitics such as MOSFET RDS(ON) typically limit the short-circuit current to a value around the peak-current-limit setting. Attach a lowpass-filter network between the currentsense pins and resistor to reduce high-frequency common-mode noise. The filter should be designed with a time constant of around one-fifth of the on-time (130ns at 600kHz, for example). Resistors in the 20Ω to 100Ω range are recommended for R7 and R8. Connect the filter capacitors C11 and C12 from V CC to CSH and CSL, respectively. Values of 39Ω and 3.3nF are suitable for many designs. Place the current-sense filter network close to the IC, within 0.1 in (2.5mm) of the CSH and CSL pins. Overvoltage Protection When the output exceeds the set voltage, the synchronous rectifier (N2) is driven high (and N1 is driven low). This causes the inductor to quickly dissipate any stored energy and force the fault current to flow to ground. __________________Design Procedure Setting the Output Voltage Select the output voltage using the D0–D4 pins. The MAX1638 uses an internal 5-bit DAC as a feedbackresistor voltage divider. The output voltage can be digitally set from 1.3V to 3.5V using the D0–D4 inputs (Table 2). D0–D4 are logic inputs and accept both TTL and CMOS voltage levels. The MAX1638 has both FB and AGND inputs, allowing a Kelvin connection for remote voltage and ground sensing to eliminate the effects of trace resistance on the feedback voltage. (See PC Board Layout Considerations for further details.) FB input current is 0.1µA (max). The MAX1638 DAC codes (D0–D4) were designed for compatibility with the Intel VRM 8.2 specification for output voltages between 1.8V (code 00101) and 3.5V (code 10000). Codes 00110 to 01111 have also been designed for 50mV increments, allowing set voltages down to 1.300V. Code 11111 turns off the buck controller, placing the IC in a shutdown mode (0.2mA typical). Choosing the Error-Amplifier Gain Set the error-amplifier gain to match the voltage-precision requirements of the CPU used. The MAX1638’s loop-gain control input (LG) allows trade-offs in DC/AC voltage accuracy versus output filter capacitor requirements. AC load regulation can be set to 0.5%, 1%, or 2% by connecting LG as shown in Table 3. DC load regulation is typically 10 times better than AC load regulation, and is determined by the gain set by the LG pin. ______________________________________________________________________________________ 11 MAX1638 Current is limited by the source impedance and parasitic resistance of the current path, so a fuse is required in series with the +5V input to protect against lowimpedance faults, such as a shorted high-side MOSFET. Otherwise, the low-side MOSFET will eventually fail. DL will go low if the input voltage drops below the undervoltage lockout point. MAX1638 High-Speed Step-Down Controller with Synchronous Rectification for CPU Power R6 10Ω C9 0.1µF VIN = 5V C5 0.1µF C7 10µF C8 4.7µF C1 C11 3.3nF TO VDD D2 CMPSH-3 VDD VCC CSH R7 C12 39Ω 3.3nF R5 100k PWROK R1 CSL R8 39Ω D0 BST D1 D2 REF MAX1638 P1 L1 VOUT = 1.3V TO 3.5V LX LG R9 (OPTIONAL) DL NO CONNECTION C4 0.1µF R11 R10 (OPTIONAL) D3 D4 N1 DH N2 D1 (OPTIONAL) LOCAL BYPASSING C2 N3 FREQ PGND CC2 CC2 NDRV RC1 CC1 PDRV CC1 FB TO AGND REF C6, 1.0µF CERAMIC AGND Figure 5. Buck Regulator with High-Side Current Sensing 12 ______________________________________________________________________________________ LOAD High-Speed Step-Down Controller with Synchronous Rectification for CPU Power D4 D3 D2 0 0 0 D1 D0 0 0 OUTPUT VOLTAGE (V) COMPATIBILITY Table 3. LG Pin Adjustment Settings AC LOADLG REGULATION CONNECTED ERROR TO: (%) DC LOADREGULATION ERROR (%) TYPICAL AE (VGAIN/ IGAIN) 2.050 VCC 2 0.2 2 REF 1 0.1 4 GND 0.5 0.05 8 0 0 0 0 1 2.000 0 0 0 1 0 1.950 0 0 0 1 1 1.900 0 0 1 0 0 1.850 0 0 1 0 1 1.800 0 0 1 1 0 1.750 0 0 1 1 1 1.700 0 1 0 0 0 1.650 0 1 0 0 1 1.600 0 1 0 1 0 1.550 0 1 0 1 1 1.500 0 1 1 0 0 1.450 0 1 1 0 1 1.400 0 1 1 1 0 1.350 0 1 1 1 1 1.300 1 0 0 0 0 3.500 1 0 0 0 1 3.400 1 0 0 1 0 3.300 1 0 0 1 1 3.200 1 0 1 0 0 3.100 1 0 1 0 1 3.000 1 0 1 1 0 2.900 1 0 1 1 1 2.800 1 1 0 0 0 2.700 1 1 0 0 1 2.600 1 1 0 1 0 2.500 1 1 0 1 1 2.400 1 1 1 0 0 2.300 1 1 1 0 1 2.200 1 1 1 1 0 2.100 1 1 1 1 1 N/A Intel-compatible DAC codes be between 0.1 to 0.5. A higher LIR value allows for smaller inductors and better transient response, but results in higher losses and output ripple. A good compromise between size and loss is a 30% ripple current to load current ratio (LIR = 0.30), which corresponds to a peak inductor current 1.15 times higher than the DC load current. Continuation of 50mV increment to 1.3V Intel-compatible DAC codes L = ( VOUT VIN(MAX) − VOUT where f is the switching frequency, between 300kHz and 1MHz; IOUT is the maximum DC load current; and LIR is the ratio of AC to DC inductor current (typically 0.3). The exact inductor value is not critical and can be adjusted to make trade-offs among size, transient response, cost, and efficiency. Although lower inductor values minimize size and cost, they also reduce efficiency due to higher peak currents. In general, higher inductor values increase efficiency, but at some point resistive losses due to extra turns of wire exceed the benefit gained from lower AC current levels. Load-transient response can be adversely affected by high inductor values, especially at low (VIN - VOUT) differentials. The peak inductor current at full load is 1.15 x IOUT if the previous equation is used; otherwise, the peak current can be calculated using the following equation: IPEAK = IOUT + Shutdown Specifying the Inductor Three key inductor parameters must be specified: inductance value (L), peak current (IPEAK), and DC resistance (RDC). The following equation includes a constant LIR, which is the ratio of inductor peak-topeak AC current to DC load current. Typically LIR can ) VIN(MAX) x fOSC x IOUT x LIR ( VOUT VIN(MAX) − VOUT ) 2fOSC x L x VIN(MAX) The inductor’s DC resistance is a key parameter for efficient performance, and should be less than the currentsense resistor value. Calculating the Current-Sense Resistor Value Calculate the current-sense resistor value according to the worst-case minimum current-limit threshold voltage (from the Electrical Characteristics ) and the peak inductor current required to service the maximum load. ______________________________________________________________________________________ 13 MAX1638 Table 2. Output Voltage Adjustment Settings MAX1638 High-Speed Step-Down Controller with Synchronous Rectification for CPU Power Use IPEAK from the equation in the section Specifying the Inductor. RSENSE = 85mV IPEAK The high inductance of standard wire-wound resistors can degrade performance. Low-inductance resistors, such as surface-mount power metal-strip resistors, are preferred. The current-sense resistor’s power rating should be higher than the following: PSENSE ≥ (115mV)2 RSENSE In high-current applications, connect several resistors in parallel as necessary to obtain the desired resistance and power rating. Selecting the Output Filter Capacitor Output filter capacitor values are generally determined by effective series resistance (ESR) and voltagerating requirements, rather than by the actual capacitance value required for loop stability. Due to the high switching currents and demanding regulation requirements in a typical MAX1638 application, use only specialized low-ESR capacitors intended for switchingregulator applications, such as Kemet T510, AVX TPS, Sprague 595D, Sanyo OS-CON, or Sanyo GX series. Do not use standard aluminum-electrolytic capacitors, which can cause high output ripple and instability due to high ESR. The output voltage ripple is usually dominated by the filter capacitor’s ESR, and can be approximated as IRIPPLE x RESR. To ensure stability, the capacitor must meet both minimum capacitance and maximum ESR values as given in the following equations: COUT > VOUT VREF 1 + VIN(MIN) VOUT x RSENSE x fOSC RESR < RSENSE Compensating the Feedback Loop The feedback loop needs proper compensation to prevent excessive output ripple and poor efficiency caused by instability. Compensation cancels unwanted poles and zeros in the DC-DC converter’s transfer function that are due to the power-switching and filter elements with corresponding zeros and poles in the feedback network. These compensation zeros and poles are set by the compensation components CC1, 14 CC2, and RC1. The objective of compensation is to ensure stability by ensuring that the DC-DC converter’s phase shift is less than 180° by a safe margin, at the frequency where the loop gain falls below unity. Canceling the Sampling Pole and Output Filter ESR Zero Compensate the fast-voltage feedback loop by connecting a resistor and a capacitor in series from the CC1 pin to AGND. The pole from CC1 can be set to cancel the zero from the filter-capacitor ESR. Thus the capacitor at CC1 should be as follows: CC1 = COUT x RESR 10kΩ Resistor RC1 sets a zero that can be used to compensate for the sampling pole generated by the switching frequency. Set RC1 to the following: RC1 = VOUT 1 + V IN 2fOSC x CC1 The CC1 pin’s output resistance is 10kΩ. Setting the Dominant Pole and Canceling the Load and Output Filter Pole Compensate the slow-voltage feedback loop by adding a ceramic capacitor from the CC2 pin to AGND. This is an integrator loop used to cancel out the DC loadregulation error. Selection of capacitor CC2 sets the dominant pole and a compensation zero. The zero is typically used to cancel the unwanted pole generated by the load and output filter capacitor at the maximum load current. Select CC2 to place the zero close to or slightly lower than the frequency of the unwanted pole, as follows: CC2 = 1mmho x COUT 4 x VOUT IOUT(MAX) The transconductance of the integrator amplifier at CC2 is 1mmho. The voltage swing at CC2 is internally clamped around 2.4V to 3V minimum and 4V to VCC maximum to improve transient response times. CC2 can source and sink up to 100µA. Choosing the MOSFET Switches The two high-current N-channel MOSFETs must be logic-level types with guaranteed on-resistance specifications at VGS = 4.5V. Lower gate-threshold specs are better (i.e., 2V max rather than 3V max). Gate charge ______________________________________________________________________________________ High-Speed Step-Down Controller with Synchronous Rectification for CPU Power 2 PD (high side) = ILOAD 2 PD (low side) = ILOAD x RDS(ON) x VOUT VIN V x RDS(ON) x 1 − OUT VIN Gate-charge losses are dissipated in the IC, and do not heat the MOSFETs. Ensure that both MOSFETs are at a safe junction temperature by calculating the temperature rise according to package thermal-resistance specifications. The high-side MOSFET’s worst-case dissipation occurs at the maximum output voltage and minimum input voltage. For the low-side MOSFET, the worst case is at the maximum input voltage when the output is shortcircuited (consider the duty factor to be 100%). Calculating IC Power Dissipation Power dissipation in the IC is dominated by average gate-charge current into both MOSFETs. Average current is approximately: IDD = (QG1 + QG2) x fOSC where I DD is the drive current, Q G is the total gate charge for each MOSFET, and fOSC is the switching frequency. Power dissipation of the IC is: PD = ICC x VCC + IDD x VDD where ICC is the quiescent supply current of the IC. Junction temperature for the IC is primarily a function of the PC board layout, since most of the heat is removed through the traces connected to the pins and the ground and power planes. A 24-pin SSOP on a typical four-layer board with ground and power planes show equivalent thermal impedance of about 60°C/W. Junction temperature of the die is approximately: TJ = PD x θJA + TA where TA is the ambient temperature and θJA is the equivalent junction-to-ambient thermal impedance. Selecting the Rectifier Diode The rectifier diode D1 is a clamp that catches the negative inductor swing during the 30ns typical dead time between turning off the high-side MOSFET and turning on the low-side MOSFET synchronous rectifier. D1 must be a Schottky diode, to prevent the MOSFET body diode from conducting. It is acceptable to omit D1 and let the body diode clamp the negative inductor swing, but efficiency will drop about 1%. Use a 1N5819 diode for loads up to 3A, or a 1N5822 for loads up to 10A. Adding the BST Supply Diode and Capacitor A signal diode, such as a 1N4148, works well for D2 in most applications, although a low-leakage Schottky diode provides slightly improved efficiency. Do not use large power diodes, such as the 1N4001 or 1N5817. Exercise caution in the selection of Schottky diodes, since some types exhibit high reverse leakage at high operating temperatures. Bypass BST to LX using a 0.1µF capacitor. Selecting the Input Capacitors Place a 0.1µF ceramic capacitor and 10µF capacitor between VCC and AGND, as well as between VDD and PGND, within 0.2 in. (5mm) of the VCC and VDD pins. Select low-ESR input filter capacitors with a ripplecurrent rating exceeding the RMS input ripple current, connecting several capacitors in parallel if necessary. RMS input ripple current is determined by the input voltage and load current, with the worst-possible case occurring at VIN = 2 x VOUT: IRMS = ILOAD (MAX) VOUT (VIN − VOUT ) VIN IRMS = IOUT / 2 when VIN = 2VOUT Choosing the GlitchCatcher MOSFETs P-channel and N-channel switches and a series resistor are required for the current-boost circuit (Figure 6). Current through the MOSFETs and current-limiting resistors must be sufficient to supply the load current, with enough extra for prompt output regulation without excessive overshoot. Design for boost-current values 1.5 times the maximum load current, and choose MOSFETs and current-limiting resistors such that: RDSON,P(MAX) + RLIMIT ≈ VIN − VOUT 1.5 IOUT(MAX) and RDSON,N(MAX) + RLIMIT ≈ VOUT 1.5 IOUT(MAX) Gate resistors may be required to slow the transition edges. ______________________________________________________________________________________ 15 MAX1638 should be less than 200nC to minimize switching losses and reduce power dissipation. I2R losses are the greatest heat contributor to MOSFET power dissipation and are distributed between the high- and low-side MOSFETs according to duty factor, as follows: MAX1638 High-Speed Step-Down Controller with Synchronous Rectification for CPU Power __________Applications Information INPUT 5V Efficiency Considerations Refer to the MAX796–MAX799 data sheet for information on calculating losses and improving efficiency. C8 (OPTIONAL) P1 PC Board Layout Considerations Good PC board layout and routing are required in highcurrent, high-frequency switching power supplies to achieve good regulation, high efficiency, and stability. The PC board layout artist must be provided with explicit instructions concerning the placement of power-switching components and high-current routing. It is strongly recommended that the evaluation kit PC board layouts be followed as closely as possible. Contact Maxim’s Applications Department concerning the availability of PC board examples for higher-current circuits. In most applications, the circuit is on a multilayer board, and full use of the four or more copper layers is recommended. Use the top layer for high-current power and ground connections. Leave the extra copper on the board as a pseudo-ground plane. Use the bottom layer for quiet connections (REF, FB, AGND), and the inner layers for an uninterrupted ground plane. A ground plane and pseudo-ground plane are essential for reducing ground bounce and switching noise. Place the high-power components (C1, R1, N1, D1, N2, L1, and C2 in Figure 1) as close together as possible. Minimize ground-trace lengths in high-current paths. The surface-mount power components should be butted up to one another with their ground terminals almost touching. Connect their ground terminals using a wide, filled zone of top-layer copper (the pseudoground plane), rather than through the internal ground plane. At the output terminal, use vias to connect the top-layer pseudo-ground plane to the normal innerlayer ground plane at the output filter capacitor ground terminals. This minimizes interference from IR drops and ground noise, and ensures that the IC’s AGND is sensing at the supply’s output terminals. Minimize high-current path trace lengths. Use very short and wide traces. From C1 to N1: 0.4 in. (10mm) max length; D1 anode to N2: 0.2 in. (5mm) max length; LX node (N1 source, N2 drain, D1 cathode, inductor L1): 0.6 in. (15mm) max length. R2 (OPTIONAL) OUTPUT 1.3V TO 3.5V C2 (OPTIONAL) NDRV LOAD N3 MAX1638 PDRV Figure 6. GlitchCatcher Circuit __________________Pin Configuration TOP VIEW BST 1 24 DH PWROK 2 23 LX CSL 3 22 PGND CSH 4 21 DL D2 5 MAX1638 20 VDD D1 6 19 PDRV D0 7 18 NDRV LG 8 17 D3 VCC 9 16 D4 REF 10 15 FREQ AGND 11 14 CC2 FB 12 13 CC1 SSOP/QSOP* *Future package ___________________Chip Information TRANSISTOR COUNT: 3135 SUBSTRATE CONNECTED TO AGND 16 ______________________________________________________________________________________