19-3319; Rev 1; 8/04 KIT ATION EVALU E L B A IL AVA Dynamically Adjustable 6-Bit VID Step-Down Controller The MAX8720 step-down controller is intended for core CPU DC-DC converters in notebook computers. It features a dynamically adjustable output, ultra-fast transient response, high DC accuracy, and the high efficiency needed for leading-edge CPU core power supplies. MAXIM’s proprietary Quick-PWM™ quick-response, constant-on-time, PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency. The output voltage can be dynamically adjusted through the 6-bit digital-to-analog converter (DAC) over a 0.275V to 1.850V range in 25mV steps. The MAX8720 has independent four-level logic inputs for setting the suspend voltage (S0-S1). Precision slew-rate control provides “just-in-time” arrival at the new DAC setting, minimizing surge currents to and from the battery. The internal DAC of the MAX8720 is synchronized to the slew-rate clock for improved operation under aggressive power management of newer chipsets and operating systems that can make incomplete mode transitions. Remote feedback and ground-sense inputs allow easy compensation for IR drops in PC board traces. Single-stage buck conversion allows these devices to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down the 5V system supply instead of the battery) at a higher switching frequency allows the minimum possible physical size. Features ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Quick-PWM Architecture ±1% VOUT Accuracy Over Line and Load 6-Bit On-Board DAC with Input Muxes Precision-Adjustable VOUT Slew Control 0.275V to 1.850V Output Adjust Range Remote Feedback and Ground Sense Supports Voltage-Positioned Applications 2V to 28V Battery Input Range 200kHz/300kHz/550kHz/1000kHz Switching Frequency Over/Undervoltage Protection Drives Large Synchronous-Rectifier FETs 800µA (typ) ICC Supply Current 10µA (typ) Shutdown Supply Current 2V ±0.75% Reference Output PGOOD Blanking During Transition Ordering Information PART TEMP RANGE PIN-PACKAGE MAX8720EEI -40°C to +85°C 28 QSOP MAX8720ETX -40°C to +85°C 36 Thin QFN 6mm x 6mm Minimal Operating Circuit The MAX8720 is available in a 28-pin QSOP or 36-pin 6mm x 6mm thin QFN package. +5V BIAS Applications VCC VDD SHDN CPU Core Supply Converters GPU Core Supply Converters Notebook and Subnotebook Computers V+ ILIM BST AGND DH INPUT (VIN) 7V TO 28V SKIP LX SUS OUTPUT (VOUT) 0.275V TO 1.850V MAX8720 DL PGOOD Quick-PWM is a trademark of Maxim Integrated Products, Inc. PGND VID0 D0 VID1 D1 FB VID2 D2 FBS VID3 D3 VID4 D4 VID5 D5 GNDS CC REF S0 Pin Configurations appear at end of data sheet. TIME S1 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8720 General Description MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller ABSOLUTE MAXIMUM RATINGS (Note 1) VCC to AGND............................................................-0.3V to +6V VDD to PGND............................................................-0.3V to +6V AGND to PGND .....................................................-0.3V to +0.3V V+ to PGND............................................................-0.3V to +30V SHDN to AGND ......................................................-0.3V to +16V D0–D5, PGOOD, SUS, SKIP to AGND .....................-0.3V to +6V FB, FBS, GNDS to AGND ...........................-0.3V to (VCC + 0.3V) CC, ILIM, REF, TIME to AGND ...................-0.3V to (VCC + 0.3V) S0, S1, TON to AGND ................................-0.3V to (VCC + 0.3V) BST to PGND..........................................................-0.3V to +36V LX to BST..................................................................-6V to +0.3V DH to LX .....................................................-0.3V to (BST + 0.3V) DL to PGND................................................-0.3V to (VDD + 0.3V) REF Short Circuit to AGND.........................................Continuous Continuous Power Dissipation (TA = +70°C) 28-Pin QSOP (derate 10.8mW/°C above +70°C)........860mW 36-Pin TQFN (derate 26.3mW/°C above +70°C) .....2105mW Operating Temperature Extended Temperature Range .......................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +165°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: For the MAX8720EEI, AGND and PGND refer to a single pin designated GND. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, V+ = 15V, SHDN = SKIP = VDD = VCC = +5V, VOUT = 1.25V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Battery voltage, V+ Input Voltage Range 2 28 4.5 5.5 DAC codes from 0.9V to 1.85V -1 +1 DAC codes from 0.45V to 0.875V -10 +10 DAC codes from 0.275V to 0.425V -18 +18 VCC, VDD V+ = 4.5V to 28V, includes load regulation error DC Output Voltage Accuracy Line Regulation Error Remote-Sense Voltage Error FB to FBS or AGND to GNDS = 0 to 25mV FBS Input Bias Current FB, FBS GNDS Input Bias Current GNDS FB Input Resistance On-Time (Note 2) 2 5 mV 3 mV -0.2 +0.2 µA -1 +1 µA 265 kΩ 115 tON % mV VCC = 4.5V to 5.5V, V+ = 4.5V to 28V TIME Frequency Accuracy V 180 150kHz, RTIME = 120kΩ -8 +8 818kHz, RTIME = 22kΩ -12 +12 38kHz, RTIME = 470kΩ -12 +12 V+ = 5V, FB = 1.25V, TON = GND (1000kHz) 230 260 290 TON = REF (550kHz) 165 190 215 TON = open (300kHz) 320 355 390 TON = VCC (200kHz) 465 515 565 % ns V+ = 12V, FB = 1.25V _______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller (Circuit of Figure 1, V+ = 15V, SHDN = SKIP = VDD = VCC = +5V, VOUT = 1.25V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Minimum Off-Time (Note 2) SYMBOL CONDITIONS tOFF(MIN) MIN TYP MAX TON = VCC, open, or REF (200kHz, 300kHz, or 550kHz) 400 500 TON = GND (1000kHz) 300 375 UNITS ns BIAS AND REFERENCE Quiescent Supply Current (VCC) ICC FB forced above their regulation points 700 1200 µA Quiescent Supply Current (VDD) IDD FB forced above their regulation points <1 5 µA 25 40 µA Quiescent Battery Supply Current (V+) I+ Shutdown Supply Current (VCC) ICC SHDN = GND 10 25 µA Shutdown Supply Current (VDD) IDD SHDN = GND <1 5 µA SHDN = GND, VCC = VDD = 0V or 5V <1 5 µA Shutdown Battery Supply Current (V+) Reference Voltage I+ VREF Reference Load Regulation ∆VREF REF Sink Current VCC = 4.5V to 5.5V, IREF = 0 TA = +25°C to +85°C 1.985 2.00 2.015 TA = 0°C to +85°C 1.98 2.00 2.02 IREF = 0 to 50µA 0.01 REF in regulation 10 Rising edge, hysteresis = 20mV, PWM disabled below this level 4.1 V V µA FAULT DETECTION VCC Undervoltage-Lockout Threshold Output Overvoltage Trip Threshold Output Overvoltage FaultPropagation Delay 2.20 tOVP Output Undervoltage-Protection Trip Threshold Output Undervoltage FaultPropagation Delay FB forced 2% above regulation With respect to unloaded output voltage 2.25 4.4 V 2.30 V 10 65 70 µs 75 % FB forced 2% below trip threshold 10 µs PGOOD Transition Blanking Time After X = Y, clock speed set by RTIME 8 clk PGOOD Lower Trip Threshold Measured at FB with respect to unloaded output voltage, hysteresis = 1% -17 -15 -13 % PGOOD Upper Trip Threshold Measured at FB with respect to unloaded output voltage, hysteresis = 1% +13 +15 +17 % PGOOD Propagation Delay tUVP tPGOOD Falling edge, 50mV overdrive PGOOD Leakage Current IPGOOD High state, PGOOD forced to 5.5V Thermal-Shutdown Threshold TSHDN Hysteresis = 10°C PGOOD Output Low Voltage 10 ISINK = 4mA µs 0.4 V 1 µA °C +150 CURRENT LIMIT ILIM Adjustment Range 0.5 VREF V _______________________________________________________________________________________ 3 MAX8720 ELECTRICAL CHARACTERISTICS (continued) MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, V+ = 15V, SHDN = SKIP = VDD = VCC = +5V, VOUT = 1.25V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS Current-Limit Threshold (Fixed) VLIMIT VPGND - VLX, ILIM = VCC Current-Limit Threshold (Adjustable) VLIMIT VPGND - VLX Current-Limit Threshold (Negative) VNEG Current-Limit Threshold (Zero Crossing) MIN TYP MAX TA = +25°C to +85°C 90 100 110 TA = 0°C to +85°C 85 VILIM = 2.00V 165 200 230 VILIM = 0.50V 35 50 65 -140 -117 -90 VLX - VPGND, SKIP = ILIM = VCC, VZX VLX - VPGND, SKIP = VCC, adjustable mode, percent of current limit VPGND - VLX, SKIP = GND Current-Limit Default Switchover Threshold 3 115 UNITS mV mV mV -117 % 4 mV VCC 1 ILIM Leakage Current VCC 0.4 V 0.1 µA GATE DRIVERS DH Gate-Driver On-Resistance (Note 3) DL Gate-Driver On-Resistance (Note 3) RDH RDL BST-LX forced to 5V DL, high state QSOP package 1.0 3.5 TQFN package 1.0 4.5 QSOP package 1.0 3.5 TQFN package DL, low state DH Gate-Driver Source/Sink Current IDH DH forced to 2.5V, BST-LX forced to 5V 1.0 4.0 0.4 1.0 A 1.6 A A IDL (SOURCE) DL forced to 2.5V DL Gate-Driver Sink Current IDL (SINK) DL forced to 2.5V 4 DL rising 35 DH rising 26 tDEAD Ω 2 DL Gate-Driver Source Current Dead Time Ω ns INPUTS AND OUTPUTS Logic high SHDN Input Level V SHDN Logic Input High Voltage VIH Logic Input Low Voltage VIL Logic Input Current Four-Level Input Logic 2.4 Logic low 0.4 No-fault mode 12 D0–D5, SKIP, SUS 2.4 D0–D5, SKIP, SUS D0–D5, SKIP, SUS TON, S0, S1 -1 4 V 0.8 V +1 µA V High VCC 0.2 Open 3.15 3.85 REF 1.65 2.35 GND Input Leakage Current SHDN, TON, S0, S1 forced to VCC or GND V 15 0.5 -3 _______________________________________________________________________________________ +3 µA Dynamically Adjustable 6-Bit VID Step-Down Controller (Circuit of Figure 1, V+ =15V, SHDN = SKIP = VDD = VCC = +5V, VOUT = 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Battery Voltage, V+ Input Voltage Range 2 28 4.5 5.5 DAC codes from 0.9V to 1.85V -1 +1 DAC codes from 0.45V to 0.875V -15 +15 VCC, VDD V+ = 4.5V to 28V, includes load regulation error DC Output Voltage Accuracy FB Input Resistance On-Time (Note 2) tON Minimum Off-Time (Note 2) tOFF(MIN) % mV DAC codes from 0.275V to 0.425V TIME Frequency Accuracy V -18 +18 115 265 150kHz, RTIME = 120kΩ -8 +8 818kHz, RTIME = 22kΩ -12 +12 38kHz, RTIME = 470kΩ -12 +12 V+ = 5V, FB = 1.25V, TON = GND (1000kHz) 230 290 TON = REF (550kHz) 165 215 TON = open (300kHz) 320 390 TON = VCC (200kHz) 465 565 kΩ % ns V+ = 12V, FB = 1.25V TON = VCC, open, or REF (200kHz, 300kHz, or 550kHz) 500 TON = GND (1000kHz) 375 ns BIAS AND REFERENCE Quiescent Supply Current (VCC) ICC FB forced above their regulation points 1300 µA Quiescent Supply Current (VDD) IDD FB forced above their regulation points 5 µA 40 µA Quiescent Battery Supply Current (V+) I+ Shutdown Supply Current (VCC) ICC SHDN = GND 25 µA Shutdown Supply Current (VDD) IDD SHDN = GND 5 µA SHDN = GND, VCC = VDD = 0V or 5V 5 µA Shutdown Battery Supply Current (V+) Reference Voltage I+ VREF VCC = 4.5V to 5.5V, no REF load 1.98 2.02 V Rising edge, hysteresis = 20mV, PWM disabled below this level 4.1 4.4 V FAULT DETECTION VCC Undervoltage-Lockout Threshold _______________________________________________________________________________________ 5 MAX8720 ELECTRICAL CHARACTERISTICS MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, V+ =15V, SHDN = SKIP = VDD = VCC = +5V, VOUT = 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 4) PARAMETER SYMBOL CONDITIONS Output Overvoltage Trip Threshold MIN TYP MAX UNITS 2.20 2.30 V Output Undervoltage-Protection Trip Threshold With respect to unloaded output voltage 65 75 % PGOOD Lower Trip Threshold Measured at FB with respect to unloaded output voltage, hysteresis = 1% -17.5 -12.5 % PGOOD Upper Trip Threshold Measured at FB with respect to unloaded output voltage, hysteresis = 1% +12.5 +17.5 % 0.5 VREF V 80 115 mV VILIM = 2.00V 160 240 VILIM = 0.50V 33 65 -140 -85 CURRENT LIMIT ILIM Adjustment Range Current-Limit Threshold (Fixed) VLIMIT VPGND - VLX, ILIM = VCC Current-Limit Threshold (Adjustable) VLIMIT VPGND - VLX Current-Limit Threshold (Negative) VNEG VLX - VPGND, SKIP = ILIM = VCC RDH BST-LX forced to 5V mV mV GATE DRIVERS DH Gate-Driver On-Resistance (Note 3) DL Gate-Driver On-Resistance (Note 3) RDL DL, high state QSOP package 3.5 TQFN package 4.5 QSOP package 3.5 TQFN package 4.0 DL, low state Ω Ω 1.0 INPUTS AND OUTPUTS Logic high SHDN Input Level VSHDN 0.4 No-fault mode 12 2.4 Logic Input High Voltage VIH D0–D5, SKIP, SUS Logic Input Low Voltage VIL D0–D5, SKIP, SUS Four-Level Input Logic 2.4 Logic low TON, S0, S1 V 0.8 V V High VCC 0.2 Open 3.15 3.85 REF 1.65 2.35 GND V 15 0.5 Note 2: On-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0, BST forced to 5V, and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to MOSFET switching speeds. Note 3: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin QFN package. The QSOP and thin QFN package contain the same die, and the thin QFN package imposes no additional resistance in the circuit. Note 4: Specifications to -40°C are guaranteed by design, not production tested. 6 _______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller 80 VIN = 12V 70 VIN = 20V PWM MODE SWITCHING FREQUENCY (kHz) OUTPUT VOLTAGE (V) 90 400 MAX8720 toc02 VIN = 7V SKIP MODE 1.250 60 SKIP = GND SKIP = VCC 50 0.01 0.1 1 100 10 SKIP MODE 200 100 0 0 5 LOAD CURRENT (A) 10 20 15 0 5 LOAD CURRENT (A) 20 25 SUPPLY CURRENT (mA) 340 330 320 310 IOUT = 3A MAX8720 toc05 30 MAX8720 toc04 IOUT = 18A 300 15 NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (PWM MODE) 360 350 10 LOAD CURRENT (A) SWITCHING FREQUENCY vs. INPUT VOLTAGE FREQUENCY (kHz) 300 PWM MODE 1.245 290 ICC + IDD 20 15 IIN 10 5 SKIP = VCC 280 5 10 15 20 0 25 5 INPUT VOLTAGE (V) 10 15 20 25 INPUT VOLTAGE (V) NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (SKIP MODE) ICC + IDD REFERENCE VOLTAGE (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 MAX8720 toc07 0.9 REFERENCE LOAD REGULATION 2.010 MAX8720 toc06 1.0 SUPPLY CURRENT (mA) EFFICIENCY (%) 1.255 MAX8720 toc01 100 SWITCHING FREQUENCY vs. LOAD CURRENT OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 1.25V) MAX8720 toc03 EFFICIENCY vs. LOAD CURRENT (VOUT = 1.25V) 2.006 2.002 1.998 1.994 IIN 0.1 0 1.990 5 10 15 INPUT VOLTAGE (V) 20 25 -20 0 20 40 60 80 100 IREF (µA) _______________________________________________________________________________________ 7 MAX8720 Typical Operating Characteristics (MAX8720 Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, TON = open, TA = +25°C, unless otherwise noted.) MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller Typical Operating Characteristics (continued) (MAX8720 Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, TON = open, TA = +25°C, unless otherwise noted.) STARTUP WAVEFORMS (NO LOAD) STARTUP WAVEFORMS (HEAVY LOAD) MAX8720 toc08 MAX8720 toc09 1.25V 1.25V A 0 0 B 5V 0 5A 0 A 0 0 C 5V 0 10A D 0 B C D -5A 500µs/div IOUT = NO LOAD A = VOUT, 500mV/div C = SHDN, 5V/div B = PGOOD, 5V/div D = INDUCTOR CURRENT, 5A/div 500µs/div IOUT = 10A A = VOUT, 500mV/div C = SHDN, 5V/div B = PGOOD, 5V/div D = INDUCTOR CURRENT, 10A/div LOAD TRANSIENT (SKIP MODE) VCC UVLO WAVEFORM MAX8720 toc10 MAX8720 toc11 1.25V A 4V B A 1.25V 12V B 0 5V C 0 D 0 IOUT = 1A A = VOUT, 500mV/div B = VCC, 2V/div 0 0 10A C 0 D 2ms/div 20µs/div SKIP = GND, IOUT = 1A TO 11A TO 1A A = VOUT, 50mV/div C = CONTROL, 5V/div D = INDUCTOR CURRENT, 10A/div B = LX, 10V/div C = DL, 5V/div D = PGOOD, 5V/div LOAD TRANSIENT (PWM MODE) DYNAMIC OUTPUT VOLTAGE TRANSITION (SKIP MODE) MAX8720 toc12 1.25V MAX8720 toc13 A A 1.65V 1.25V 12V 12V B 0 B 0 C 0 10A C 0 10A 0 D 0 D -10A 20µs/div SKIP = VCC, IOUT = 1A TO 11A TO 1A A = VOUT, 50mV/div C = CONTROL, 5V/div B = LX, 10V/div D = INDUCTOR CURRENT, 10A/div 8 50µs/div SKIP = GND, IOUT = 0.2A A = VOUT, 200mV/div C = D4, 5V/div B = LX, 10V/div D = INDUCTOR CURRENT, 10A/div _______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller SUSPEND TRANSITION (SKIP MODE) DYNAMIC OUTPUT VOLTAGE TRANSITION (PWM MODE) MAX8720 toc15 MAX8720 toc14 A 1.65V 1.25V A 0.65V 12V 1.25V 12V B C 0 10A 0 B 0 5V 0 C 0 10A D D 0 -10A -10A 100µs/div SKIP = GND, IOUT = 0.2A A = VOUT, 500mV/div C = D4, 5V/div B = LX, 10V/div D = INDUCTOR CURRENT, 10A/div 50µs/div SKIP = VCC, IOUT = 0.2A A = VOUT, 200mV/div C = D4, 5V/div B = LX, 10V/div D = INDUCTOR CURRENT, 10A/div SUSPEND TRANSITION (PWM MODE) 25 1.25V VOUT = 1.25V SAMPLE PERCENTAGE (%) A 0.65V 12V B 0 5V C 0 10A 20 15 10 D 0 MAX8720 toc17 OUTPUT VOLTAGE DISTRIBUTION MAX8720 toc16 5 -10A 0 -0.48 100µs/div SKIP = VCC, IOUT = 0.2A A = VOUT, 500mV/div C = D4, 5V/div B = LX, 10V/div D = INDUCTOR CURRENT, 10A/div -0.24 0.00 0.24 0.48 OUTPUT VOLTAGE ERROR (%) REFERENCE VOLTAGE DISTRIBUTION SAMPLE PERCENTAGE (%) MAX8720 toc18 25 20 15 10 5 0 1.995 1.998 2.000 2.002 2.005 REFERENCE VOLTAGE (V) _______________________________________________________________________________________ 9 MAX8720 Typical Operating Characteristics (continued) (MAX8720 Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, TON = open, TA = +25°C, unless otherwise noted.) Dynamically Adjustable 6-Bit VID Step-Down Controller MAX8720 Pin Description PIN 28 QSOP 36 THIN QFN NAME 1 33 V+ Battery Voltage-Sense Connection. Connect V+ to input power source. V+ is used only for PWM one-shot timing. DH on-time is inversely proportional to input voltage over a 2V to 28V range. SHDN Shutdown Control Input. Connect SHDN to VCC for normal operation. Connect SHDN to GND to put the controller into its shutdown state. Forcing SHDN to 12V to 15V disables both the overvoltage-protection and undervoltage-protection circuits and clears the fault latch. Do not connect SHDN to >15V. Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slewrate clock. A 470kΩ to 22kΩ resistor sets the clock from 38kHz to 818kHz, fSLEW = 150kHz x 120kΩ / RTIME. To reduce inrush current, fSLEW = 150kHz x 120kΩ / 4 x RTIME during power-up and power-down transient. 2 3 35 TIME 4 1 FB Fast Feedback Input. Connect FB to the junction of the external inductor and outputcapacitor node (Figure 1). 5 2 FBS Feedback Remote-Sense Input. For nonvoltage-positioned circuits, connect FBS to VOUT directly at the load. FBS internally connects to the integrator that fine tunes the DC output voltage. For voltage-positioned circuits, connect FBS directly to FB near the IC to disable the FBS remote-sense integrator amplifier. To disable all three integrator amplifiers, connect FBS to VCC. 6 3 CC Integrator Capacitor Connection. Connect a 47pF to 1000pF (47pF typ) capacitor from CC to AGND to set the integration time constant. CC can be left open if FBS is connected to VCC. 7, 8 4, 5 S0, S1 9 7 VCC Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through a series 10Ω resistor. Bypass VCC to analog ground with a 1µF or greater ceramic capacitor. Suspend-Mode Voltage-Select Input. S0 and S1 are four-level digital inputs that select the suspend-mode VID code for the suspend-mode multiplexer inputs. If SUS is high, the suspend-mode VID code is delivered to the DAC. 10 8 TON On-Time Selection Control Input. This is a four-level input that sets the K-factor to determine DH on-time. Connect TON to the following pins for the indicated operation: GND = 1000kHz REF = 550kHz Open = 300kHz VCC = 200kHz 11 9 REF 2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.22µF or greater ceramic capacitor. The reference can source up to 50µA for external loads. Loading REF degrades output voltage accuracy according to the REF load regulation error. ILIM Current-Limit Adjustment. The PGND–LX current-limit threshold defaults to 100mV if ILIM is connected to VCC. In adjustable mode, the current-limit threshold voltage is 1/10th the voltage seen at ILIM over a 0.5V to 3.0V range. The logic threshold for switchover to the 100mV default value is approximately VCC - 1V. Connect ILIM to REF for a fixed 200mV threshold. 12 10 34 FUNCTION 10 ______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller PIN 28 QSOP 13 36 THIN QFN 11 NAME FUNCTION GNDS Ground Remote-Sense Input. For nonvoltage-positioned circuits, connect GNDS to ground directly at the load. GNDS internally connects to the integrator that fine tunes the output voltage. The output voltage rises by an amount of GNDS - AGND. For voltagepositioned circuits, increase the output voltage by biasing GNDS with a resistor-divider from REF to AGND. Open-Drain Power-Good Output. PGOOD is normally high when the output is in regulation. If VFB is not within a ±15% window of the DAC setting, PGOOD is asserted low. During DAC code transitions, PGOOD is forced high for an additional 8 clocks after the slew-rate controller finishes the transition. PGOOD is low during shutdown. PGOOD upper threshold is blanked whenever the MAX8720 is in pulse-skipping mode (SKIP = GND or SUS = high). 14 12 PGOOD 15 — GND 16 16, 17 DL 17 19 VDD Supply Voltage Input for the DL Gate Driver. Connect to the system supply voltage (+4.5V to +5.5V). Bypass VDD to power ground with a 1µF or greater ceramic capacitor. 18 20 SUS Suspend-Mode Control Input. When SUS is high, the suspend-mode VID code, as programmed by S0 and S1, is delivered to the DAC. Connect SUS to GND if the suspendmode multiplexer is not used. PGOOD upper threshold is blanked when SUS is high. 19 21 D0 20 22 SKIP 21 23 D5 22 24 D4 23 25 D3 24 26 D2 25 27 D1 26 29 BST Boost Flying-Capacitor Connection. Connect to an external capacitor and diode as shown in Figure 1. An optional resistor in series with BST allows the DH pullup current to be adjusted. 27 31 LX Inductor Connection. Connect LX to the switched side of the inductor. LX serves as the lower supply rail for the DH high-side gate driver. It also connects to the current-limit comparator and the skip-mode zero-crossing comparator. 28 32 DH High-Side Gate-Driver Output. DH swings from LX to BST. — 13 AGND Analog Ground. Connect the backside pad to AGND. — 14,15 PGND Power Ground. Also connects to the current-limit comparator. — 6, 18, 28, 30, 36 N.C. Analog and Power Ground. Also connects to the current-limit comparator. Low-Side Gate-Driver Output. DL swings from PGND to VDD. DAC Code Inputs. D0 is the LSB and D5 is the MSB for the 6-bit DAC. Pulse-Skipping Control Input. Connect SKIP to VCC for low-noise, forced-PWM mode, or connect SKIP to GND to enable pulse-skipping operation. PGOOD upper threshold is blanked when SKIP = GND. DAC Code Inputs. D0 is the LSB and D5 is the MSB for the 6-bit DAC. Not internally connected. ______________________________________________________________________________________ 11 MAX8720 Pin Description (continued) MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller R1 10Ω +5V BIAS C2 1µF R2 TO R7 (6) 100kΩ VCC VDD AGND* C1 1µF DBST V+ CIN (2) 10µF BST VID0 D0 VID1 D1 VID2 D2 VID3 D3 VID4 D4 VID5 D5 +5V BIAS R8 100kΩ DH NH L1 0.8µH CBST 0.1µF MAX8720 DL DL NL FB S1 FBS VCPU_SENSE OPEN (300kHz) TON GNDS VGND_SENSE PGOOD PWM SKIP ON SKIP CC CREF 0.22µF RILIM1 100kΩ RTIME 100kΩ RILIM2 33.2kΩ TIME CONNECT TO REMOTESENSE POINTS CCC 47pF REF SHDN OFF COUT (3) 470µF *PGND S0 SUS OUTPUT (VOUT) LX 4-LEVEL SUSPEND INPUTS PGOOD INPUT (VIN) 7V TO 28V ILIM *FOR THE MAX8720EEI, AGND AND PGND REFER TO A SINGLE PIN DESIGNATED GND Figure 1. MAX8720 Standard Application Circuit Detailed Description The MAX8720 is a constant-on-time, quick-PWM controller with 6-bit VID inputs to dynamically set the output voltage from 0.275V to 1.85V. The MAX8720 standard application circuit (Figure 1) generates a low-voltage 1.25V/15A output typical of low-power CPU and GPU core supplies in a notebook computer. The input supply range is 7V to 24V. See Table 1 for component selections and Table 2 for component manufacturers. 5V Bias Supply (VCC and VDD) The MAX8720 requires an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook’s 95%-efficient, 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the 5V supply can be generated with an external linear regulator. 12 The 5V bias supply must provide VCC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is: IBIAS = ICC + fSW (QG(LOW) + QG(HIGH)) = 4mA to 40mA (typ) where ICC is 800µA (typ), fSW is the switching frequency, and Q G(LOW) and Q G(HIGH) are the MOSFET data sheet’s total gate-charge specification limits at VGS = 5V. V+ and VDD can be connected together if the input power source is a fixed 4.5V to 5.5V supply. If the 5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup. Reference (REF) The 2V reference is accurate to ±0.75% over temperature and load, making REF useful as a precision system reference. Bypass REF to GND with a 0.22µF or greater ceramic capacitor. The reference sources up to 100µA and sinks 10µA to support external loads. Loading the reference reduces the output voltages slightly, because of the reference load regulation error. ______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller COMPONENT 15A/300kHz Table 2. Component Suppliers SUPPLIER WEBSITE AVX www.avx.com Input Voltage VIN = 7V to 24V Central Semiconductor www.centralsemi.com Output Voltage VOUT = 1.25V Coiltronics www.coiltronics.com Fairchild Semiconductor www.fairchildsemi.com CIN Input Capacitor (2) 10µF, 25V TDK C3225X7R1E106M AVX 12103D106M Taiyo Yuden TMK325BJ106MM Sanyo www.secc.co.jp COUT Output Capacitor (3) 470µF, 2.5V, 9mΩ low-ESR polymer capacitor Sanyo 2R5TPE470M9 Siliconix (Vishay) www.vishay.com Sumida www.sumida.com NH High-Side MOSFET Siliconix SI7390DP Taiyo Yuden www.t-yuden.com NL Low-Side MOSFET Siliconix SI7356DP TDK www.component.tdk.com DL Schottky Rectifier 3A, 30V, 0.45Vf Nihon EC31QS03L TOKO www.tokoam.com L1 Inductor 0.8µH, 20A, 4.9mΩ Sumida CDEP104-0R8MC-50 Free-Running, Constant-On-Time PWM Controller with Input Feed-Forward The quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode type with voltage feed-forward (Figure 2). This architecture relies on the output filter capacitor’s ESR to act as the current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a minimum off-time (400ns typ). The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the current-limit threshold, and the minimum off-time oneshot has timed out. On-Time One-Shot (TON) The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. The high-side switch on-time is inversely proportional to the battery voltage as measured by the V+ input, and proportional to the output voltage. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a con- MAX8720 Table 1. Component Selection for Standard Applications Kemet www.kemet.com Nihon www.niec.co.jp Panasonic www.panasonic.com/industrial Table 3. K-Factor TON SETTING TON FREQUENCY (kHz) K-FACTOR (µs) VCC 200 5 ±10 Open 300 3.3 ±10 REF 550 1.8 ±12.5 GND 1000 1.0 ±12.5 stant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. On-Time = K (VOUT + 0.075V) / VIN where K is set by the TON pin-strap connection and 0.075V is an approximation to accommodate the expected drop across the low-side MOSFET switch (Table 3). The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics table (±10% at 200kHz and 300kHz, and ±12% at 550kHz and 1000kHz). On-times at operating points far removed from the conditions specified in the Electrical Characteristics table can vary over a wider range. For example, the 1000kHz setting typically runs approximately 10% slower with inputs much greater than +5V due to the very short on-times required. ______________________________________________________________________________________ 13 MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller VBATT 2V TO 28V REF V+ ILIM MAX8720 TOFF TON FROM D/A ON-TIME COMPUTE TON S Q TRIG +5V ONE-SHOT TRIG Q 9 BST 1 Q R DH CURRENT LIMIT ONE-SHOT Σ LX ERROR AMP SHDN REF ZERO CROSSING VDD 10kΩ 70kΩ CC GNDS FBS REF -15% Gm +5V DL REF Gm VOUT S Q PGND R Gm FB FB REF +15% PGOOD OVP/UVP DETECT CHIP SUPPLY VCC 2V REF REF R-2R D/A CONVERTER +5V AGND MUX AND SLEW CONTROL SKIP SUS S0, S1 D0–D5 TIME Figure 2. MAX8720 Block Diagram On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics table are influenced by switching delays in the external high-side MOSFET. Resistive losses, including the inductor, both MOSFETs, output-capacitor 14 ESR, and PC board copper losses in the output and ground tend to raise the switching frequency at higher output currents. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only in PWM mode (SKIP = high) and during ______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller fSW = VOUT + VDIS t ON (VIN + VDIS − VCHG ) where VDIS is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VCHG is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PC board resistances; and tON is the on-time calculated by the MAX8720. Integrator Amplifiers and Output-Voltage Offsets Three integrator amplifiers provide a fine adjustment to the output regulation point. One amplifier integrates the difference between GNDS and AGND, and a second integrates the difference between FBS and FB. The third amplifier integrates the difference between REF and the DAC output. These three transconductance amplifiers’ outputs are directly summed inside the chip, so the integration time constant can be set easily with one capacitor. The Gm of each amplifier is 160µS (typ). The integrator block has the ability to lower the output voltage by 2% and raise it by 6%. For each amplifier, the differential input voltage range is at least ±70mV total, including DC offset and AC ripple. The integrator corrects for approximately 90% of the total error, due to finite gain. The FBS amplifier corrects for DC voltage drops in PC board traces and connectors in the output bus path between the DC-DC converter and the load. The GNDS amplifier performs a similar DC correction task for the output ground bus. The third integrator amplifier corrects the small offset of the error amplifier and provides an averaging function that forces VOUT to be regulated at the average value of the output ripple waveform. Integrators have both beneficial and detrimental characteristics. Although they correct for drops due to DC bus resistance and tighten the DC output-voltage tolerance limits by averaging the peak-to-peak output ripple, they can interfere with achieving the fastest possible loadtransient response. The fastest transient response is achieved when all three integrators are disabled. This can work very well if the MAX8720 circuit is placed very close to the CPU. All three integrators can be disabled by connecting FBS to VCC. When the integrators are disabled, CC can be left unconnected, which eliminates a component but leaves GNDS connected to any convenient ground. When the inductor is in continuous conduction, the output voltage has a DC regulation higher than the trip level by 50% of the ripple. In discontinuous conduction (SKIP = GND, light loaded), the output voltage has a DC regulation higher than the trip level by approximately 1.5% due to slope compensation. There is often a connector, or at least many milliohms of PC board trace resistance, between the DC-DC converter and the CPU. In these cases, the best strategy is to place most of the bulk bypass capacitors close to the CPU, with just one capacitor on the other side of the connector near the MAX8720 to control ripple if the CPU card is unplugged. In this situation, the remotesense lines (GNDS and FBS) and integrators provide a real benefit. Forced-PWM Mode (SKIP = High) The low-noise forced-PWM mode (SKIP = high) disables the zero-crossing comparator, allowing the inductor current to reverse at light loads. This causes the low-side gate-drive waveform to become the complement of the high-side gate-drive waveform. The benefit of forced-PWM mode is to keep the switching frequency fairly constant, but it comes at a cost: the noload battery current can be 10mA to 40mA, depending on the external MOSFETs and switching frequency. Forced-PWM mode is required during downward output-voltage transitions. The MAX8720 uses PWM mode during all transitions, but only while the slew-rate controller is active. Due to voltage positioning, when a transition uses high negative inductor current, the output voltage does not settle to its final intended value until well after the slew-rate controller terminates. Because of this it is possible, at very high negative slew currents, for the output to end up high enough to cause PGOOD to go low. Thus, it is necessary to use forced-PWM mode during all negative transitions. Most applications should use PWM mode exclusively, although there is some benefit to using skip mode while in the low-power suspend state. Automatic Pulse-Skipping Switchover (SKIP = GND) In skip mode (SKIP = GND), an inherent automatic switchover to PFM takes place at light loads (Figure 3). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. This mechanism causes the ______________________________________________________________________________________ 15 MAX8720 dynamic output-voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor’s EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH-rising dead time. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is equal to half the peak-to-peak ripple current, which is a function of the inductor value (Figure 3). For a 7V to 24V battery range, this threshold is relatively constant, with only a minor dependence on battery voltage: ILOAD(SKIP) = KVOUT (VIN − VOUT ) 2LVIN where K is the on-time scale factor (Table 2). For example, in the standard application circuit this becomes: ILOAD(SKIP) = 3.3µs × 1.25V(12V − 1.25V) = 2.31A 2 × 0.8µH × 12V The crossover point occurs at a lower value if a swinging (soft-saturation) inductor is used. The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input-voltage levels. Current-Limit Circuit The current-limit circuit employs a unique “valley” current-sensing algorithm that uses the on-resistance of the low-side MOSFET as a current-sensing element. If the current-sense signal is above the current-limit threshold, the PWM is not allowed to initiate a new cycle (Figure 4). The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact currentlimit characteristic and maximum load capability are a function of the MOSFET on-resistance, inductor value, and battery voltage. The reward for this uncertainty is robust, lossless overcurrent sensing. When combined with the undervoltage-protection circuit, this currentlimit method is effective in almost every circumstance. There is also a negative current limit that prevents excessive reverse inductor currents when V OUT is 16 sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ILIM is adjusted. The current-limit threshold is adjusted with an external resistor-divider at ILIM. The current-limit threshold voltage adjustment range is from 50mV to 200mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ILIM. The threshold defaults to 100mV when ILIM is connected to VCC. The logic threshold for switchover to the 100mV default value is approximately VCC - 1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by LX and PGND. Place the IC close to the low-side MOSFET with short, direct traces, making a Kelvin-sense connection to the source and drain terminals. MOSFET Gate Drivers (DH, DL) The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in the notebook CPU environment, where a large VIN - VOUT differential exists. An adaptive dead-time circuit monitors the DL output and prevents the high-side FET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the MAX8720 interprets the MOSFET gate as “off” while there is actually still charge left on the gate. Use very short, wide traces measuring 10 to 20 squares (50 to 100 mils wide if the MOSFET is 1in from the MAX8720). The dead time at the other edge (DH turning off) is determined by a fixed 35ns (typ) internal delay. The internal pulldown transistor that drives DL low is robust, with a 0.4Ω (typ) on-resistance. This helps prevent DL from being pulled up during the fast rise time of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier MOSFET. Applications with high input voltages and long, inductive DL traces may require additional gate-tosource capacitance to ensure fast-rising LX edges do not pull up the low-side MOSFET’s gate voltage, causing shoot-through currents. The capacitive coupling between LX and DL created by the MOSFET’s gate-todrain capacitance (CRSS), gate-to-source capacitance (CISS - CRSS), and additional board parasitics should not exceed the minimum threshold voltage: ______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller MAX8720 ∆I = ∆t IPEAK VIN - VOUT L IPEAK ILOAD = IPEAK / 2 INDUCTOR CURRENT INDUCTOR CURRENT ILOAD ILIMIT ( LIR2 ) ILIM(VAL) = ILOAD(MAX) 1- 0 ON-TIME TIME 0 Figure 3. Pulse-Skipping/Discontinuous Crossover Point Figure 4. Valley Current-Limit Threshold C VGS(TH) > VIN RSS CISS Lot-to-lot variation of the threshold voltage can cause problems in marginal designs. Typically, adding 4700pF between DL and power ground (CNL in Figure 5), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays. Alternatively, shoot-through currents may be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5Ω in series with BST slows down the high-side MOSFETs’ turn-on time, eliminating the shoot-through currents without degrading the turn-off time (RBST in Figure 5). Slowing down the high-side MOSFETs also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise. VCC POR and UVLO Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the PWM for operation. VCC undervoltage-lockout (UVLO) circuitry inhibits switching, forces PGOOD low, and forces the DL gate driver low. When VCC rises above 4.2V, the DAC inputs are sampled and the output voltage begins to slew to the DAC setting. If VCC drops low enough to trip the UVLO comparator, it is assumed that there is not enough supply voltage to make valid decisions. The MAX8720 immediately forces both DH and DL low. The output discharges to 0V at a TIME CBYP MAX8720 VDD BST (RBST)* DBST INPUT (VIN) CBST DH NH L LX VDD DL NL (CNL)* PGND (RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING-NODE RISE TIME. (CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS. Figure 5. Reducing the Switching-Node Rise Time rate dependent on the load and the total output capacitance. This prevents negative output voltages, eliminating the need for a Schottky diode to GND at the output. For automatic startup, the battery voltage should be present before VCC. If the MAX8720 attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The SHDN pin can be toggled to reset the fault latch. ______________________________________________________________________________________ 17 MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller VCC(UVLO) VCC VCC DL DL MODE FORCED-PWM MODE FORCED-PWM MODE PWM SHDN SHDN PGOOD PGOOD SOFT-STARTUP AND SHUTDOWN 1/4TH SLEW RATE SET BY RTIME VCPU VCPU 8x RTIME CLOCKS Figure 6. Soft-Startup and Soft-Shutdown Soft-Startup and Soft-Shutdown (SHDN) When SHDN goes low, the MAX8720 enters low-power shutdown mode. PGOOD goes low immediately. The output voltage ramps down to 0V in 25mV steps at 1/4th the clock rate set by RTIME. The slow rampdown of the output voltage results in smaller negative inductor currents, eliminating negative voltages on the output. When the DAC reaches the 0V setting, DL goes high, DH goes low, the reference is turned off, and the supply current drops to approximately 10µA. When SHDN goes high, the reference powers up, and after the reference UVLO is passed, the DAC target is evaluated and switching begins. The slew-rate controller ramps up from 0V in 25mV steps at 1/4th the clock rate set by R TIME to the currently selected code value (based on SUS). Full output current is available immediately. PGOOD goes high after the slew-rate controller has terminated and the output voltage is in regulation. Nominal Output Voltage Setting The MAX8720 uses a multiplexer that selects from two different inputs (Figure 7)—the VID DAC inputs or the suspend-mode S0, S1 inputs. On startup, the MAX8720 slews the target voltage from ground to either the decoded D0–D5 (SUS = low) voltage or the S0, S1 voltage (SUS = high). 18 D0 D1 D2 D3 D4 D5 SUS MUX 6-BIT CODE OUT 6-BIT CODE S0 S1 0 S0/S1 DECODER IN DAC 1 SEL OUT SUS Figure 7. Internal Multiplexers Functional Diagram DAC Inputs (D0–D5) The digital-to-analog converter (DAC) programs the output voltage. It typically receives a preset digital code from the CPU pins, which are either hardwired to GND or left open-circuit. They can also be driven by digital logic, general-purpose I/O, or an external mux. Do not leave D0–D5 floating—use 1MΩ or less pullup resistors if the inputs may float. D0–D5 can be changed while the ______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller MAX8720 Table 4. Output Voltage vs. DAC Codes D5 D4 D3 D2 D1 D0 VOUT D5 D4 D3 D2 D1 D0 VOUT 0 0 0 0 0 0 1.850 1 0 0 0 0 0 1.050 0 0 0 0 0 1 1.825 1 0 0 0 0 1 1.025 0 0 0 0 1 0 1.800 1 0 0 0 1 0 1.000 0 0 0 0 1 1 1.775 1 0 0 0 1 1 0.975 0 0 0 1 0 0 1.750 1 0 0 1 0 0 0.950 0 0 0 1 0 1 1.725 1 0 0 1 0 1 0.925 0 0 0 1 1 0 1.700 1 0 0 1 1 0 0.900 0 0 0 1 1 1 1.675 1 0 0 1 1 1 0.875 0 0 1 0 0 0 1.650 1 0 1 0 0 0 0.850 0 0 1 0 0 1 1.625 1 0 1 0 0 1 0.825 0 0 1 0 1 0 1.600 1 0 1 0 1 0 0.800 0 0 1 0 1 1 1.575 1 0 1 0 1 1 0.775 0 0 1 1 0 0 1.550 1 0 1 1 0 0 0.750 0 0 1 1 0 1 1.525 1 0 1 1 0 1 0.725 0 0 1 1 1 0 1.500 1 0 1 1 1 0 0.700 0 0 1 1 1 1 1.475 1 0 1 1 1 1 0.675 0 1 0 0 0 0 1.450 1 1 0 0 0 0 0.650 0 1 0 0 0 1 1.425 1 1 0 0 0 1 0.625 0 1 0 0 1 0 1.400 1 1 0 0 1 0 0.600 0 1 0 0 1 1 1.375 1 1 0 0 1 1 0.575 0 1 0 1 0 0 1.350 1 1 0 1 0 0 0.550 0 1 0 1 0 1 1.325 1 1 0 1 0 1 0.525 0 1 0 1 1 0 1.300 1 1 0 1 1 0 0.500 0 1 0 1 1 1 1.275 1 1 0 1 1 1 0.475 0 1 1 0 0 0 1.250 1 1 1 0 0 0 0.450 0 1 1 0 0 1 1.225 1 1 1 0 0 1 0.425 0 1 1 0 1 0 1.200 1 1 1 0 1 0 0.400 0 1 1 0 1 1 1.175 1 1 1 0 1 1 0.375 0 1 1 1 0 0 1.150 1 1 1 1 0 0 0.350 0 1 1 1 0 1 1.125 1 1 1 1 0 1 0.325 0 1 1 1 1 0 1.100 1 1 1 1 1 0 0.300 0 1 1 1 1 1 1.075 1 1 1 1 1 1 0.275 SMPS is active, initiating a transition to a new output voltage level. If this mode of DAC control is used, connect SUS low. Change D0–D5 together, avoiding greater than 50ns skew between bits. Otherwise, incorrect DAC readings may cause a partial transition to the wrong voltage level, followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages are shown in Table 4. Suspend Mode (S0, S1, SUS) When the CPU enters low-power suspend mode, the processor sets the regulator to a lower output voltage to reduce power consumption. The MAX8720 includes a suspend-mode input (S0, S1) and a digital SUS control input. The suspend voltage is programmed using the 4-level S0, S1 inputs (Table 5). The suspend voltage adjustment range is from 0.275V to 0.650V. ______________________________________________________________________________________ 19 MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller Table 5. Suspend-Mode DAC Codes S1 S0 VOUT S1 S0 VOUT GND GND GND 0.650 OPEN GND 0.450 REF 0.625 OPEN REF 0.425 GND GND OPEN 0.600 OPEN OPEN 0.400 VCC 0.575 OPEN VCC 0.375 REF REF GND 0.550 VCC GND 0.350 REF 0.525 VCC REF 0.325 REF OPEN 0.500 VCC OPEN 0.300 REF VCC 0.475 VCC VCC 0.275 When the CPU suspends operation (SUS = high), the controller overrides the 6-bit VID DAC code set by D0–D5, and slews the output voltage to the target voltage set by the S0, S1 inputs. During the transition, the MAX8720 blanks both PGOOD thresholds (PGOOD forced high impedance) until the slew-rate controller reaches the suspend-mode voltage, plus 8 extra RTIME clocks. After this blanking time expires, the MAX8720 automatically switches to a pulse-skipping control scheme regardless of SKIP. Output-Voltage-Transition Timing The MAX8720 is designed to perform output-voltage transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output-voltage level with the lowest possible peak currents for a given output capacitance. This makes the IC ideal for CPUs and GPUs that operate at different voltages. At the beginning of an output-voltage transition (VID change or SUS level change), the MAX8720 enters forced-PWM mode and blanks the PGOOD output (forced high impedance). PGOOD remains blanked during the transition and is re-enabled when the slewrate controller has set the internal DAC to the final value and 8 additional slew-rate clock periods have passed. The slew-rate clock frequency (set by resistor R TIME) must be set fast enough to ensure that the longest required transition is completed within the allowed transition time. The output-voltage transition is performed in 25mV steps, preceded by a delay and followed by one addi- 20 tional clock period. The total time for a transition depends on R TIME , the voltage difference, and the accuracy of the MAX8720’s slew-rate clock, and is not dependent on the total output capacitance. The greater the output capacitance, the higher the surge current required for the transition. The MAX8720 automatically controls the current to the minimum level required to complete the transition in the calculated time, as long as the surge current is less than the current limit set by ILIM. The transition time is given by: t TRANS = | VOLD − VNEW | + tDELAY 25mV × fSLEW where fSLEW = 150kHz x 120kΩ / RTIME, VOLD is the original DAC setting, VNEW is the new DAC setting, and tDELAY ranges from zero to a maximum of 2 / fSLEW. See Time Frequency Accuracy in the Electrical Characteristics table for f SLEW accuracy. The practical range of RTIME is 22kΩ to 470kΩ, corresponding to 1.22µs to 26µs per 25mV step. Although the DAC takes discrete 25mV steps, the output filter makes the transitions relatively smooth. The average inductor current required to make an output-voltage transition is: IL( AVE) = COUT × 25mV × fSLEW Suspend Transition (Forced-PWM Operation Selected) When the MAX8720 enters suspend mode while configured for forced-PWM operation (SKIP pulled high), the controller ramps the output voltage down to the S0, S1 programmed voltage at the slew rate determined by R TIME . The controller blanks PGOOD (forced high impedance) until the transition is completed plus 8 extra RTIME clocks—the internal target voltage equals the selected S0, S1 DAC voltage. After this blanking time expires, the controller enters pulse-skipping operation. When exiting suspend mode (SUS pulled low), the MAX8720 immediately enters forced-PWM mode and ramps the output up at the slew rate set by RTIME. The controller blanks PGOOD (forced high impedance) until the transition is completed plus 8 extra RTIME clocks— the internal target voltage equals the selected D0–D5 DAC voltage. ______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller MAX8720 VOUT HIGH VID VOLTAGE SLEW RATE SET BY RTIME LOW VID VOLTAGE SKIP SUS PGOOD HIGH IMPEDANCE D0-D5 HIGH VID MODE PWM MODE HIGH IMPEDANCE LOW VID FORCED-PWM HIGH VID PWM MODE FORCED-PWM PWM MODE 8x RTIME CLOCKS 8x RTIME CLOCKS Figure 8. VID Transition in Forced-PWM Mode (SKIP = High) VOUT HIGH VID VOLTAGE SLEW RATE SET BY RTIME LOW VID VOLTAGE SKIP SUS PGOOD LOW T'HOLD ONLY D0-D5 HIGH VID MODE SKIP MODE HIGH IMPEDANCE LOW THRESHOLD ONLY LOW VID FORCED-PWM LOW T'HOLD ONLY HIGH VID SKIP MODE 8x RTIME CLOCKS HIGH IMPEDANCE FORCED-PWM SKIP MODE 8x RTIME CLOCKS Figure 9. VID Transition in Pulse-Skipping Mode (SKIP = GND) ______________________________________________________________________________________ 21 MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller VOUT D0–D5 VOLTAGE SLEW RATE SET BY RTIME S0, S1 VOLTAGE SKIP SUS PGOOD HIGH IMPEDANCE TARGET D0–D5 MODE PWM MODE LOW THRESHOLD ONLY S0, S1 FORCED-PWM HIGH IMPEDANCE D0–D5 AUTOSKIP MODE FORCED-PWM PWM MODE 8x RTIME CLOCKS 8x RTIME CLOCKS Figure 10. Suspend Transition in Forced-PWM Mode (SKIP = High) VOUT D0–D5 VOLTAGE SLEW RATE SET BY RTIME S0, S1 VOLTAGE SKIP SUS PGOOD LOW T'HOLD ONLY TARGET D0–D5 MODE SKIP MODE HIGH IMPEDANCE LOW THRESHOLD ONLY S0, S1 FORCED-PWM HIGH IMPEDANCE LOW T'HOLD ONLY D0–D5 AUTOSKIP MODE 8x RTIME CLOCKS FORCED-PWM SKIP MODE 8x RTIME CLOCKS Figure 11. Suspend Transition in Pulse-Skipping Mode (SKIP = GND) 22 ______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller Output Overvoltage Protection The overvoltage-protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The output voltage is continuously monitored for overvoltage. If the output is more than 2.25V, OVP is triggered and the circuit shuts down. The DL low-side gate-driver output is then latched high until SHDN is toggled or VCC power is cycled below 1V. This action turns on the synchronous-rectifier MOSFET with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output to ground. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. DL is also kept high continuously in shutdown when VCC is above the UVLO threshold. Output Undervoltage Shutdown The output UVP function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX8720 output voltage is under 70% of the nominal value, the PWM is latched off and won’t restart until VCC power is cycled or SHDN is toggled. To allow startup, UVP is ignored until the internal DAC reaches the final target plus 8 extra RTIME clocks. UVP can be defeated through the no-fault test mode (see the No-Fault Test Mode section). No-Fault Test Mode The over/undervoltage-protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a test mode is provided to disable the OVP, UVP, and thermal-shutdown features, and clear the fault latch if it has been set. The no-fault test mode is entered by forcing 12V to 15V on SHDN. Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: • Input Voltage Range. The maximum value (VIN(MAX)) must accommodate the worst-case, high AC-adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. • Maximum Load Current. There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements and thus drives output-capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. • Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and V IN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. • Inductor Operating Point. This choice provides trade-offs between size vs. efficiency, and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (SKIP low and light loads), the inductor ______________________________________________________________________________________ 23 MAX8720 Suspend Transition (Pulse-Skipping Operation Selected) If the MAX8720 is configured for pulse-skipping operation (SKIP = GND) when SUS goes high, the MAX8720 immediately enters forced-PWM mode, ramping the output voltage down to the S0, S1 programmed voltage at the slew rate determined by RTIME. The controller blanks PGOOD (forced high impedance) until the transition is completed plus 8 extra R TIME clocks—the internal target voltage equals the selected S0, S1 DAC voltage. After this blanking time expires, the controller enters pulse-skipping operation. When exiting suspend mode (SUS pulled low), the MAX8720 immediately enters forced-PWM mode and ramps the output up at the slew rate set by RTIME. The controller blanks PGOOD (forced high impedance) until the transition is completed plus 8 extra RTIME clocks— the internal target voltage equals the selected D0–D5 DAC voltage. After this blanking time expires, the controller returns to pulse-skipping operation. MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller value also determines the load-current value at which PFM/PWM switchover occurs. Inductor Selection The switching frequency and inductor operating point determine the inductor value as follows: L= VOUT (VIN − VOUT ) VIN fSW ILOAD(MAX) LIR For example: ILOAD(MAX) = 15A, VIN = 12V, VOUT = 1.25V, fSW = 300kHz, 30% ripple current or LIR = 0.3 L= 1.25V × (12V − 1.25V) = 0.83µH 12V × 300kHz × 15A × 0.3 Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): LIR IPEAK = ILOAD(MAX) 1+ 2 Most inductor manufacturers provide inductors in standard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. Transient Response The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The total output-voltage sag is the sum of the voltage sag while the inductor is ramping up and the voltage sag before the next pulse can occur. V L(∆ILOAD(MAX) ) K OUT + t OFF(MIN) V IN VSAG = VIN − VOUT 2COUT VOUT K − t OFF(MIN) VIN where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics) and K is from Table 3. 24 The amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: VSOAR ≈ (∆ILOAD(MAX) )2L 2COUT VOUT Setting the Current Limit The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The peak inductor current occurs at ILOAD(MAX) plus half the ripple current; therefore: LIR ILIMIT(LOW) > ILOAD(MAX) 1− 2 where I LIMIT(LOW) equals the minimum current-limit threshold voltage divided by the RDS(ON) of NL. For the 100mV default setting, the minimum current-limit threshold is 90mV. Connect ILIM to VCC for a default 100mV current-limit threshold. For an adjustable threshold, connect a resistor-divider from REF to GND, with ILIM connected to the center tap. The external adjustment range of 0.5V to 2.0V corresponds to a current-limit threshold of 50mV to 200mV. When adjusting the current limit, use 1% tolerance resistors and a 10µA divider current to prevent a significant increase of errors in the current-limit tolerance. Output Capacitor Selection The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. The output capacitance must be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault protection. When using high-capacitance, low-ESR capacitors (see the Output-Capacitor Stability Requirements section), the filter capacitor’s ESR dominates the output voltage ripple. Thus, the output capacitor’s size depends on the maximum ESR required to meet the output-voltageripple (VRIPPLE(P-P)) specifications: VRIPPLE(P−P) = RESR IILOAD(MAX) LIR In CPU VCORE converters and other applications where the output is subject to violent load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too ______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller RESR ≤ VSTEP / ILOAD(MAX) The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high-ESR zeros that may affect the overall stability (see the OutputCapacitor Stability Considerations section). Output-Capacitor Stability Considerations Stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: f fESR ≤ SW π 1 where fESR = 2π RESR COUT A voltage-positioned circuit has the ESR zero frequency lowered due to the external resistor in series with the output-capacitor ESR, guaranteeing stability. For a voltage-positioned circuit, the minimum ESR requirement of the output capacitor is reduced by the voltage-positioning resistor value. The boundary condition of instability is given by the following equation: RESR x COUT ≥ 1 / (2 x fSW) For good phase margin, it is recommended to increase the equivalent RC time constant by a factor of two. The standard application circuit (Figure 1) operating at 300kHz with COUT = 1410µF and RESR = 3mΩ easily meets this requirement. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. Do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. Unstable operation manifests itself in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the 400ns minimum offtime period has expired. Double pulsing is more of a nuisance than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. Input Capacitor Selection The input capacitor must meet the ripple-current requirement (IRMS) imposed by the switching currents defined by the following equation: IRMS = IOUT(MAX) VIN VOUT (VIN − VOUT ) For most applications, nontantalum chemistries (ceramic or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a switch or a connector in series with the battery. If the MAX8720 is operated as the second stage of a twostage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal reliability and lifetime. Power MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are ______________________________________________________________________________________ 25 MAX8720 low under a load transient. Ignoring the sag due to finite capacitance: MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, maximum efficiency is achieved by selecting a high-side MOSFET (N H) that has conduction losses equal to the switching losses. Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., SO-8, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX8720 DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drainto-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur. Switching losses are not an issue for the lowside MOSFET since it is a zero-voltage switched device when used in the step-down topology. Power MOSFET Dissipation Worst-case conduction losses occur at the duty-factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage: V PD (NH RESISTIVE) = OUT (ILOAD )2 × RDS(ON) VIN Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: PD (NH SWITCHING) = (VIN(MAX) )2 CRSS fSW ILOAD For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum battery voltage: V PD (NL RESISTIVE) = 1 − OUT (ILOAD )2 RDS(ON) VIN(MAX) The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than ILOAD(MAX) but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, “overdesign” the circuit to tolerate: ILOAD(MAX) LIR ILOAD = ILIMIT − 2 where ILIMIT is the peak current allowed by the currentlimit circuit, including threshold tolerance and senseresistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward-voltage drop low enough to prevent the low-side MOSFET’s body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3rd of the load current. This diode is optional and can be removed if efficiency is not critical. Boost Capacitors The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1µF ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1µF. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs’ gates: IGATE where CRSS is the reverse transfer capacitance of NH, and IGATE is the peak gate-drive source/sink current (2A typ). 26 Switching losses in the high-side MOSFET can become a heat problem when maximum AC-adapter voltages are applied, due to the squared term in the switchingloss equation (C x VIN2 x fSW). If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. CBST = N × QGATE 200mV ______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller CBST = 1× 14nC = 0.07µF 200mV Select the closest standard value. This example requires a 0.1µF ceramic capacitor. Applications Information Dropout Performance The output-voltage adjust range for continuous-conduction operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot (375ns max at 1000kHz). For best dropout performance, use the slower (200kHz) on-time settings. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table 3). Also, keep in mind that transientresponse performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the V SAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN) as much as it ramps up during the on-time (∆IUP). The ratio h = ∆IUP / ∆IDOWN is an indicator of the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current is less able to increase during each switching cycle and V SAG greatly increases unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but this may be adjusted up or down to allow tradeoffs between V SAG , output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: VIN(MIN) = VOUT + VDIS + VCHG − VDIS t OFF(MIN) × h − 1 K where VDIS and VCHG are the parasitic voltage drops in the discharge and charge paths, respectively (see the On-Time One-Shot (TON) section), tOFF(MIN) is from the Electrical Characteristics table, and K is taken from Table 3. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable V SAG . If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response. Dropout Design Example: VOUT = 1.6V fSW = 550kHz K = 1.8µs, worst-case K = 1.58µs tOFF(MIN) = 500ns VDIS = VCHG = 100mV h = 1.5 VIN(MIN) = (1.6V + 0.1V) / (1 - 0.5µs x 1.5 / 1.58µs) + 0.1V - 0.1V = 3.2V Calculating again with h = 1 gives the absolute limit of dropout: VIN(MIN) = (1.6V + 0.1V) / (1 - 0.5µs x 1.0 / 1.58µs) + 0.1V - 0.1V = 2.5V Therefore, VIN must be greater than 2.5V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance is 3.2V. One-Stage (Battery Input) vs. Two-Stage (5V Input) Applications The MAX8720 can be used with a direct battery connection (one stage) or can obtain power from a regulated 5V supply (two stage). Each approach has advantages, and careful consideration should go into the selection of the final design. The one-stage approach offers smaller total inductor size and fewer capacitors overall due to the reduced demands on the 5V supply. The transient response of the single stage is better due to the ability to ramp up the inductor current faster. The total efficiency of a single stage is better than the two-stage approach. The two-stage approach allows flexible placement due to smaller circuit size and reduced local power dissipation. The power supply can be placed closer to the CPU for better regulation and lower I2R losses from PC board traces. Although the two-stage design has worse transient response than the single stage, this can be offset by the use of a voltage-positioned converter. ______________________________________________________________________________________ 27 MAX8720 where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET’s data sheet. For example, assume the IRF7821 n-channel MOSFET is used on the high side. According to the manufacturer’s data sheet, a single IRF7821 has a maximum gate charge of 14nC (VGS = 5V). Using the above equation, the required boost capacitance is: MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller QSOP LAYOUT EXAMPLE QFN LAYOUT EXAMPLE CC VCC REF VDD ANALOG GROUND POWER GROUND CONNECT AGND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN CONNECT AGND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN CIN COUT COUT INPUT COUT OUTPUT INDUCTOR ANALOG GROUND POWER GROUND GROUND CIN POWER STAGE LAYOUT EXAMPLE Figure 12. PC Board Layout Example PC Board Layout Guidelines Careful PC board layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 12). If possible, mount all of the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PC board layout: • Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. • Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing 28 PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. • When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. • Route high-speed switching nodes (BST, LX, DH, and DL) away from sensitive analog areas (REF, FB). ______________________________________________________________________________________ Dynamically Adjustable 6-Bit VID Step-Down Controller 4) Make the DC-DC controller ground connections as shown in Figures 1 and 12. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go, and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC. 5) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical. Chip Information TRANSISTOR COUNT: 7190 PROCESS: BiCMOS Pin Configurations 27 LX TIME 3 26 BST 36 35 34 33 32 31 30 29 28 FB 4 25 D1 FBS 5 24 D2 LX N.C. BST N.C. SHDN 2 V+ DH 28 DH TIME SHDN V+ 1 N.C. TOP VIEW S0 7 22 D4 S1 8 21 D5 CC S0 S1 N.C. 20 SKIP VCC 7 21 TON 10 19 D0 TON REF 8 20 D1 D2 D3 D4 D5 SKIP D0 SUS 9 19 VDD REF 11 18 SUS ILIM 12 17 VDD GNDS 13 16 DL 26 3 25 4 24 5 23 MAX8720ETX 6 22 DL 10 11 12 13 14 15 16 17 18 N.C. VCC 9 23 D3 27 2 ILIM MAX8720EEI 1 GNDS PGOOD AGND PGND PGND DL CC 6 FB FBS 15 GND PGOOD 14 QSOP THIN QFN 6mm x 6mm ______________________________________________________________________________________ 29 MAX8720 Layout Procedure 1) Place the power components first, with ground terminals adjacent (NL source, C IN, C OUT , and DL anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the back side opposite NL and NH to keep LX, GND, DH, and the DL gate-drive lines short and wide. The DL and DH_ gate traces must be short and wide (50 to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive deadtime sensing. 3) Group the gate-drive components (BST diode and capacitor, VDD bypass capacitor) together near the controller IC. Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QSOP.EPS MAX8720 Dynamically Adjustable 6-Bit VID Step-Down Controller PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH 21-0055 30 ______________________________________________________________________________________ E 1 1 Dynamically Adjustable 6-Bit VID Step-Down Controller QFN THIN 6x6x0.8.EPS D2 D CL D/2 b D2/2 k E/2 E2/2 (NE-1) X e E CL E2 k e L (ND-1) X e e L CL CL L1 L L e A1 A2 e A PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 1 2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX8720 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)