19-2192; Rev 0; 10/01 Dual-Rate Fibre Channel Repeaters Features ♦ Pin Selectable 1.0625Gbps/2.125Gbps Dual-Rate Fibre Channel Operation ♦ Exceeds Fibre Channel Jitter Tolerance Requirements ♦ 1400mV Differential Output Swing ♦ +3.0V to +3.6V Operation ♦ No Reference Clock Required ♦ Frequency Lock Indication ♦ 290mW Power Consumption (MAX3775) at +3.3V ♦ 100Ω/150Ω (differential) Input/Output Terminations Ordering Information PART Applications 1.0625Gbps/2.125Gbps Dual-Rate Fibre Channel Fibre Channel Data Storage Systems TEMP. RANGE PIN-PACKAGE MAX3772CEE 0°C to +70°C 16 QSOP-EP MAX3773CEE 0°C to +70°C 16 QSOP-EP MAX3774CEE 0°C to +70°C 16 QSOP-EP MAX3775CEE 0°C to +70°C 16 QSOP-EP Storage Area Networks Fibre Channel Hubs Pin Configuration appears at end of data sheet. 100Ω/150Ω (Differential) Impedance Transformation Selector Guide appears at end of data sheet. Typical Operating Circuits LIN+ LIN- CLK+ LOUT- LOUT+ CF- CF+ LOCK LIN+ LIN- LOUT- LOUT+ 0.047µF CLK- 3.3V 3.3V PORT BYPASS CIRCUIT OUT+ Zo = 75Ω IN- OUT- 3.3V 0.1µF 0.1µF IN+ MAX3750 OUT- IN- Zo = 75Ω GND Zo = 75Ω GND SEL VCC OUT- VCC IN- OUT+ SEL MAX3775 VCC IN+ GND Zo = 75Ω RATESEL OUT+ MAX3750 CLKEN IN+ FIBRE CHANNEL REPEATER 0.1µF PORT BYPASS CIRCUIT ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3772–MAX3775 General Description The MAX3772–MAX3775 are dual-rate (1.0625Gbps and 2.125Gbps) fibre channel repeaters. They are optimized for use in fibre channel arbitrated loop applications and operate from a +3.3V supply. The MAX3772–MAX3775 exceed fibre channel jitter tolerance requirements and can recover data signals with up to 0.7 unit interval (UI) jitter. The circuit’s fully integrated phase-locked loop (PLL) provides a frequency lock indication and does not need an external reference clock. These repeaters provide low-jitter CML clock and data outputs, and are pin compatible with the MAX3770 repeater (except RATESEL pin and exposed paddle). The MAX3773/MAX3774 can also be used for impedance transformation between 100Ω (differential) and 150Ω (differential) systems. To reduce the number of external components, all signal inputs and outputs are internally terminated. The MAX3772–MAX3775 are available in 16-pin QSOP-EP packages. MAX3772–MAX3775 Dual-Rate Fibre Channel Repeaters ABSOLUTE MAXIMUM RATINGS VCC ........................................................................-0.5V to +5.0V Pin Voltage Levels (IN±, CF±, RATESEL, CLKEN, LOCK) .....................-0.5V to (VCC + 0.5V) Current into LOCK...............................................-1mA to +10mA CML Output Currents (OUT±, CLK±), ROUT = 75Ω ........ +22mA CML Output Currents (OUT±, CLK±), ROUT = 50Ω ........ +33mA Continuous Power Dissipation (TA = +70°C) 16-Pin QSOP-EP (derate 18.9mW/°C above +70°C) ...702mW Operating Junction Temperature Range ...........-55°C to +150°C Operating Temperature Range .........................-55°C to +110°C Storage Temperature Range ............................-55°C to +150°C Lead Temperature (soldering, 10s) ................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, 8B/10B data coding, CF = 0.047µF, lock pin loaded with ≥ 15kΩ resistor, all high-speed inputs and outputs AC-coupled, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER CONDITIONS CLKEN = GND Supply Current (Note 1) CLKEN = VCC Differential Voltage Signal at OUT+ Differential Voltage Signal at CLK+ TYP MAX MAX3772/MAX3773 80 101 140 MAX3774/MAX3775 68 88 124 MAX3772/MAX3773 115 146 195 MAX3774/MAX3775 95 121 164 MAX3772/MAX3773, 100Ω terminated 1000 1400 1800 MAX3774/MAX3775, 150Ω terminated 1000 1400 1800 MAX3772/MAX3773 100Ω terminated 1000 1400 1800 MAX3774/MAX3775, 150Ω terminated 1000 1400 1800 mA mVp-p Figure 1 Figure 1 UNITS mVp-p 1.0625Gbps operation, RATESEL = GND -100 +100 2.125Gbps operation, RATESEL = VCC -100 +100 20% to 80% 1.0625Gbps operation 136 325 20% to 80% 2.125Gbps operation 75 160 Data Transition Time (OUT±) 20% to 80% (Note 2) 100 130 175 ps Clock Transition Time (CLK±) 20% to 80% (Note 2) 50 75 100 ps LOCK Output Low IOL = +250µA (sinking) LOCK Output High IOH = -100µA (sourcing) Input Data Rate Range Input Edge Speed 0.4 2.4 CLKEN, RATESEL Input Current -50 CLKEN, RATESEL Input Low -0.3 CLKEN, RATESEL Input High (Note 2) CDR Lock Time Input = CJTPAT (Note 3) V µA 0.8 V VCC 0.45 Differential Voltage across CF+ ps 50 VCC + 0.3 2200 200 Input Common-Mode Voltage ppm V 2 Differential Input Voltage Swing 2 MIN _______________________________________________________________________________________ mVp-p V VCC 500 V V µs Dual-Rate Fibre Channel Repeaters (VCC = +3.0V to +3.6V, 8B/10B data coding, CF = 0.047µF, lock pin loaded with ≥ 15kΩ resistor, all high-speed inputs and outputs AC-coupled, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) MIN TYP MAX Differential Input Resistance (IN+) PARAMETER MAX3772/MAX3774 78 100 122 MAX3773/MAX3775 118 150 182 Differential Output Resistance (OUT+, CLK+) MAX3772/MAX3773 78 100 122 MAX3774/MAX3775 118 150 182 Supply Noise Tolerance (Note 4) CONDITIONS 10Hz ≤ f < 100Hz 100 100Hz ≤ f < 1MHz 40 1MHz ≤ f < 2.5GHz OPERATION AT 2.125Gbps (Note 2) Input = K28.7 (Note 5) Random Jitter Generation at Input = CRPAT (Note 6) OUT+ and CLK+ Input = CRPAT (Notes 6, 7) Deterministic Jitter on OUT+ Total Jitter at OUT+ Sinusoidal Component of Jitter Tolerance (BER = 10-12) Ω mVp-p 4.4 psRMS 2.8 2.9 22 Input = RPAT (Notes 7, 9) 48 Input = RPAT (Notes 7, 9, 10) 99 f = 85kHz 1.5 f = 1270kHz 0.1 f = 10MHz 0.1 Total High-Frequency Jitter Tolerance Jitter Transfer Bandwidth Measured with 50% edge density Jitter Transfer Peaking (Note 11) Input = CJTPAT (Notes 3, 7, 9) Falling clock to data transition 150 psp-p psp-p UI 0.7 Propagation Delay Clock to Q Delay Ω 10 Input = K28.5 (Note 8) Input = CJTPAT (Notes 3, 7) UNITS UI 11 MHz 0.05 dB 1.0 1.5 ns 280 300 ps OPERATION AT 1.0625Gbps (Note 2) Random Jitter Generation at OUT+ and CLK+ Deterministic Jitter on OUT+ Total Jitter at OUT+ Sinusoidal Component of Jitter Tolerance (BER = 10-12) Input = K28.7 (Note 5) 6.2 Input = CRPAT (Note 6) 3.6 Input = CRPAT (Notes 6, 7) 4.9 Input = K28.5 (Note 8) 40 Input = RPAT (Notes 7, 9) 75 Input = RPAT (Notes 7, 9, 10) Input = CJTPAT (Notes 3, 7) 160 f = 42.5kHz 1.5 f = 635kHz 0.1 f = 5MHz 0.1 Total High-Frequency Jitter Tolerance Input = CJTPAT (Notes 3, 7, 9) Jitter Transfer Bandwidth Measured with 50% edge density Jitter Transfer Peaking (Note 11) Falling clock to data transition 0.7 200 psp-p psp-p UI UI Propagation Delay Clock to Q Delay psRMS 510 6 MHz 0.05 dB 5 ns 740 ps _______________________________________________________________________________________ 3 MAX3772–MAX3775 ELECTRICAL CHARACTERISTICS (continued) MAX3772–MAX3775 Dual-Rate Fibre Channel Repeaters ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, 8B/10B data coding, CF = 0.047µF, lock pin loaded with ≥ 15kΩ resistor, all high-speed inputs and outputs AC-coupled, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) Note 1: Supply current includes output currents. Note 2: Guaranteed by design and characterization. Note 3: Compliant jitter tolerance pattern in hex (CJTPAT): Pattern Sequence: 3E AA 2A AA AA 3E AA A6 A5 A9 87 1E 38 71 E3 87 1E 38 70 BC 78 F4 AA AA AA AA AA AA AA AA AA A1 55 55 E3 87 1E 38 71 E1 AB 9C 96 86 E6 C1 6A AA 9A A6 Note 4: Meets jitter output specifications with noise applied. Note 5: K28.7 Pattern: 00 1111 1000. Note 6: Compliant random pattern in hex (CRPAT): Pattern Sequence: Repetitions: 6 1 41 1 12 1 1 1 Repetitions: 3E AA 2A AA AA 6 3E AA A6 A5 A9 1 86 BA 6C64 75 D0 E8 DC A8 B4 79 49 EA A6 65 16 72 31 9A 95 AB 1 C1 6A AA 9A A6 1 Note 7: Parameter measured with 0.40UI deterministic jitter (patterns other than K28.7), and 0.20UI random jitter (BER = 10 -12) applied to the input. Jitter is in compliance with the inter-enclosure, fibre channel jitter tolerance (at compliance point αR) and jitter output (at compliance point αT) specifications (FC-PI rev 10.0). Output jitter is specified as an output total given a non-zero jitter input. Note 8: K28.5 Pattern: 00 1111 1010 11 0000 0101 Note 9: Random Pattern in hex (RPAT): 3EB0 5C67 85D3 172C A856 D84B B6A6 65 Note 10: Using differential drive over the entire input amplitude range. The input signal bandwidth is limited to 0.75 x (bit-rate) by a 4thorder Bessel Thompson filter or equivalent. Total jitter (TJ) is the range of the eye pattern where the BER exceeds 10-12. TJ can be estimated as TJ = DJ + 14 x RJ. DJ is deterministic jitter. RJ is a one sigma distribution (RMS) of random jitter. Note 11: Simulation shows peaking of 0.01dB max. Characterization results limited by test equipment. 4 _______________________________________________________________________________________ Dual-Rate Fibre Channel Repeaters 1.0625Gbps JITTER TRANSFER vs. FREQUENCY -4 -5 -6 200mVp-p INPUT SIGNAL, PATTERN = CRPAT -9 -3 -4 -5 -6 -7 -8 200mVp-p INPUT SIGNAL, PATTERN = CRPAT 10 1 FIBRE CHANNEL MASK -9 -10 10k 100k 1M -10 10M 0.1 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) 1.0625Gbps JITTER TOLERANCE OUTPUT EYE DIAGRAM AT OUT± (2.125Gbps CRPAT) 1M 100k 10M OUTPUT EYE DIAGRAM AT OUT± (1.0625Gbps CRPAT) MAX3772-75 toc05 CJTPAT PATTERN, DJ = 0.4UI RJ = 0.2UI TOLERANCE EXCEEDS THE TEST EQUIPMENT'S GENERATION LIMIT 10k FREQUENCY (Hz) MAX3772 toc04 100 10 INPUT = 600mV DJ = 0.4UI RJ = 0.2UI INPUT = 600mV DJ = 0.4UI RJ = 0.2UI 1 FIBRE CHANNEL MASK 0.1 10k 1M 100k 10M FREQUENCY (Hz) 1E+00 1E-01 1E-02 1E-03 1E-04 1E-05 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 BIT ERROR RATE 2.125Gbps CRPAT AT INPUT (DJ = 0.4UI, RJ = 0.2UI) 0 0.2 0.4 0.6 0.8 DATA-CROSSING TIME RELATIVE TO FIRST ZERO CROSSING (UI) 1.0 1E+00 1E-01 1E-02 1E-03 1E-04 1E-05 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 1.0625Gbps CRPAT AT INPUT (DJ = 0.4UI, RJ = 0.2UI) 0 0.2 0.4 0.6 0.8 MAX3772-75 toc08 1.0625Gbps OUTPUT JITTER BATHTUB PLOT 2.125Gbps OUTPUT JITTER BATHTUB PLOT BIT ERROR RATE SINUSOIDAL JITTER (UIp-p) -2 CJTPAT PATTERN, DJ = 0.4UI RJ = 0.2UI TOLERANCE EXCEEDS THE TEST EQUIPMENT'S GENERATION LIMIT MAX3772-75 toc06 -7 -8 -1 100 SINUSOIDAL JITTER (UIp-p) -3 0 MAX3772-75 toc07 JITTER ATTENUATION (dB) -2 MAX3772-75 toc02 0 -1 2.125Gbps JITTER TOLERANCE 1 JITTER ATTENUATION (dB) MAX3772-75 toc01 1 MAX3772 toc03 2.125Gbps JITTER TRANSFER vs. FREQUENCY 1.0 DATA-CROSSING TIME RELATIVE TO FIRST ZERO CROSSING (UI) _______________________________________________________________________________________ 5 MAX3772–MAX3775 Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) Dual-Rate Fibre Channel Repeaters MAX3772–MAX3775 Pin Description PIN NAME FUNCTION 1 CF+ CDR Filter Capacitor Positive Connection. CF = 0.047µF. 2 CF- CDR Filter Capacitor Negative Connection. CF = 0.047µF. 3, 6, 12 GND Electrical Ground 4 IN+ Noninverted Data Input 5 IN- Inverted Data Input 7, 8 VCC Supply Voltage 9 RATESEL 10 OUT- Inverted Data Output 11 OUT+ Noninverted Data Output 13 CLKEN Clock Output Enable. TTL high enables the clock output. TTL low disables the clock output. 14 CLK- Inverted Clock Output. Enabled when CLKEN is forced high; disabled when CLKEN is forced low. 15 CLK+ Noninverted Clock Output. Enabled when CLKEN is forced high; disabled when CLKEN is forced low. 16 LOCK Frequency Lock Indicator. When data is present, a high level indicates the PLL is frequency-locked. The output of the LOCK pin may chatter when large jitter is applied to the input. EP Exposed Paddle The exposed paddle must be soldered to the circuit board ground for proper thermal performance. Rate Select Pin. TTL low selects 1.0625Gbps operation. TTL high selects 2.125Gbps operation. Detailed Description VOUT+ 500mVp-p MIN 900mVp-p MAX VOUT- (VOUT+) - (VOUT-) 1000mVp-p MIN 1800mVp-p MAX Figure 1. Example of Output Signal with Matched Output Loads 6 Figure 2 shows the functional block diagram of the MAX3772–MAX3775 fibre channel repeaters. They consist of a fully integrated PLL, CML input and output buffers, and a data latch. The PLL consists of a combined phase detector (PD) and frequency detector (FD), a loop filter, and a voltage-controlled oscillator (VCO). The input and output signal buffers employ lownoise CML architecture and are terminated on-chip. Phase and Frequency Detector The frequency difference between the VCO clock and the received data is derived by sampling the in-phase and quadrature VCO outputs on the edges of the input data signal. The FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the PD produces a voltage proportional to the phase difference between the incoming data and the internal clock. The PLL drives this error voltage to zero, aligning the recovered clock to the center of the incoming eye. _______________________________________________________________________________________ Dual-Rate Fibre Channel Repeaters MAX3772–MAX3775 0.047µF CF+ CFVCC D Q OUT+ OUT- IN+ PHASE/FREQ DETECTOR LOOP FILTER OPTIONAL 50Ω OR 75Ω 1 VCO IN÷2 OPTIONAL 100Ω OR 150Ω TERMINATION VCC 0 CLK+ RATESEL CLKCLKEN LOCK Figure 2. Block Diagram Loop Filter, VCO, and Latch The phase detector and frequency detector outputs are summed into a loop filter. An external capacitor (between CF+ and CF-) is required to set the PLL damping factor. The fully integrated VCO contains an internal current reference and filter circuitry to minimize the influence of VCC noise. The VCO creates a clock output with frequency proportional to the control voltage applied by the loop filter. Data recovery is accomplished by using the recovered clock signal to latch the incoming data to the CML output buffers, significantly reducing output jitter. See the Applications Information section for the functionality of the RATESEL pin. Applications Information Input and Output Terminations Figures 3 and 4 show models for the MAX3772– MAX3775 inputs and outputs, including packaging parasitics. VCC LOCK Output An active high LOCK output monitor derived from the frequency detector indicates that the PLL is frequencylocked onto the input data. Without input data, the LOCK signal may settle high or low. The use of a lowpass RC filter is recommended to reduce the effects of chatter that could be caused by high input-jitter content. For optimum jitter performance, keep the load ≥ 15kΩ on the output of the LOCK pin. PACKAGE 1kΩ 1.5nH IN+ 0.2pF 0.4pF 1.5nH 0.2pF 0.4pF RATESEL Input The RATESEL input is used to select between input data rates of 2.125Gbps and 1.0625Gbps. This function allows the repeater to sample data at the correct data rate by selecting a divide-by-2 network, giving maximum jitter tolerance at both data rates. The loop bandwidth of the repeater scales with the selected frequency; i.e., the loop-bandwidth at an input rate of 1.0625Gbps is half that at the input rate of 2.125Gbps. ESD STRUCTURES OPTIONAL VCC - 0.450V 50Ω OR 75Ω Figure 3. Input Structure _______________________________________________________________________________________ 7 Dual-Rate Fibre Channel Repeaters MAX3772–MAX3775 Layout Procedure VCC PACKAGE OPTIONAL 50Ω OR 75Ω 1.5nH OUT+ 0.4pF 0.2pF 1.5nH OUT0.4pF 0.2pF ESD STRUCTURES The MAX3772–MAX3775 performance can be greatly affected by circuit-board layout and design. Use good high-frequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the data and clock signals. All IN, OUT, and CLK pins should be connected with 0.1µF coupling capacitors equivalent or better than X5R. A 0.047µF capacitor should be used for the loop filter. If DC coupling is desired pay particular attention to the DC voltage and current requirements at the pins of interest (see DC Electrical Characteristics). The MAX3750/MAX3754/MAX3755 port bypass circuits can be DC-coupled to the Maxim dual-rate repeaters. The exposed paddle of the repeater must be connected to ground and should be soldered onto the circuit board for optimal thermal and electrical operation. Pin Configuration TOP VIEW Figure 4. Output Structure CF+ 1 16 LOCK Control Functions CF- 2 15 CLK+ The MAX3772–MAX3775 have two control inputs: RATESEL and CLKEN. GND 3 14 CLK- IN+ 4 RATESEL is an input that sets the operational data rate for the repeaters. Table 1 shows the selected input data rates when using the RATESEL function. IN- 5 GND 6 CLKEN is an input that can be used to enable or disable the output clock, as shown in Table 2. MAX3772 MAX3773 MAX3774 MAX3775 13 CLKEN 12 GND 11 OUT+ VCC 7 10 OUT- VCC 8 9 RATESEL QSOP-EP* Table 1. Input Data Rate Using RATESEL Function RATESEL LEVEL DATA RATE SELECTED GND 1.0625Gbps VCC 2.125Gbps Table 2. CLKEN Function CLKEN LEVEL CLOCK OUTPUT GND Disabled VCC Enabled *EXPOSED PADDLE MUST BE SOLDERED TO GROUND. Selector Guide DIFFERENTIAL INPUT TERMINATION DIFFERENTIAL OUTPUT TERMINATION MAX3772CEE 100Ω 100Ω MAX3773CEE 150Ω 100Ω MAX3774CEE 100Ω 150Ω MAX3775CEE 150Ω 150Ω PART Chip Information TRANSISTOR COUNT: 1280 PROCESS: Si 8 _______________________________________________________________________________________ Dual-Rate Fibre Channel Repeaters Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3772–MAX3775 Package Information