19-0230; Rev 2a; 1/97 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface The MAX536/MAX537 combine four 12-bit, voltage-output digital-to-analog converters (DACs) and four precision output amplifiers in a space-saving 16-pin package. Offset, gain, and linearity are factory calibrated to provide the MAX536’s ±1LSB total unadjusted error. The MAX537 operates with ±5V supplies, while the MAX536 uses -5V and +12V to +15V supplies. Each DAC has a double-buffered input, organized as an input register followed by a DAC register. A 16-bit serial word is used to load data into each input/DAC register. The serial interface is compatible with either SPI/QSPI™ or Microwire™, and allows the input and DAC registers to be updated independently or simultaneously with a single software command. The DAC registers can be simultaneously updated with a hardware LDAC pin. All logic inputs are TTL/CMOS compatible. ________________________Applications Industrial Process Controls Automatic Test Equipment Digital Offset and Gain Adjustment Motion Control Devices Remote Industrial Controls Microprocessor-Controlled Systems ________________Functional Diagram SDO VDD DGND VSS TP REFAB AGND LDAC ____________________________Features ♦ Four 12-Bit DACs with Output Buffers ♦ Simultaneous or Independent Control of Four DACs via a 3-Wire Serial Interface ♦ Power-On Reset ♦ SPI/QSPI and Microwire Compatible ♦ ±1LSB Total Unadjusted Error (MAX536) ♦ Full 12-Bit Performance without Adjustments ♦ ±5V Supply Operation (MAX537) ♦ Double-Buffered Digital Inputs ♦ Buffered Voltage Output ♦ 16-Pin DIP/SO Packages ______________Ordering Information PART TEMP. RANGE MAX536ACPE 0°C to +70°C MAX536BCPE MAX536ACWE MAX536BCWE MAX536BC/D MAX536AEPE MAX536BEPE MAX536AEWE MAX536BEWE MAX536AMDE MAX536BMDE 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C -55°C to +125°C PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO Dice* 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO 16 Ceramic SB** 16 Ceramic SB** INL (LSB) ±1⁄2 ±1 ±1⁄2 ±1 ±1 ±1⁄2 ±1 ±1⁄2 ±1 ±1⁄2 ±1 Ordering Information continued at end of data sheet. * Contact factory for dice specifications. ** Contact factory for availability and processing to MIL-STD-883. __________________Pin Configuration DECODE CONTROL 16-BIT SHIFT REGISTER MAX536/MAX537 OUTA INPUT REG A DAC REG A DAC A INPUT REG B DAC REG B DAC B INPUT REG C INPUT REG D DAC REG C DAC REG D OUTB SR CONTROL OUTB 1 16 OUTC OUTA 2 15 OUTD OUTC VSS 3 OUTD REFAB 5 12 REFCD DGND 6 11 SDO LDAC 7 10 SCK DAC C DAC D TOP VIEW AGND 4 14 VDD MAX536 MAX537 SDI 8 CS SDI SCK 13 TP 9 CS REFCD DIP/SO SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX536/MAX537 _______________General Description MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface ABSOLUTE MAXIMUM RATINGS VDD to AGND or DGND MAX536 ..................................................................-0.3V, +17V MAX537 ....................................................................-0.3V, +7V VSS to AGND or DGND ...............................................-7V, +0.3V SDI, SCK , CS, LDAC, TP, SDO to AGND or DGND.....................................-0.3V, (VDD + 0.3V) REFAB, REFCD to AGND or DGND .............-0.3V, (VDD + 0.3V) OUT_ to AGND or DGND .............................................VDD, VSS Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 10.53mW/°C above +70°C) .................842mW Wide SO (derate 9.52mW/°C above +70°C).................762mW Ceramic SB (derate 10.53mW/°C above +70°C)..................842mW Operating Temperature Ranges MAX53_AC_E/BC_E.............................................0°C to +70°C MAX53_AE_E/BE_E ..........................................-40°C to +85°C MAX53_AMDE/BMDE .....................................-55°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX536 (VDD = +15V, VSS = -5V, REFAB/REFCD = 10V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE—ANALOG SECTION Resolution N 12 TA = +25°C Total Unadjusted Error (Note 1) TUE TA = TMIN to TMAX Integral Nonlinearity INL Differential Nonlinearity DNL Bits MAX536A ±1.0 MAX536B ±2.0 MAX536AC ±2.0 MAX536BC ±3.0 MAX536AE ±2.5 MAX536BE ±3.5 MAX536AM ±3.0 MAX536BM ±4.0 MAX536A ±0.15 ±1 Guaranteed monotonic ±1 TA = +25°C Offset Error TA = TMIN to TMAX MAX536A ±2.5 MAX536B ±5.0 MAX536AC ±5.0 MAX536BC ±7.5 MAX536AE ±6.1 MAX536BE ±8.5 MAX536AM ±7.5 MAX536BM RL = ∞ Gain Error ±0.50 MAX536B RL = 5kΩ MAX536_C/E LSB LSB LSB mV ±10.0 -0.1 ±1.0 -0.6 ±1.5 MAX536_M LSB ±2.0 VDD Power-Supply Rejection Ratio PSRR TA = +25°C, 10.8V < VDD < 16.5V ±0.02 ±0.125 LSB/V VSS Power-Supply Rejection Ratio PSRR TA = +25°C, -5.5V < VSS < -4.5V ±0.03 ±0.30 LSB/V 2 _______________________________________________________________________________________ Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface (VDD = +15V, VSS = -5V, REFAB/REFCD = 10V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MATCHING PERFORMANCE (TA = +25°C) Total Unadjusted Error TUE MAX536A ±1.0 MAX536B ±2.0 Gain Error Offset Error Integral Nonlinearity LSB ±0.1 ±1.0 MAX536A ±1.2 ±2.5 MAX536B ±1.2 ±5.0 ±0.2 ±1.0 LSB VDD – 4 V INL LSB mV REFERENCE INPUT Reference Input Range Reference Input Resistance REF RREF 0.0 Code dependent, minimum at code 555 hex kΩ 5 MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth VREF = 2Vp-p Reference Feedthrough Total Harmonic Distortion Plus Noise Input code = all 0s THD + N 700 VREF = 10Vp-p at 400Hz -100 VREF = 10Vp-p at 4kHz -82 kHz dB VREF = 2.0Vp-p at 50kHz 0.012 % DIGITAL INPUTS (SDI, SCK, CS, LDAC) Input High Voltage VIH Input Low Voltage VIL Input Leakage Current 2.4 V VIN = 0V or VDD Input Capacitance (Note 2) 0.8 V 1.0 µA 10 pF DIGITAL OUTPUT (SDO) Output Low Voltage VOL Output Leakage Current SDO sinking 5mA 0.18 SDO = 0V to VDD 0.40 V ±10 µA DYNAMIC PERFORMANCE (RL = 5kΩ, CL = 100pF) Voltage-Output Slew Rate To ±1⁄2LSB of full scale Output Settling Time Digital Feedthrough Digital Crosstalk (Note 3) VREF = 5V 5 V/µs 3 µs 5 nV-s 8 nV-s POWER SUPPLIES Positive Supply Range VDD Negative Supply Range VSS Positive Supply Current (Note 4) IDD Negative Supply Current (Note 4) ISS 10.8 -4.5 TA = +25°C 8 TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX 16.5 V -5.5 V 18 25 -6 -16 -23 mA mA _______________________________________________________________________________________ 3 MAX536/MAX537 ELECTRICAL CHARACTERISTICS—MAX536 (continued) MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX536 (continued) (VDD = +15V, VSS = -5V, REFAB/REFCD = 10V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 20 µs TIMING CHARACTERISTICS (Note 5) Internal Power-On Reset Pulse Width (Note 2) tPOR SCK Clock Period tCP 100 ns SCK Pulse Width High tCH 30 ns SCK Pulse Width Low tCL 30 ns CS Fall to SCK Rise Setup Time tCSS 20 ns SCK Rise to CS Rise Hold Time tCSH 10 ns SDI Setup Time tDS 40 SDI Hold Time tDH 0 26 ns ns SCK Rise to SDO Valid Propagation Delay (Note 6) tDO1 1kΩ pull-up on SDO to VDD, CLOAD = 50pF SDO high 78 105 SDO low 50 80 SCK Fall to SDO Valid Propagation Delay (Note 7) tDO2 1kΩ pull-up on SDO to VDD, CLOAD = 50pF SDO high 81 110 SDO low 53 85 ns ns CS Fall to SDO Enable (Note 8) tDV 27 45 ns CS Rise to SDO Disable (Note 9) tTR 40 60 ns SCK Rise to CS Fall Delay tCS0 Continuous SCK, SCK edge ignored 20 ns CS Rise to SCK Rise Hold Time tCS1 SCK edge ignored 20 ns LDAC Pulse Width Low tLDAC 30 ns CS Pulse Width High tCSW 40 ns TUE is specified with no resistive load. Guaranteed by design. Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC. Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly. All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0V to 5V. Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO pin has an internal active pull-up.) Note 7: Serial data clocked out of SDO on SCK’s rising edge. Note 8: SDO changes from High-Z state to 90% of final value. Note 9: SDO rises 10% toward High-Z state. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: 4 _______________________________________________________________________________________ Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface (VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX ±0.15 ±0.50 UNITS STATIC PERFORMANCE—ANALOG SECTION Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL 12 MAX537A Bits MAX537B ±1 Guaranteed monotonic TA = +25°C Offset Error TA = TMIN to TMAX ±1 MAX537A ±3.0 MAX537B ±6.0 MAX537AC ±6.0 MAX537BC ±9.0 MAX537AE ±7.0 MAX537BE ±11.0 MAX537AM ±9.0 MAX537BM Gain Error LSB LSB mV ±15.0 RL = ∞ -0.3 ±1.5 RL = 5kΩ -0.8 ±3.0 LSB VDD Power-Supply Rejection Ratio PSRR TA = +25°C, 4.5V ≤ VDD ≤ 5.5V ±0.01 ±0.5 LSB/V VSS Power-Supply Rejection Ratio PSRR TA = +25°C, -5.5V ≤ VSS ≤ -4.5V ±0.02 ±0.7 LSB/V LSB MATCHING PERFORMANCE (TA = +25°C) Gain Error Offset Error Integral Nonlinearity ±0.1 ±1.25 MAX537A ±0.3 ±3.0 MAX537B ±0.3 ±6.0 ±0.35 ±1.0 INL mV LSB REFERENCE INPUT Reference Input Range Reference Input Resistance REF RREF 0.0 Code dependent, minimum at code 555 hex VDD - 2.2 V kΩ 5 MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth VREF = 2Vp-p Reference Feedthrough Total Harmonic Distortion Plus Noise Input code = all 0s THD + N 700 VREF = 10Vp-p at 400Hz -100 VREF = 10Vp-p at 4kHz -82 VREF = 850mVp-p at 100kHz kHz dB 0.024 % DIGITAL INPUTS (SDI, SCK, CS, LDAC) Input High Voltage VIH Input Low Voltage VIL Input Leakage Current Input Capacitance (Note 2) 2.4 VIN = 0V or VDD V 0.8 V 1.0 µA 10 pF _______________________________________________________________________________________ 5 MAX536/MAX537 ELECTRICAL CHARACTERISTICS—MAX537 MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX537 (continued) (VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUT (SDO) Output High Voltage VOH SDO sourcing 2mA Output Low Voltage VOL SDO sinking 2mA VDD – 0.5 VDD – 0.25 0.13 V 0.40 V DYNAMIC PERFORMANCE (RL = 5kΩ, CL = 100pF) 5 V/µs 5 µs Digital Feedthrough 5 nV-s Digital Crosstalk (Note 3) 5 nV-s Voltage-Output Slew Rate To ±1⁄2LSB of full scale Output Settling Time POWER SUPPLIES Positive Supply Range VDD 4.5 5.5 V Negative Supply Range VSS -4.5 -5.5 V Positive Supply Current (Note 4) IDD Negative Supply Current (Note 4) ISS TA = +25°C 5.5 TA = TMIN to TMAX 12 16 TA = +25°C -4.7 TA = TMIN to TMAX -10 -14 mA mA TIMING CHARACTERISTICS (Note 5) Internal Power-On Reset Pulse Width (Note 2) SCK Clock Period 6 tPOR 50 tCP SCK Pulse Width High tCH SCK Pulse Width Low tCL CS Fall to SCK Rise Setup Time tCSS SCK Rise to CS Rise Hold Time tCSH SDI Setup Time tDS SDI Hold Time tDH 100 MAX537_C/E 35 MAX537_M 40 MAX537_C/E 35 MAX537_M 40 MAX537_C/E 40 MAX537_M 50 ns ns ns ns 0 MAX537_C/E 40 MAX537_M 50 ns 24 ns 0 SCK Rise to SDO Valid Propagation Delay (Note 6) tDO1 CLOAD = 50pF SCK Fall to SDO Valid Propagation Delay (Note 7) tDO2 CLOAD = 50pF MAX537_C/E ns 116 MAX537_M MAX537_C/E µs 200 230 123 MAX537_M _______________________________________________________________________________________ 210 250 ns ns Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface (VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS CS Fall to SDO Enable tDV CLOAD = 50pF CS Rise to SDO Disable (Note 10) tTR CLOAD = 50pF SCK Rise to CS Fall Delay tCS0 Continuous SCK, SCK edge ignored CS Rise to SCK Rise Hold Time tCS1 SCK edge ignored LDAC Pulse Width High tLDAC CS Pulse Width High tCSW MIN MAX537_C/E TYP 75 MAX537_M MAX 140 170 MAX537_C/E 70 MAX537_M 130 165 MAX537_C/E 35 MAX537_M 40 MAX537_C/E 35 MAX537_M 40 MAX537_C/E 50 MAX537_M 70 MAX537_C/E 100 MAX537_M 125 UNITS ns ns ns ns ns ns Guaranteed by design. Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC. Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly. All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0V to 5V. Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO pin has an internal active pull-up.) Note 7: Serial data clocked out of SDO on SCK’s rising edge. Note 10: When disabled, SDO is internally pulled high. Note 2: Note 3: Note 4: Note 5: Note 6: _______________________________________________________________________________________ 7 MAX536/MAX537 ELECTRICAL CHARACTERISTICS—MAX537 (continued) __________________________________________Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) MAX536 VDD = +15V 0.2 VDD = +12V MAX536/7-02 0.200 0.175 -10 -20 RL = 10kΩ, CL = 100pF 0.125 0.100 RL = NO LOAD, CL = 0pF 0.075 -30 0.050 --0.6 -40 0.025 -50 0 4 8 12 REFERENCE VOLTAGE (V) 0 1k 16 MAX536 TOTAL HARMONIC DISTORTION PLUS NOISE vs. REFERENCE FREQUENCY 0.125 RL = 10kΩ, CL = 100pF 0.100 0.075 RL = NO LOAD, CL = 0pF 0.050 10M 10 MAX536 FULL-SCALE ERROR vs. LOAD MAX536 SUPPLY CURRENT vs. TEMPERATURE 10 0 6 -1 -2 -3 10 100 200 2 -2 ISS -10 0.1 1 FREQUENCY (kHz) 10 100 1000 -60 LOAD (kΩ) MAX536 REFERENCE FEEDTHROUGH AT 400Hz -20 20 60 100 TEMPERATURE (°C) MAX536 REFERENCE FEEDTHROUGH AT 4kHz REFAB, 5V/div 0V REFAB, 5V/div OUTA, 100µV/div OUTA, 200µV/div 0V 500µs/div INPUT CODE = ALL 0s IDD VDD = +15V VSS = -5V -6 -5 0 200 FREQUENCY (kHz) -4 0.025 100 FREQUENCY (Hz) SUPPLY CURRENT (mA) 0.150 1M MAX536/7-04 0.175 FULL-SCALE ERROR (LSB) DAC CODE = ALL 1s REFAB = 5Vp-p 100k 1 MAX1536/7-03b 0.200 10k MAX536/7-05 -1.0 8 DAC CODE = ALL 1s REFAB = 10Vp-p 0.150 0 THD + NOISE (%) INL ERROR (LSB) 0.6 REFAB SWEPT 2Vp-p VOUTA MONITORED 10 RELATIVE OUTPUT (dB) VSS = -5V -0.2 20 MAX536/7-01 1.0 MAX536 TOTAL HARMONIC DISTORTION PLUS NOISE vs. REFERENCE FREQUENCY MAX1536/7-03 MAX536 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE MAX536 INTEGRAL NONLINEARITY ERROR vs. REFERENCE VOLTAGE THD + NOISE (%) MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface 50µs/div INPUT CODE = ALL 0s _______________________________________________________________________________________ 140 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536 MAX536 DYNAMIC RESPONSE (ALL BITS ON, OFF, ON) MAX536 NEGATIVE FULL-SCALE SETTLING TIME (ALL BITS ON TO ALL BITS OFF) CS, 5V/div CS, 5V/div OUTA, 5V/div OUTA, 2V/div 5µs/div OUTA, 5mV/div 1µs/div VDD = +15V, VSS = -5V, REFAB = 5V, CL = 100pF, RL = 10kΩ VDD = +15V, VSS = -5V, REFAB = 10V, CL = 100pF, RL = 10kΩ MAX536 POSITIVE FULL-SCALE SETTLING TIME (ALL BITS OFF TO ALL BITS ON) MAX536 DIGITAL FEEDTHROUGH CS, 5V/div SCK, 5V/div OUTA, 5V/div OUTA, -10V OFFSET 5mV/div OUTA, AC-COUPLED, 10mV/div 1µs/div VDD = +15V, VSS = -5V, REFAB = 10V, CL = 100pF, RL = 10kΩ VDD = +15V, VSS = -5V, REFAB = 10V, CS = HIGH, DIN TOGGLING AT 1⁄2 THE CLOCK RATE, OUTA = 5V _______________________________________________________________________________________ 9 MAX536/MAX537 ____________________________Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) ____________________________Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MAX537 MAX537 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE 0.5 0 -0.5 -1.0 REFAB = 2.5Vp-p 0.175 0.150 0 THD + NOISE (%) RELATIVE OUTPUT (dB) -10 -20 0.125 RL = 10kΩ, CL = 100pF 0.100 0.075 RL = NO LOAD, CL = 0pF -30 0.050 -40 -1.5 0.025 -50 -2.0 0 1 2 3 4 1k 5 10k 100k 1M 0 10M 10 100 200 VREF (V) FREQUENCY (Hz) FREQUENCY (kHz) MAX537 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX537 FULL-SCALE ERROR vs. LOAD MAX537 SUPPLY CURRENT vs. TEMPERATURE 0.125 0.100 RL = 10kΩ, CL = 100pF 0.075 0.050 3 SUPPLY CURRENT (mA) 0.150 5 MAX536/7-11 1 FULL-SCALE ERROR (LSB) REFAB = 1Vp-p 0.175 2 MAX1536/7-09 0.200 MAX536/7-10 INL ERROR (LSB) 1.0 REFAB SWEPT 2Vp-p VOUTA MONITORED 10 0.200 MAX536/7-07 VDD = +5V VSS = -5V 1.5 20 MAX536/7-06 2.0 MAX537 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX1536/7-14 MAX537 INTEGRAL NONLINEARITY ERROR vs. REFERENCE VOLTAGE THD + NOISE (%) MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface 0 -1 -2 IDD VDD = +5V VSS = -5V 1 -1 ISS -3 -3 0.025 RL = NO LOAD, CL = 0pF -4 0 10 100 200 -5 0.1 10 1 100 1000 -60 LOAD (kΩ) FREQUENCY (kHz) -20 20 REFAB, 1V/div REFAB, 1V/div 0V 0V OUTA, AC-COUPLED, 100µV/div OUTA, AC-COUPLED, 100µV/div 50µs/div 500µs/div 10 100 MAX537 REFERENCE FEEDTHROUGH AT 4kHz MAX537 REFERENCE FEEDTHROUGH AT 400Hz INPUT CODE = ALL 0s 60 TEMPERATURE (°C) INPUT CODE = ALL 0s ______________________________________________________________________________________ 140 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX537 MAX537 NEGATIVE FULL-SCALE SETTLING TIME (ALL BITS ON TO ALL BITS OFF) MAX537 DYNAMIC RESPONSE (ALL BITS ON, OFF, ON) CS, 5V/div CS, 5V/div OUTA, 5mV/div OUTA, 1V/div 5µs/div 1µs/div VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ MAX537 POSITIVE FULL-SCALE SETTLING TIME (ALL BITS OFF TO ALL BITS ON) MAX537 DIGITAL FEEDTHROUGH 1µs/div VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ CS, 5V/div SCK, 5V/div OUTA, 5mV/div OUTA, AC-COUPLED, 20mV/div 100ns/div VDD = +5V, VSS = -5V, REFAB = 2.5V, CS = HIGH, DIN TOGGLING AT 1⁄2 THE CLOCK RATE, OUTA = 1.25V ______________________________________________________________________________________ 11 MAX536/MAX537 ____________________________Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface ______________________________________________________________Pin Description PIN NAME 1 OUTB DAC B Output Voltage FUNCTION 2 OUTA DAC A Output Voltage 3 VSS Negative Power Supply 4 AGND Analog Ground 5 REFAB Reference Voltage Input for DAC A and DAC B 6 DGND Digital Ground 7 LDAC Load DAC Input (active low). Driving this asynchronous input low transfers the contents of all input registers to their respective DAC registers. 8 SDI Serial Data Input. Data is shifted into an internal 16-bit shift register on SCK's rising edge. 9 CS Chip-Select Input (active low). A low level on CS enables the input shift register and SDO. On CS’s rising edge, data is latched into the appropriate register(s). 10 SCK Shift Register Clock Input 11 SDO Serial Data Output. SDO is the output of the internal shift register. SDO is enabled when CS is low. For the MAX536, SDO is an open-drain output. For the MAX537, SDO has an active pull-up to VDD. 12 REFCD Reference Voltage Input for DAC C and DAC D 13 TP Test Pin. Connect to VDD for proper operation. 14 VDD Positive Power Supply 15 OUTD DAC D Output Voltage 16 OUTC DAC C Output Voltage _______________Detailed Description The MAX536/MAX537 contain four 12-bit voltage-output DACs that are easily addressed using a simple 3-wire serial interface. They include a 16-bit data-in/data-out shift register, and each DAC has a double-buffered input composed of an input register and a DAC register (see the Functional Diagram on the front page). The DACs are “inverted” R-2R ladder networks that convert 12-bit digital inputs into equivalent analog output voltages in proportion to the applied reference-voltage inputs. DAC A and DAC B share the REFAB reference input, while DAC C and DAC D share the REFCD reference input. The two reference inputs allow different full-scale output voltage ranges for each pair of DACs. Figure 1 shows a simplified circuit diagram of one of the four DACs. Reference Inputs The two reference inputs accept positive DC and AC signals. The voltage at each reference input sets the full-scale output voltage for its two corresponding DACs. The REFAB/REFCD voltage range is 0V to (VDD - 4V) for the MAX536 and 0V to (VDD - 2.2V) for the MAX537. The output voltages VOUT_ are represented by 12 R 2R 2R D0 R R 2R 2R D9 D10 VOUT 2R D11 REF AGND SHOWN FOR ALL 1s ON DAC Figure 1. Simplified DAC Circuit Diagram a digitally programmable voltage source as: VOUT_ = NB (VREF) / 4096 where NB is the numeric value of the DAC’s binary input code (0 to 4095) and VREF is the reference voltage. ______________________________________________________________________________________ Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface The REFAB and REFCD reference inputs have a 5kΩ guaranteed minimum input impedance. When the two reference inputs are driven from the same source, the effective minimum impedance becomes 2.5kΩ. A voltage reference with a load regulation of 0.001%/mA, such as the MAX674, would typically deviate by 0.164LSB (0.328LSB worst case) when simultaneously driving both MAX536 reference inputs at 10V. An op amp, such as the MAX400 or OP07, can be used to buffer the reference to increase reference accuracy. The op amp’s closed-loop output impedance should be kept below 0.05Ω to ensure an error of less than 0.08LSB. Reference accuracy is also improved by driving the REFAB and REFCD pins separately, or by using a reference with excellent accuracy and superior load regulation, such as the MAX676/MAX677/MAX678. The reference input capacitance is also code dependent and typically ranges from 125pF to 300pF. Output Buffer Amplifiers All MAX536/MAX537 voltage outputs are internally buffered by precision unity-gain followers with a typical slew rate of 5V/µs for the MAX536 and 3V/µs for the MAX537. With a full-scale transition at the MAX536 output (0V to 10V or 10V to 0V), the typical settling time to ±1/2LSB is 3µs when loaded with 5kΩ in parallel with 100pF (loads less than 5kΩ degrade performance). With a full-scale transition at the MAX537 output (0V to 2.5V or 2.5V to 0V), the typical settling time to ±1/2LSB is 5µs when loaded with 5kΩ in parallel with 100pF (loads less than 5kΩ degrade performance). Output dynamic responses and settling performances of the MAX536/MAX537 output amplifier are shown in the Typical Operating Characteristics. Serial-Interface Configurations The MAX536/MAX537’s 3-wire or 4-wire serial interface is compatible with both Microwire (Figure 2) and SPI/QSPI (Figure 3). In Figures 2 and 3, LDAC can be tied either high or low for a 3-wire interface, or used as the fourth input with a 4-wire interface. The connection between SDO and the serial-interface port is not necessary, but may be used for data echo. (Data held in the shift register 5V 5V †RP †RP 1k 1k SDO* MAX536 MAX537 SCK SK SDI SO SDO* SI* CS I/O LDAC** I/O MICROWIRE PORT MAX536 MAX537 MISO* SDI MOSI SCK SCK CS I/O LDAC** I/O SS SPI/QSPI PORT CPOL = 0, CPHA = 0 *THE SDO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536, BUT MAY BE USED FOR READBACK PURPOSES. **THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE. †THE MAX537 HAS AN INTERNAL ACTIVE PULL-UP TO VDD, SO RP IS NOT NECESSARY. Figure 2. Connections for Microwire *THE SDO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536, BUT MAY BE USED FOR READBACK PURPOSES. **THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE. †THE MAX537 HAS AN INTERNAL ACTIVE PULL-UP TO VDD, SO RP IS NOT NECESSARY. Figure 3. Connections for SPI/QSPI _______________________________________________________________________________________ 13 MAX536/MAX537 The input impedance at each reference input is code dependent, ranging from a low value of typically 6kΩ (with an input code of 0101 0101 0101) to a high value of 60kΩ (with an input code of 0000 0000 0000). Since the input impedance at the reference pins is code dependent, load regulation of the reference source is important. MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface , , ,, , ,,, CS COMMAND EXECUTED SCK 1 8 9 16 SDI ..........D2 D1 D0 D15 D14 D13.......... MSB LSB SDO ...........Q0 Q15.......... MSB FROM PREVIOUS WRITE LSB FROM PREVIOUS WRITE Figure 4. 3-Wire Serial-Interface Timing Diagram (LDAC = GND or VDD) CS INPUT REGISTER(S) UPDATED SCK 1 8 9 16 SDI .......... D2 D1 D0 D15 D14 D13 .......... MSB LSB SDO Q15.......... .......... Q0 MSB FROM PREVIOUS WRITE LSB FROM PREVIOUS WRITE LDAC DACs UPDATED Figure 5. 4-Wire Serial-Interface Timing Diagram for Asynchronous DAC Updating Using LDAC tCSW CS tCSS tCSO tCL tCP tCH tCSH tCSI SCK tDS tDH SDI tDV SDO tDO1 tDO2 tTR LDAC* *USE OF LDAC IS OPTIONAL tLDAC Figure 6. Detailed Serial-Interface Timing Diagram 14 ______________________________________________________________________________________ Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface clocked into the internal shift register via the serial data input pin (SDI) on SCK’s rising edge. The maximum guaranteed clock frequency is 10MHz. Data is latched into the appropriate MAX536/MAX537 input/DAC registers on CS’s rising edge. Interface timing is optimized when serial data is clocked out of the microcontroller/microprocessor on one clock edge and clocked into the MAX536/MAX537 on the other edge. Table 1 lists the serial-interface programming commands. For certain commands, the 12 data bits are “don’t cares”. The programming command Load-All-DACs-From-ShiftRegister allows all input and DAC registers to be simultaneously loaded with the same digital code from the input shift register. The NOP (no operation) command allows the register contents to be unaffected and is useful when the MAX536/MAX537 are configured in a daisy-chain (see the Daisy-Chaining Devices section). The command to change the clock edge on which serial data is shifted out of the MAX536/MAX537 SDO pin also loads data from all input registers to their respective DAC registers. Serial-Interface Description Serial-Data Output The MAX536/MAX537 require 16 bits of serial data. Data is sent MSB first and can be sent in two 8-bit packets or one 16-bit word (CS must remain low until 16 bits are transferred). The serial data is composed of two DAC address bits (A1, A0), two control bits (C1, C0), and the 12 data bits D11…D0 (Figure 7). The 4-bit address/control code determines the following: 1) the register(s) to be updated and/or the status of the input and DAC registers (i.e., whether they are in transparent or latch mode), and 2) the edge on which data is clocked out of SDO. The serial-data output, SDO, is the internal shift register’s output. The MAX536/MAX537 can be programmed so that data is clocked out of SDO on SCK’s rising (Mode 1) or falling (Mode 0) edge . In Mode 0, output data at SDO lags input data at SDI by 16.5 clock cycles, maintaining compatibility with Microwire, SPI/QSPI, and other serial interfaces. In Mode 1, output data lags input data by 16 clock cycles. On power-up, SDO defaults to Mode 1 timing. MSB ..................................................................................LSB 16 Bits of Serial Data Address Bits A1 A0 Control Bits C1 4 Address/ Control Bits C0 Data Bits MSB.............................................LSB D11................................................D0 12 Data Bits Figure 7. Serial-Data Format (MSB Sent First) Figure 6 shows the serial-interface timing requirements. The chip-select pin (CS) must be low to enable the DAC’s serial interface. When CS is high, the interface control circuitry is disabled and the serial data output pin (SDO) is driven high (MAX537) or is a high-impedance open drain (MAX536). CS must go low at least tCSS before the rising serial clock (SCK) edge to properly clock in the first bit. When CS is low, data is For the MAX536, SDO is an open-drain output that should be pulled up to +5V. The data sheet timing specifications for SDO use a 1kΩ pull-up resistor. For the MAX537, SDO is a complementary output and does not require an external pull-up. Test Pin The test pin (TP) is used for pre-production analysis of the IC. Connect TP to VDD for proper MAX536/MAX537 operation. Failure to do so affects DAC operation. Daisy-Chaining Devices Any number of MAX536/MAX537s can be daisy-chained by connecting the SDO pin of one device (with a pull-up resistor, if appropriate) to the SDI pin of the following device in the chain (Figure 8). Since the MAX537’s SDO pin has an internal active pull-up, the SDO sink/source capability determines the time required to discharge/charge a capacitive load. Refer to the serial data out V OH and V OL specifications in the Electrical Characteristics. ______________________________________________________________________________________ 15 MAX536/MAX537 of the MAX536/MAX537 can be shifted out of SDO and returned to the microprocessor for data verification; data in the MAX536/MAX537 input/DAC registers cannot be read.) With a 3-wire interface (CS, SCK, SDI) and LDAC tied high, the DACs are double-buffered. In this mode, depending on the command issued through the serial interface, the input register(s) may be loaded without affecting the DAC register(s), the DAC register(s) can be loaded directly, or all four DAC registers may be simultaneously updated from the input registers. With a 3wire interface (CS, SCK, SDI) and LDAC tied low (Figure 4), the DAC registers remain transparent. Any time an input register is updated, the change appears at the DAC output with the rising edge of CS. The 4-wire interface (CS, SCK, SDI, LDAC) is similar to the 3-wire interface with LDAC tied high, except LDAC is a hardware input that simultaneously and asynchronously loads all DAC registers from their respective input registers when driven low (Figure 5). MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface Table 1. Serial-Interface Programming Commands 16-BIT SERIAL WORD D11…D0 LDAC FUNCTION A1 A0 C1 C0 0 0 0 1 12-bit DAC data 1 Load DAC A input register; DAC output unchanged. 0 1 0 1 12-bit DAC data 1 Load DAC B input register; DAC output unchanged. 1 0 0 1 12-bit DAC data 1 Load DAC C input register; DAC output unchanged. 1 1 0 1 12-bit DAC data 1 Load DAC D input register; DAC output unchanged. 0 0 1 1 12-bit DAC data 1 Load input register A; all DAC registers updated. 0 1 1 1 12-bit DAC data 1 Load input register B; all DAC registers updated. 1 0 1 1 12-bit DAC data 1 Load input register C; all DAC registers updated. 1 1 1 1 12-bit DAC data 1 Load input register D; all DAC registers updated. X 0 0 0 12-bit DAC data X Load all DACs from shift register. X 1 0 0 XXXXXXXXXXXX X No operation (NOP) 0 X 1 0 XXXXXXXXXXXX 1 Update all DACs from their respective input registers. 1 1 1 0 XXXXXXXXXXXX X Mode 1 (default condition at power-up), DOUT clocked out on SCK’s rising edge. All DACs updated from their respective input registers. 1 0 1 0 XXXXXXXXXXXX X Mode 0, DOUT clocked out on SCK’s falling edge. All DACs updated from their respective input registers. 0 0 X 1 12-bit DAC data 0 Load DAC A input register; DAC A is immediately updated. 0 1 X 1 12-bit DAC data 0 Load DAC B input register; DAC B is immediately updated. 1 0 X 1 12-bit DAC data 0 Load DAC C input register; DAC C is immediately updated. 1 1 X 1 12-bit DAC data 0 Load DAC D input register; DAC D is immediately updated. “X” = Don’t Care. LDAC provides true latch control: when LDAC is low, the DAC registers are transparent; when LDAC is high, the DAC registers are latched. When daisy-chaining MAX536s, the delay from CS low to SCK high (tCSS) must be the greater of: tDV + tDS or tTR + tRC + tDS - tCSW where tRC is the time constant of the external pull-up resistor (Rp) and the load capacitance (C) at SDO. For tRC < 20ns, tCSS is simply tDV + tDS. Calculate tRC from the following equation: VPULL-UP tRC = Rp (C) ln VPULL-UP - 2.4V [( )] where VPULL-UP is the voltage to which the pull-up resistor is connected. 16 Additionally, when daisy-chaining devices, the maximum clock frequency is limited to: 1 fSCK(max) = —————————————— 2 (tDO + tRC - 38ns + tDS) For example, with t RC = 23ns (5V ±10% supply with Rp = 1kΩ and C = 30pF), the maximum clock frequency is 8.7MHz. Figure 9 shows an alternate method of connecting several MAX536/MAX537s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC. ______________________________________________________________________________________ Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface +5V RP* 1k +5V RP* 1k RP* 1k MAX536 MAX536 MAX536 SCK SCK MAX537 SCK MAX537 SCK MAX537 DIN SDI CS CS SDO SDO SDI CS MAX536/MAX537 +5V SDI SDO CS TO OTHER SERIAL DEVICES * THE MAX537 HAS AN ACTIVE INTERNAL PULL-UP, SO RP IS NOT NECESSARY. Figure 8. Daisy-Chaining MAX536/MAX537s with a 3-Wire Serial Interface DIN SCK LDAC CS1 TO OTHER SERIAL DEVICES CS2 CS3 CS CS CS LDAC LDAC LDAC MAX536 MAX536 MAX536 SCK MAX537 SCK MAX537 SCK MAX537 SDI SDI SDI Figure 9. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3… are driven separately, thus controlling which data are written to devices 1, 2, 3… ______________________________________________________________________________________ 17 MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface __________Applications Information Interfacing to the M68HC11* PORT D of the 68HC11 supports SPI. The four registers used for SPI operation are the Serial Peripheral Control Register, the Serial Peripheral Status Register, the Serial Peripheral Data I/O Register, and PORT D’s Data Direction Register. These registers have a default starting location of $1000. On reset, the PORT D register (memory location $1008) is cleared and bits 5-0 are configured as general-purpose inputs. Setting bit 6 (SPE) of the Serial Peripheral Control Register (SPCR) configures PORT D for SPI as follows: BIT 7 6 NAME – – 5 4 SS 3 2 SCK MOSI MISO 1 0 TXD RXD Bits 6 and 7 are not used. Writes to these bits are ignored. The PORT D Data Direction Register (DDRD) determines whether the port bits are inputs or outputs. Its configuration is shown below: BIT 7 6 NAME – – 5 4 3 2 1 0 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 Setting DDD_ = 0 configures the port bit as an input, while setting DDD_ = 1 configures the port bit as an output. Writes to bits 6 and 7 have no effect. In SPI mode with MSTR = 1, when a PORT D bit is expected to be an input (SS, MISO, RXD), the corresponding DDRD bit (DDD_) is ignored. If the bit is expected to be an output (SCK, MOSI, TXD), the corresponding DDRD bit must be set for the bit to be an output. Table 2. Serial Peripheral Control-Register Definitions NAME DEFINITION SPIE Serial Peripheral Interrupt Enable. Clearing SPIE disables the SPI hardware-interrupt request; the SPSR is polled to determine when an SPI data transfer is complete. Setting SPIE requests a hardware interrupt when the Serial Peripheral Status Register’s SPIF bit or MODF bit is set. SPE Setting SPE (Serial Peripheral System Enable) configures PORT D for SPI. Clearing SPE configures the port as a generalpurpose I/O port. DWOM When DWOM is set, the six PORT D outputs are open drain. When DWOM is cleared, the outputs are complementary. MSTR Master/Slave select option CPOL Determines clock polarity. When set, the serial clock idles high while data is not being transferred; when cleared, the clock idles low. CPHA Determines the clock phase. SPI Clock-Rate Select SPR1/0 SPR1 SPR0 0 0 µP clock divided by 2 0 1 µP clock divided by 4 1 0 µP clock divided by 16 1 1 µP clock divided by 32 Table 3. Serial Peripheral Status-Register Definitions NAME SPIF DEFINITION SPIF is set when an SPI data transfer is complete. It is cleared by reading the SPSR and then accessing the SPDR. WCOL The Write Collision flag is set when a write to the SPDR occurs while a data transfer is in progress. It is cleared by reading the SPSR and then accessing the SPDR. MODF The Mode Fault flag detects master/slave conflicts in a multimaster environment. It is set when the “master” controller has its SS line (PORT D) pulled low, and cleared by reading the SPSR followed by a write to the SPCR. *M68HC11 is a Motorola microcontroller. General information about the device was obtained from M68HC11 technical manuals. 18 ______________________________________________________________________________________ Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537 Table 4. M68HC11 Programming Code ______________________________________________________________________________________ 19 MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface SS is an input intended for use in a multimaster environment. However, SS or unused PORT D bit RXD, TXD, or possibly MISO (if DAC readback is not used) should be configured as a general-purpose output and used as CS by setting the appropriate Data Direction Register bit. The SPCR configuration (memory location $1028) is shown below: BIT 7 6 5 4 3 2 1 0 NAME SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0 SETTING AFTER RESET 0 0 0 0 0 U* 1 U* SETTING FOR TYPICAL SPI COMMUNICATION 1** 0 1 0 1 0 0 0** Unipolar Output For a unipolar output, the output voltages and the reference inputs are the same polarity. Figure 10 shows the MAX536/MAX537 unipolar output circuit, which is also the typical operating circuit. Table 5 lists the unipolar output codes. Bipolar Output The MAX536/MAX537 outputs can be configured for bipolar operation using Figure 11’s circuit. One op amp and two resistors are required per DAC. With R1 = R2: VOUT = VREF [(2NB / 4096) - 1] where N B is the numeric value of the DAC’s binary input code. Table 6 shows digital codes and corresponding output voltages for Figure 11’s circuit. Table 5. Unipolar Code Table DAC CONTENTS MSB LSB *U = Unknown **Depends on µP clock frequency. ANALOG OUTPUT Always configure the 68HC11 as the “master” controller and the MAX536/MAX537 as the “slave” device. 1111 1111 1111 4095 +VREF ( ——— ) 4096 When MSTR = 1 in the SPCR, a write to the Serial Peripheral Data I/O Register (SPDR), located at memory location $102A, initiates the transmission/reception of data. The data transfer is monitored and the appropriate flags are set in the Serial Peripheral Status Register (SPSR). 1000 0000 0001 2049 +VREF ( ——— ) 4096 1000 0000 0000 2048 +VREF +VREF ( ——— ) = ———— 4096 2 0111 1111 1111 2047 +VREF ( ——— ) 4096 0000 0000 0001 1 +VREF ( ——— ) 4096 0000 0000 0000 0V The SPSR configuration is shown below: BIT 7 6 NAME SPIF WCOL 5 4 3 2 1 0 – MODF – – – – 0 0 0 0 RESET CONDITIONS 0 0 0 0 Table 6. Bipolar Code Table DAC CONTENTS MSB LSB ANALOG OUTPUT An example of 68HC11 programming code for a two-byte SPI transfer to the MAX536/MAX537 is given in Table 4. SS is used for CS, the high byte of MAX536/ MAX537 digital data is stored in memory location $0100, and the low byte is stored in memory location $0101. 1111 1111 1111 1000 0000 0001 Interfacing to Other Controllers 1000 0000 0000 0111 1111 1111 1 ) -VREF ( ——— 2048 0000 0000 0001 2047 -VREF ( ——— ) 2048 0000 0000 0000 2048 -VREF ( ——— ) = -VREF 2048 When using Microwire, refer to the section on Interfacing to the M68HC11 for guidance, since Microwire can be considered similar to SPI when CPOL = 0 and CPHA = 0. When interfacing to Intel’s 80C51/80C31 microcontroller family, use bit-pushing to configure a desired port as the MAX536/MAX537 interface port. Bitpushing involves arbitrarily assigning I/O port bits as interface control lines, and then writing to the port each time a signal transition is required. NOTE: 1LSB = (VREF) ( 20 2047 +VREF ( ——— ) 2048 1 +VREF ( ——— ) 2048 0V 1 ) 4096 ______________________________________________________________________________________ Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface 5 REFAB 12 REFCD MAX536 MAX537 13 TP 14 VDD R1 2 DAC A R2 VREF OUTA +15V (+5V) 1 DAC B OUTB VOUT 16 DAC C DAC OUTPUT OUTC –5V 15 DAC D VSS 3 -5V AGND 4 R1 = R2 = 10kΩ 0.1% OUTD DGND 6 NOTES: ( ) ARE FOR MAX537. VREF IS THE SELECTED REFERENCE INPUT FOR THE MAX536/MAX537. NOTE: ( ) ARE FOR MAX537. Figure 10. Unipolar Output Circuit Figure 11. Bipolar Output Circuit +15V (+5V) AC REFERENCE INPUT +15V (+5V) 15k 5 REFAB +4V (+750mV) 5 -4V (-750mV) 10k 13 TP REFAB 14 VDD 13 TP 14 VDD + VIN 2 DAC A - OUTA 1 DAC B OUTB 4 MAX536/MAX537 VSS 3 -5V NOTES: ( ) ARE FOR MAX537. DIGITAL INPUTS NOT SHOWN. Figure 12. AC Reference Input Circuit AGND 4 DGND 6 + VBIAS - AGND MAX536/MAX537 VSS 3 DGND 6 -5V NOTES: ( ) ARE FOR MAX537. DIGITAL INPUTS NOT SHOWN. Figure 13. AGND Bias Circuit ______________________________________________________________________________________ 21 MAX536/MAX537 +15V (+5V) REFERENCE INPUTS MAX536 MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537 Offsetting AGND AGND can be biased from DGND to the reference voltage to provide an arbitrary nonzero output voltage for a zero input code (Figure 13). The output voltage VOUTA is: 3 VOUTA = VBIAS + NB (VIN) VSS MAX536 MAX537 1N5817 4 AGND where VBIAS is the positive offset voltage (with respect to DGND) applied to AGND, and N B is the numeric value of the DAC’s binary input code. Since AGND is common to all four DACs, all outputs will be offset by VBIAS in the same manner. As the voltage at AGND increases, the DAC’s resolution decreases because its full-scale voltage swing is effectively reduced. AGND should not be biased more negative than DGND. Power-Supply Considerations Figure 14. When VSS and VDD cannot be sequenced, tie a Schottky diode between VSS and AGND. Using an AC Reference In applications where the reference has AC signal components, the MAX536/MAX537 have multiplying capability within the reference input range specifications. Figure 12 shows a technique for applying a sine-wave signal to the reference input where the AC signal is offset before being applied to REFAB/REFCD. The reference voltage must never be more negative than DGND. The MAX536’s total harmonic distortion plus noise (THD + N) is typically less than 0.012%, given a 5Vp-p signal swing and input frequencies up to 35kHz, or given a 2Vp-p swing and input frequencies up to 50kHz. The typical -3dB frequency is 700kHz as shown in the Typical Operating Characteristics graphs. For the MAX537, with an input signal amplitude of 0.85mVp-p, THD + N is typically less than 0.024% with a 5kΩ load in parallel with 100pF and input frequencies up to 100kHz, or with a 2kΩ load in parallel with 100pF and input frequencies up to 95kHz. 22 On power-up, VSS should come up first, VDD next, then REFAB or REFCD. If supply sequencing is not possible, tie an external Schottky diode between VSS and AGND as shown in Figure 14. On power-up, all input and DAC registers are cleared (set to zero code) and SDO is in Mode 0 (serial data is shifted out of SDO on the clock’s rising edge). For rated MAX536 performance, VDD should be 4V higher than REFAB/REFCD and should be between 10.8V and 16.5V. When using the MAX537, VDD should be at least 2.2V higher than REFAB/REFCD and should be between 4.75V and 5.5V. Bypass both VDD and VSS with a 4.7µF capacitor in parallel with a 0.1µF capacitor to AGND. Use short lead lengths and place the bypass capacitors as close to the supply pins as possible. Grounding and Layout Considerations Digital or AC transient signals between AGND and DGND can create noise at the analog outputs. Tie AGND and DGND together at the DAC, then tie this point to the highest quality ground available. Good printed circuit board ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines. Wire-wrapped boards are not recommended. ______________________________________________________________________________________ Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface PIN-PACKAGE ___________________Chip Topography INL (LSB) PART TEMP. RANGE MAX537ACPE 0°C to +70°C 16 Plastic DIP ±1⁄2 MAX537BCPE MAX537ACWE MAX537BCWE MAX537BC/D MAX537AEPE MAX537BEPE MAX537AEWE MAX537BEWE 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C 16 Plastic DIP 16 Wide SO 16 Wide SO Dice* 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO ±1 ±1⁄2 ±1 ±1 ±1⁄2 ±1 ±1⁄2 ±1 MAX537AMDE -55°C to +125°C 16 Ceramic SB** ±1⁄2 MAX537BMDE -55°C to +125°C 16 Ceramic SB** ±1 OUTA OUTB OUTC OUTD V DD V SS TP AGND REFAB REFCD * Contact factory for dice specifications. ** Contact factory for availability and processing to MIL-STD-883. 0.309" (7.848mm) DGND SDO LDAC SCK SDI CS 0.139" (3.5306mm) TRANSISTOR COUNT: 5034 SUBSTRATE CONNECTED TO VDD ______________________________________________________________________________________ 23 MAX536/MAX537 _Ordering Information (continued) PDIPN.EPS ________________________________________________________Package Information SOICW.EPS MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.