19-3558; Rev 2; 10/05 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer Features The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial data rate. The data enable input determines when the video or control data is serialized. The MAX9217 pairs with the MAX9218 deserializer to form a complete digital video serial link. Interconnect can be controlled-impedance PC board traces or twistedpair cable. Proprietary data encoding reduces EMI and provides DC balance. DC balance allows AC-coupling, providing isolation between the transmitting and receiving ends of the interface. The LVDS output is internally terminated with 100Ω. ESD tolerance is specified for ISO 10605 with ±10kV contact discharge and ±30kV air discharge. ♦ Proprietary Data Encoding for DC Balance and Reduced EMI The MAX9217 operates from a +3.3V core supply and features a separate input supply for interfacing to 1.8V to 3.3V logic levels. This device is available in 48-lead Thin QFN and TQFP packages and is specified from -40°C to +85°C. ♦ Space-Saving Thin QFN and TQFP Packages Applications Navigation System Display In-Vehicle Entertainment System Video Camera ♦ Control Data Sent During Video Blanking ♦ Five Control Data Inputs Are Single-Bit-Error Tolerant ♦ Programmable Phase-Shifted LVDS Signaling Reduces EMI ♦ Output Common-Mode Filter Reduces EMI ♦ Greater than 10m STP Cable Drive ♦ Wide ±2% Reference Clock Tolerance ♦ ISO 10605 ESD Protection ♦ Separate Input Supply Allows Interface to 1.8V to 3.3V Logic ♦ +3.3V Core Supply ♦ -40°C to +85°C Operating Temperature Ordering Information PART MAX9217ECM -40°C to +85°C 48 TQFP -40°C to +85°C 48 Thin QFN-EP* C48-5 T4866-1 *EP = Exposed pad. 36 2 35 RGB_IN10 3 34 RGB_IN11 RGB_IN12 RGB_IN13 4 33 5 32 6 31 RGB_IN14 RGB_IN15 RGB_IN16 7 RNG0 RNG1 VCCLVDS OUT+ OUTLVDS GND 8 29 9 28 LVDS GND CMF PWRDWN RGB_IN17 10 27 VCCPLL CNTL_IN0 CNTL_IN1 11 26 12 25 PLL GND MOD1 37 38 39 40 41 42 43 44 45 1 36 RNG0 2 35 3 34 RGB_IN11 RGB_IN12 RGB_IN13 4 33 RNG1 VCCLVDS OUT+ 5 32 6 31 RGB_IN14 RGB_IN15 RGB_IN16 7 30 OUTLVDS GND LVDS GND 8 29 CMF 9 28 RGB_IN17 10 27 CNTL_IN0 CNTL_IN1 11 26 PWRDWN VCCPLL PLL GND 12 25 MOD1 MAX9217 24 23 22 21 20 19 18 17 16 15 14 13 GND VCC CNTL_IN2 CNTL_IN3 CNTL_IN4 CNTL_IN5 CNTL_IN6 CNTL_IN7 CNTL_IN8 DE_IN PCLK_IN MOD0 TQFP GND VCCIN RGB_IN10 24 23 22 21 20 19 18 17 16 15 30 GND VCC CNTL_IN2 CNTL_IN3 CNTL_IN4 CNTL_IN5 CNTL_IN6 CNTL_IN7 CNTL_IN8 DE_IN PCLK_IN MOD0 14 MAX9217 46 RGB_IN9 RGB_IN8 RGB_IN7 RGB_IN6 RGB_IN5 RGB_IN4 RGB_IN3 RGB_IN2 RGB_IN1 RGB_IN0 VCC GND 48 1 47 GND 37 38 39 40 41 42 43 44 45 46 RGB_IN9 RGB_IN8 RGB_IN7 RGB_IN6 RGB_IN5 RGB_IN4 RGB_IN3 RGB_IN2 RGB_IN1 RGB_IN0 VCC 47 48 Pin Configurations GND VCCIN 13 PKG CODE MAX9217ETM LCD Displays TOP VIEW PINPACKAGE TEMP RANGE THIN QFN-EP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9217 General Description MAX9217 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer ABSOLUTE MAXIMUM RATINGS VCC_ to _GND........................................................-0.5V to +4.0V Any Ground to Any Ground...................................-0.5V to +0.5V OUT+, OUT- to LVDS GND ...................................-0.5V to +4.0V OUT+, OUT- Short Circuit to LVDS GND or VCCLVDS .............................................................Continuous OUT+, OUT- Short Through 0.125µF (or smaller), 25V Series Capacitor..........................................-0.5V to +16V RGB_IN[17:0], CNTL_IN[8:0], DE_IN, RNG0, RNG1, MOD0, MOD1, PCLK_IN, PWRDWN, CMF to GND......................-0.5V to (VCCIN + 0.5V) Continuous Power Dissipation (TA = +70°C) 48-Lead TQFP (derate 20.8mW/°C above +70°C) ....1667mW 48-Lead Thin QFN (derate 37mW/°C above +70°C) .2963mW ESD Protection Human Body Model (RD = 1.5kΩ, CS = 100pF) All Pins to GND.................................................................±2kV ISO 10605 (RD = 2kΩ, CS = 330pF) Contact Discharge (OUT+, OUT-) to GND.....................±10kV Air Discharge (OUT+, OUT-) to GND.............................±30kV Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, PWRDWN = high, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN, PWRDWN, RNG_, MOD_) High-Level Input Voltage VIH Low-Level Input Voltage VIL Input Current IIN Input Clamp Voltage VCCIN = 1.71V to <3V 0.65VCCIN VCCIN + 0.3 2 VCCIN = 1.71V to <3V VIN = -0.3V to (VCCIN + 0.3V), VCCIN = 1.71V to 3.6V, PWRDWN = high or low VCL ICL = -18mA VOD Figure 1 ∆VOD Figure 1 VOS Figure 1 ∆VOS Figure 1 VCCIN + 0.3 V -0.3 0.3VCCIN -0.3 +0.8 -70 +70 µA -1.5 V 450 mV 20 mV 1.375 V 20 mV ±8 +15 mA 5.5 15 mA +1 µA V LVDS OUTPUTS (OUT+, OUT-) Differential Output Voltage Change in VOD Between Complementary Output States Common-Mode Voltage Change in VOS Between Complementary Output States Output Short-Circuit Current Magnitude of Differential Output Short-Circuit Current Output High-Impedance Current 2 IOS IOSD IOZ 250 1.125 VOUT+ or VOUT- = 0 or 3.6V -15 VOD = 0 PWRDWN = low or VCC_ = 0 OUT+ = 0, OUT- = 3.6V 335 1.29 -1 OUT+ = 3.6V, OUT- = 0 _______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer (VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, PWRDWN = high, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL Differential Output Resistance Worst-Case Supply Current Power-Down Supply Current CONDITIONS MIN TYP MAX UNITS 78 110 147 Ω 3MHz 15 25 5MHz 18 25 10MHz 23 28 RO ICCW ICCZ RL = 100Ω ± 1%, CL = 5pF, continuous 10 transition words, modulation off 20MHz 33 39 35MHz 50 70 (Note 3) 50 mA µA AC ELECTRICAL CHARACTERISTICS (VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25°C.) (Note 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 28.57 333.00 ns fCLK 3 35 MHz ∆fCLK -2 +2 % PCLK_IN TIMING REQUIREMENTS Clock Period tT Clock Frequency Clock Frequency Difference from Deserializer Reference Clock Clock Duty Cycle DC Clock Transition Time Figure 2 tHIGH/tT or tLOW/tT, Figure 2 35 50 65 % 2.5 ns 215 350 ps 206 350 ps tR, tF Figure 2 Output Rise Time tRISE 20% to 80%, VOD ≥ 250mV, modulation off, Figure 3 Output Fall Time tFALL 80% to 20%, VOD ≥ 250mV, modulation off, Figure 3 Input Setup Time tSET Figure 4 3 ns Input Hold Time tHOLD Figure 4 3 ns Serializer Delay tSD Figure 5 3.15 x tT PLL Lock Time tLOCK tPD SWITCHING CHARACTERISTICS Power-Down Delay 3.2 x tT ns Figure 6 16385 x tT ns Figure 7 1 µs _______________________________________________________________________________________ 3 MAX9217 DC ELECTRICAL CHARACTERISTICS (continued) AC ELECTRICAL CHARACTERISTICS (continued) (VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25°C.) (Note 4) PARAMETER Peak-to-Peak Output Offset Voltage SYMBOL VOSp-p TYP MAX 700Mbps data rate, CMF open, Figure 8 CONDITIONS MIN 22 70 700Mbps data rate, CMF 0.1µF to ground, Figure 8 12 50 UNITS mV Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VOD, ∆VOD, and ∆VOS. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25°C. Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ VCCIN - 0.3V. PWRDWN is ≤ 0.3V. Note 4: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma. Typical Operating Characteristics (TA = +25°C, VCC_ = +3.3V, RL = 100Ω, modulation off, unless otherwise noted.) WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY MAX9217 toc01 60 50 SUPPLY CURRENT (mA) MAX9217 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer 40 30 20 10 0 3 7 11 15 19 23 27 31 35 FREQUENCY (MHz) 4 _______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer PIN NAME FUNCTION 1, 13, 37 GND Input Buffer Supply and Digital Supply Ground 2 VCCIN Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 3–10, 39–48 RGB_IN[17:0] LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to GND. 11, 12, 15–21 CNTL_IN[8:0] LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN when DE_IN is low. Internally pulled down to GND. 14, 38 VCC 22 DE_IN 23 PCLK_IN 24 MOD0 LVTTL/LVCMOS Modulation Rate Input. Selects the phase-modulation step size. Internally pulled down to GND. 25 MOD1 LVTTL/LVCMOS Modulation Rate Input. Selects the phase-modulation step size. Internally pulled down to GND. 26 PLL GND 27 VCCPLL 28 PWRDWN 29 CMF 30, 31 LVDS GND Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Data Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally pulled down to GND. LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL reference clock. Internally pulled down to GND. PLL Supply Ground PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter common-mode switching noise. LVDS Supply Ground 32 OUT- Inverting LVDS Serial Data Output 33 OUT+ Noninverting LVDS Serial Data Output 34 VCCLVDS LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 35 RNG1 LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the PCLK_IN frequency as shown in Table 3. Internally pulled down to GND. 36 RNG0 LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the PCLK_IN frequency as shown in Table 3. Internally pulled down to GND. EP GND Exposed Pad (Thin QFN Package Only). Connect Thin QFN exposed pad to PC board GND. _______________________________________________________________________________________ 5 MAX9217 Pin Description 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer MAX9217 Functional Diagram RGB_IN 1 INPUT LATCH CNTL_IN 0 OUT+ DC BALANCE/ ENCODE PAR-TO-SER CMF DE_IN PCLK_IN RNG0 RNG1 OUT- MOD0 PLL TIMING AND CONTROL MOD1 MAX9217 PWRDWN RL / 2 OUT+ VOD OUT- VOS RL / 2 GND ((OUT+) + (OUT-)) / 2 OUTVOS(-) VOS(+) VOS(-) OUT+ ∆VOS = |VOS(+) - VOS(-)| VOD(+) VOD = 0V VOD(-) ∆VOD = |VOD(+) - VOD(-)| (OUT+) - (OUT-) Figure 1. LVDS DC Output Load and Parameters 6 _______________________________________________________________________________________ VOD(-) 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer MAX9217 tT VIHmin tHIGH PCLK_IN VILmax tR tF tLOW Figure 2. Parallel Clock Requirements OUT+ RL OUTCL CL 80% 80% 20% 20% (OUT+) - (OUT-) tFALL tRISE Figure 3. Output Rise and Fall Times VIHmin PCLK_IN VILmax tSET tHOLD RGB_IN[17:0] VIHmin VIHmin VILmax VILmax CNTL_IN[8:0] DE_IN Figure 4. Synchronous Input Timing _______________________________________________________________________________________ 7 MAX9217 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer EXPANDED TIME SCALE RGB_IN CNTL_IN N N+1 N+3 N+2 N+4 PCLK_IN N-1 N OUT_ tSD BIT 0 BIT 19 Figure 5. Serializer Delay VILmax PWRDWN tLOCK (OUT+) - (OUT-) VOD = 0V HIGH-Z PCLK_IN Figure 6. PLL Lock Time PWRDWN VILmax tPD (OUT+) - (OUT-) HIGH-Z PCLK_IN Figure 7. Power-Down Delay 8 _______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer MAX9217 OUT- OUT+ ((OUT+) + (OUT-)) / 2 VOS(P-P) VOS(P-P) Figure 8. Peak-to-Peak Output Offset Voltage Detailed Description The MAX9217 DC-balanced serializer operates at a parallel clock frequency of 3MHz to 35MHz, serializing 18 bits of parallel video data RGB_IN[17:0] when the data enable input DE_IN is high, or 9 bits of parallel control data CNTL_IN[8:0] when DE_IN is low. The RGB video input data are encoded using 2 overhead bits, EN0 and EN1, resulting in a serial word length of 20 bits (Table 1). Control inputs are mapped to 19 bits and encoded with 1 overhead bit, EN0, also resulting in a 20-bit serial word. Encoding reduces EMI and main- tains DC balance across the serial cable. Two transition words, which contain a unique bit sequence, are inserted at the transition boundaries of video-to-control and control-to-video phases. Control data inputs C0 to C4 are mapped to 3 bits each in the serial control word (Table 2). At the deserializer, 2 or 3 bits at the same state determine the state of the recovered bit, providing single bit-error tolerance for C0 to C4. Control data that may be visible if an error occurs, such as VSYNC and HSYNC, can be connected to these inputs. Control data inputs C5 to C8 are mapped to 1 bit each. Table 1. Serial Video Phase Word Format 14 15 16 17 18 19 EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 Bit 0 is the LSB and is serialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 S13 S14 S15 S16 S17 Table 2. Serial Control Phase Word Format 0 EN0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 C0 C0 C0 C1 C1 C1 C2 C2 C2 C3 C3 C3 C4 C4 C4 C5 C6 C7 C8 Bit 0 is the LSB and is serialized first. C[8:0] are the control inputs. _______________________________________________________________________________________ 9 MAX9217 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer CONTROL PHASE TRANSITION PHASE VIDEO PHASE TRANSITION PHASE CONTROL PHASE PCLK_IN CNTL_IN DE_IN RGB_IN = NOT SAMPLED BY PCLK_IN Figure 9. Transition Timing Transition Timing The transition words require interconnect bandwidth and displace control data. Therefore, control data is not sampled (see Figure 9): • Two clock cycles before DE_IN goes high. • During the video phase. • Two clock cycles after DE_IN goes low. The last sampled control data are latched at the deserializer control data outputs during the transition and video phases. Video data are latched at the deserializer RGB data outputs during the transition and control phases. Applications Information AC-Coupling Benefits AC-coupling increases the common-mode voltage to the voltage rating of the capacitor. Two capacitors are sufficient for isolation, but four capacitors—two at the serializer output and two at the deserializer input—provide protection if either end of the cable is shorted to a high voltage. AC-coupling blocks low-frequency ground shifts and common-mode noise. The MAX9217 serializer can also be DC-coupled to the MAX9218 deserializer. 10 Figure 10 shows an AC-coupled serializer and deserializer with two capacitors per link, and Figure 11 is the AC-coupled serializer and deserializer with four capacitors per link. Selection of AC-Coupling Capacitors See Figure 12 for calculating the capacitor values for AC-coupling, depending on the parallel clock frequency. The plot shows capacitor values for two- and fourcapacitor-per-link systems. For applications using less than 18MHz clock frequency, use 0.125µF capacitors. Frequency-Range Setting RNG[1:0] The RNG[1:0] inputs select the operating frequency range of the MAX9217 serializer. An external clock within this range is required for operation. Table 3 shows the selectable frequency ranges and corresponding data rates for the MAX9217. ______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer OUT IN * CMF DE_IN 82Ω PLL MOD0 TIMING AND CONTROL R/F OUTEN RGB_OUT 1 CNTL_OUT 0 DE_OUT 82Ω PCLK_OUT RNG0 PCLK_IN RNG0 RNG1 DC BALANCE/ DECODE PAR-TO-SER 0 CNTL_IN DC BALANCE/ ENCODE 1 INPUT LATCH RGB_IN * SER-TO-PAR 130Ω 130Ω PLL RNG1 REF_IN MOD1 PWRDWN TIMING AND CONTROL PWRDWN LOCK MAX9217 MAX9218 CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE *CAPACITORS CAN BE AT EITHER END. Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link VCC IN OUT CMF DE_IN 82Ω 82Ω RNG0 PCLK_IN RNG0 RNG1 PLL TIMING AND CONTROL MOD0 SER-TO-PAR 130Ω DC BALANCE/ DECODE 0 PAR-TO-SER CNTL_IN 1 INPUT LATCH RGB_IN DC BALANCE/ ENCODE 130Ω RNG1 1 0 R/F OUTEN RGB_OUT CNTL_OUT DE_OUT PCLK_OUT PLL REF_IN MOD1 PWRDWN TIMING AND CONTROL PWRDWN MAX9217 CERAMIC RF SURFACE-MOUNT CAPACITOR LOCK MAX9218 100Ω DIFFERENTIAL STP CABLE Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link ______________________________________________________________________________________ 11 MAX9217 VCC MAX9217 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer Table 3. Parallel Clock Frequency Range Select AC-COUPLING CAPACITOR VALUE vs. PARALLEL CLOCK FREQUENCY 140 SERIAL DATA RATE (Mbps) 0 0 3 to 5 60 to 100 0 1 5 to10 100 to 200 95 1 0 10 to 20 200 to 400 80 1 1 20 to 35 400 to 700 MAX9217 fig12 RNG0 125 CAPACITOR VALUE (nF) PARALLEL CLOCK (MHz) RNG1 FOUR CAPACITORS PER LINK 110 65 TWO CAPACITORS PER LINK 50 Table 4. Modulation Rate Function Table 35 20 18 21 24 27 30 33 MOD1 MOD0 SIMULATED PEAK POWER REDUCTION (dB) 0 0 0 (off) 0 1 2.5 1 0 4.5 1 1 (reserved) 36 PARALLEL CLOCK FREQUENCY (MHz) Figure 12. AC-Coupling Capacitor Values vs. Clock Frequency of 18MHz to 35MHz Phase-Modulation Setting MOD[1:0] The serial output edges can be phase shifted (modulated) to reduce EMI. Table 4 shows the available settings for phase modulation. Two shift amplitudes are available. The parallel clock frequency should be 10MHz or higher for the highest amplitude (MOD1 = 1, MOD0 = 0). Termination The MAX9217 has an integrated 100Ω output-termination resistor. This resistor damps reflections from induced noise and mismatches between the transmission line impedance and termination resistors at the deserializer input. With PWRDWN = low or with the supply off, the output termination is switched out and the LVDS output is high impedance. OUT+ RO / 2 CMF RO / 2 CCMF OUT- Common-Mode Filter The integrated 100Ω output termination is made up of two 50Ω resistors in series. The junction of the resistors is connected to the CMF pin for connecting an optional common-mode filter capacitor. Connect the filter capacitor to ground close to the MAX9217 as shown in Figure 13. The capacitor shunts common-mode switching current to ground to reduce EMI. 12 Figure 13. Common-Mode Filter Capacitor Connection ______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer Power-Supply Circuits and Bypassing The MAX9217 has isolated on-chip power domains. The digital core supply (VCC) and single-ended input supply (VCCIN) are isolated but have a common ground (GND). The PLL has separate power and ground (VCCPLL and VCCPLL GND) and the LVDS input also has separate power and ground (VCCLVDS and VCCLVDS GND). The grounds are isolated by diode connections. Bypass each VCC, VCCIN, VCCPLL, and VCCLVDS pin with high-frequency, surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. PLL Lock Time The PLL lock time is set by an internal counter. The lock time is 16,385 PCLK_IN cycles. Power and clock should be stable to meet the lock-time specification. Input Buffer Supply The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, RNG0, RNG1, MOD0, MOD1, PCLK_IN, and PWRDWN) are powered from V CCIN. V CCIN can be connected to a 1.71V to 3.6V supply, allowing logic inputs with a nominal swing of VCCIN. If no power is applied to VCCIN when power is applied to VCC, the inputs are disabled and PWRDWN is internally driven low, putting the device in the power-down state. LVDS Output The LVDS output is a current source. The voltage swing is proportional to the termination resistance. The output is rated for a differential load of 100Ω ±1%. Cables and Connectors Interconnect for LVDS typically has a differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. ______________________________________________________________________________________ 13 MAX9217 Power-Down and Power-Off Driving PWRDWN low stops the PLL, switches out the integrated 100Ω output termination, and puts the output in high impedance to ground and differentially. With PWRDWN ≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or ≥ VCCIN - 0.3V, supply current is reduced to 50µA or less. Driving PWRDWN high starts PLL lock to PCLK_IN and switches in the 100Ω output termination resistor. The LVDS output is not driven until the PLL locks. The LVDS output is high impedance to ground and 100Ω differential. The 100Ω integrated termination pulls OUT+ and OUT- together while the PLL is locking so that VOD = 0V. If VCC = 0, the output resistor is switched out and the LVDS outputs are high impedance to ground and differentially. MAX9217 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer Board Layout ESD Protection Separate the LVTTL/LVCMOS inputs and LVDS output to prevent crosstalk. A four-layer PC board with separate layers for power, ground, and signals is recommended. The MAX9217 ESD tolerance is rated for Human Body Model and ISO 10605. ISO 10605 specifies ESD tolerance for electronic systems. The Human Body Model discharge components are C S = 100pF and R D = 1.5kΩ (Figure 14). The ISO 10605 discharge components are CS = 330pF and RD = 2kΩ (Figure 15). 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF RD 1.5kΩ 50Ω TO 100Ω CHARGE-CURRENTLIMIT RESISTOR DISCHARGE RESISTANCE STORAGE CAPACITOR Figure 14. Human Body ESD Test Circuit DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE CS 330pF RD 2kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 15. ISO 10605 Contact-Discharge ESD Test Circuit Chip Information TRANSISTOR COUNT: 16,608 PROCESS: CMOS 14 ______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer 32L/48L,TQFP.EPS PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm 21-0054 E 1 2 PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm 21-0054 E 2 2 ______________________________________________________________________________________ 15 MAX9217 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 48L THIN QFN.EPS MAX9217 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer PACKAGE OUTLINE, 48L THIN QFN 6x6x0.8mm BODY / 0.4mm LEAD PITCH A 21-0160 1 2 NOTE : 1. ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. COPLANARITY SHALL NOT EXCEED 0.08mm. 3. WARPAGE SHALL NOT EXCEED 0.10 mm. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC. (S) 5. REFER TO JEDEC MO-220. 6. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 7. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. EXPOSED PAD VARIATONS COMMON DIMENSIONS MIN. NOM. MAX. A 0.700 0.750 0.800 A1 0.000 -- -- 0.050 SYMBOLS A2 D2 E2 PKG. CODE MIN. NOM. MAX. MIN. NOM. MAX. T4866-1 4.20 4.30 4.40 4.20 4.30 4.40 0.200 REF. b 0.150 0.200 0.250 D 5.900 6.000 6.100 e 0.400 TYP. E 5.900 6.000 6.050 k 0.250 0.350 0.450 k1 0.350 0.450 0.550 L 0.400 0.500 0.600 L1 0.300 0.400 0.500 N 48 ND 12 NE 12 PACKAGE OUTLINE, 48L THIN QFN 6x6x0.8mm BODY / 0.4mm LEAD PITCH 21-0160 A 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.