MB15U36
Dual PLL Frequency Synthesizer
with On-Chip Prescaler
Packages
Description
The Fujitsu MB15U36 dual PLL is a serial input frequency
synthesizer with 2.0 GHz and 1.2 GHz prescalers.The
prescalers both have a selectable dual modulus division ratio
of 64/65 or 128/129 enabling pulse swallow operation. The
MB15U36 utilizes a refined charge pump design (Fujitsu’s
Super Charger)that provides fast tuning along with low
spurious noise and phase noise characteristics. The MB15U36
is ideally suited for digital mobile communications, including
GSM, DCS1800, PCS1900, IS-136, IS-95 and ISM-band
applications.
20-pin plastic SSOP,
FPT-20P-M03
Features
• Very low spurious and phase noise characteristics
• Wide operating voltage: 3.0 to 5.5 volts
• Low operating current: 6.0 mA @ VCC = 3 volts (typical)
• 18-bit programmable divider:
– Binary 7-bit swallow counter: 0 to 127
– Binary 11-bit programmable counter: 3 to 2047
• Power-saving current: 10µA (typical)
• Software selectable charge pump current:
– Do output ±1.0 or ±4.0 mA @ VCC = 3V
• Wide operating temperature: –40 to +85°C
• Evaluation Kits available
• Plastic 20-pin SSOP package
• Reference counter:
– 15-bit programmable divider: 3 to 32767
Parameter
RF frequency of operation, max.
MB15U36
2.0 GHz
IF/RF frequency of operation, max
1.2 GHz
Low power supply voltage
3 - 5.5V
Low power supply current
6.0 mA @ 3V
Prescaler divide ratios
RF1, RF2 = 64/65 or 128/129
Power-saving function
10µA typical
MB15U36
Table of Contents
Pin Descriptions: MB15U36 ................................................................................................................................................... 4
Block Diagram: MB15U36 ..................................................................................................................................................... 5
Absolute Maximum Ratings .................................................................................................................................................... 6
Recommended Operating Conditions........................................................................................................................................ 6
Handling Precautions...................................................................................................................................................... 6
Electrical Characteristics........................................................................................................................................................ 7
Measurement Circuit (fin, OSCIN Input Sensitivity) .................................................................................................................... 9
Typical Electrical Characteristics ........................................................................................................................................... 10
Reference Information ................................................................................................................................................... 13
Functional Descriptions ....................................................................................................................................................... 14
Serial Data Input .......................................................................................................................................................... 14
Table 1: Control Bits ..................................................................................................................................................... 14
Shift Register Configuration for the Programmable Reference Counter .......................................................................... 14
Shift Register Configuration for the Programmable Counter ........................................................................................ 15
Table 2: Binary 14-bit Programmable Reference Counter Data Setting................................................................................. 15
Table 3: Phase Comparator Phase Switching Data Setting.................................................................................................. 15
Table 4: Charge Pump Current Setting ............................................................................................................................ 16
Table 5: Charge Pump Output Impedance Setting ............................................................................................................. 16
Table 6: LD/fOUT Output Select Data Setting.................................................................................................................... 16
Table 7: Binary 11-bit Programmable Counter Data Setting............................................................................................... 16
Table 8: Binary 7-bit Swallow Counter Data Setting ......................................................................................................... 17
Table 9: Prescaler Data Setting ...................................................................................................................................... 17
Power Saving Mode (Intermittent Mode Control Circuit) ........................................................................................................ 17
Table 10: Power Save Internal Shutdown Logic.................................................................................................................. 17
Serial Data Input Timing ..................................................................................................................................................... 18
Table 11: Timing Parameters.......................................................................................................................................... 18
Power-ON Timing Diagram ........................................................................................................................................... 18
Phase Detector Output Waveform .......................................................................................................................................... 19
Application Example ........................................................................................................................................................... 20
Application Example: Fastlock Mode ..................................................................................................................................... 21
Ordering Information .......................................................................................................................................................... 22
Package Dimensions ........................................................................................................................................................... 23
Fujitsu Microelectronics, Inc.
3
Dual PLL Frequency Synthesizer with On-Chip Prescaler
Pin Descriptions: MB15U36
Pin No.
SSOP
Pin Name
I/O
Descriptions
1
Vcc1
–
Power supply voltage input pin for the RF1-PLL section, the shift register, and the oscillator input buffer. When poweris OFF, latched data
for RF1-PLL is lost.
2
Vp1
I
Power supply for the RF1-PLL charge pump. (Independent of pin 19)
3
Do1
O
Charge pump output for the RF1-PLL section. Phase detector characteristics can be reversed using the FC-bit.
4
GND1
–
Ground for the RF1-PLL section.
5
fin1
I
Prescaler input for the RF1-PLL. Connection to an external VCO should be via AC coupling.
6
Xfin1
I
Prescaler complimentary input for the RF1-PLL section. This pin should be grounded via a small capacitor.
7
GND1
–
Ground for the RF1-PLL section.
8
OSCIN
I
External TCXO reference oscillator input or connection to crystal. TCXO should be connected via AC coupling.
9
OSCOUT
O
Oscillator output or connection to crystal.
10
LD/fOUT
O
Lock detect signal output (LD) or phase comparator monitoring output (fout). The output signal is selected by the LDS and FDS bits in the
serial programming data.
11
Clock
I
Clock input for the 22-bit shift register. One bit of data is shifted into the shift register on a rising edge of the clock.
12
Data
I
Serial data input. Data is transferred to the corresponding latch (RF1-ref counter, RF1-prog. counter, RF2-ref. counter, RF2-prog. counter)
according to the control bits settings in the serial programming data.
13
LE
I
Load enable signal input. When the LE bit is set to “H”, data in the shift register is transferred to the corresponding latch ac cording to the
control bits settings in the serial programming data.
14
GND2
–
Ground for the RF2-PLL section.
15
Xfin2
I
Prescaler complimentary input for the RF2-PLL section. This pin should be grounded via a small capacitor.
16
fin2
I
Prescaler input for the RF2-PLL. Connection to an external VCO should be via AC coupling.
17
GND2
–
Ground for the RF2-PLL section.
18
Do2
O
Charge pump output for the RF2-PLL section. Phase detector characteristics can be reversed using the FC-bit.
19
Vp2
I
Power supply for the RF2-PLL charge pump. (Independent of pin 2)
20
Vcc2
–
Power supply voltage input pin for the RF2-PLL section. When power is OFF, latched data for RF2-PLL is lost.
Vcc1
1
20
Vcc2
Vp1
2
19
Vp2
Do1
3
18
Do2
GND1
4
17
GND2
fin1
5
Xfin1
6
GND1
7
14
GND2
OSCIN
8
13
LE
OSCOUT
9
12
Data
LD/fOUT
10
11
Clock
(FPT-20P-M03)
4
Fujitsu Microelectronics, Inc.
fin2
TOP 16
VIEW 15
Xfin2
MB15U36
Block Diagram: MB15U36
VCC2
20
2-bit latch
SW
fin2 16
Xfin2 15
PS
7-bit latch
11-bit latch
Binary 7-bit
swallow counter
(RF2-PLL)
Binary 11-bit
programmable
counter (RF2-PLL)
fpRF2
GND2
14 17
Vp2
19
Phase
comp.
Charge pump
(RF2-PLL)
(RF2-PLL)
Prescaler
18 Do2
Lock Detect
(RF2-PLL)
64/65, 128/129
(RF2-PLL)
5-bit latch
FC
CMC
ZC
LDS FDS
LDRF2
15-bit latch
Binary 15-bit
programmable ref.
counter (RF2-PLL)
OSCOUT 9
frRF2
OSCIN 8
Selector
LDRF2
FC
CMC
ZC
LDS FDS
OR
Binary 15-bit
programmable ref.
counter (RF1-PLL)
LDRF1
frRF2
frRF1
frRF1
10 LD/fout
fpRF2
5-bit latch
15-bit latch
fpRF1
LDRF1
fin1 5
Xfin1 6
Prescaler
Lock Detect
(RF1-PLL)
64/65, 128/129
(RF1-PLL)
SW
PS
Binary 7-bit
swallow counter
(RF1-PLL)
Binary 11-bit
programmable
counter (RF1-PLL)
7-bit latch
11-bit latch
2-bit latch
LE 13
Data 12
Clock 11
fpRF1
Phase
comp.
Charge pump
(RF1-PLL)
(RF1-PLL)
3 Do1
Latch selector
C C
N N
1 2
22-bit shift register
1
Vcc1
4 7
2
GND2
Vp1
Fujitsu Microelectronics, Inc.
5
Dual PLL Frequency Synthesizer with On-Chip Prescaler
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Vcc1,2
–0.5 to +6.5
V
Vp1,2
–0.5 to +6.5
V
Input voltage
VI
–0.5 to +6.5
V
Output voltage
VO
–0.5 to +6.5
V
Storage temperature
TSTG
–55 to +125
°C
Power supply voltage
Note
WARNING: Semiconductor devices can be permanently damaged by the application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed
these ratings.
Recommended Operating Conditions
Value
Parameter
Symbol
Unit
Note
Min.
Typ.
Max.
Vcc
3.0
5.0
5.5
V
Vcc1 = Vcc2
Vp
3.0
5.0
5.5
V
Vcc1 = Vcc2 *1
Input voltage
VI
GND
–
VCC
V
Operating temperature
Ta
–40
–
+85
°C
Power supply voltage
*1: Prescaler divide ratio is only 64/65 (SW = “L”) at RF1.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these
ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device
failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions
are advised to contact their Fujitsu representative beforehand.
Handling Precautions
• This device should be transported and stored in anti-static containers
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded.
Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
6
Fujitsu Microelectronics, Inc.
MB15U36
Electrical Characteristics
(VCC =3.0 to 5.5V,Ta = –40 to +85°C)
Value
Parameter
Symbol
Icc1*1
Condition
Unit
Vcc = 5V
–
6.0
–
mA
Vcc = 3V
–
3.5
–
mA
fin2 = 1200 MHz
fosc = 12 MHz
Vcc = 5V
–
3.0
–
mA
Vcc = 3V
–
2.5
–
mA
Vcc1 current at PS bitRF1, RF2 =“H”
–
0.1*3
10
µA
Ips2
Vcc1 current at PS bit RF2 =“H”
–
0.1*3
10
µA
fin1*4
RF1-PLL
100
–
2000
MHz
fin2*4
RF2-PLL
50
–
1200
MHz
fOSC
500mVp-p minimm
3
–
40
MHz
fin RF1-PLL
PfinRF1- PLL
50Ω load system
(Refer to measurement circuit.)
–10
–
+2
dBm
finRF2-PLL
PfinRF2-PLL
50Ω load system
(Refer to measurement circuit.)
–10
–
+2
dBm
Vp-p
Operating frequency
Input sensitivity
OSCIN
VOSC
0.5
–
VCC
Data, Clock,
LE
VIH
VCC × 0.8
–
–
VIL
–
–
VCC × 0.2
Data, Clock,
LE
Input current
OSCIN
LD/fOUT
Output voltage
Do1, Do2
High impedance cutoff
current
Max.
Ips1
Power saving current
Input voltage
Typ.
fin1 = 2000 MHz
fosc = 12 MHz
Power supply current
Icc2*2
Min.
Do1, Do2
LD/fOUT
IIH*5
VIH = Vcc
–1.0
–
+1.0
IIL*5
VIL = Vcc
–1.0
–
+1.0
IIH
VIH = Vcc
0
–
+100
IIL*5
VIL = Vcc
–100
–
0
VOH
IOH = –1 mA
Vcc –0.4
–
–
VOL
IOL = 1 mA
–
–
0.4
VDOH
IOH = –0.5 mA
Vcc –0.4
–
–
VDOL
IOL = 0 .5 mA
–
–
0.4
IOFF
VCC = Vp = 5.0V
0.5V ≤ VDO ≤ Vp – 0.5V
–
–
3.0
nA
IOH*5
VCC = 5.0V
–1.0
–
–
mA
IOL
VCC = 5.0V
–
–
1.0
mA
IDOH*5
Output current
V
IDOL
Do1, Do2
IDOH*5
IDOL
µA
µA
V
V
VCC = Vp = 5.0V
CMC bit = “L”
–
–1.25
–
mA
VCC = Vp = 3.0V
CMC bit = “L”
–
–1.0
–
mA
VCC = Vp = 5.0V
CMC bit = “L”
–
1.25
–
mA
VCC = Vp = 3.0V
CMC bit = “L”
–
1.0
–
mA
VCC = Vp = 5.0V
CMC bit = “H”
–
–5.0
–
mA
VCC = Vp = 3.0V
CMC bit = “H”
–
–4.0
–
mA
VCC = Vp = 5.0V
CMC bit = “H”
–
5.0
–
mA
VCC = 3.0V
CMC bit = “H”
–
4.0
–
mA
Fujitsu Microelectronics, Inc.
7
Dual PLL Frequency Synthesizer with On-Chip Prescaler
Value
Parameter
Charge pump current
characteristics
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
Symbol
Condition
Max.
Unit
IDOMT*6
VDO = VCC/2
–
3
–
%
IDO vs VDO
IDOVD*7
0.5V ≤ VDO ≤ VCC – 0.5V
–
15
–
%
IDO vs Ta
IDOTA*8
–40×C ≤ Ta ≤ +85°C,
VDO = Vp/2
–
10
–
%
I1
I3
I2
IDOL
I4
I2
I1
0.5
Vcc/2
Vcc − 0.5 V Vcc
Charge Pump Output Voltage (V)
8
Typ.
IDOL/IDOH
Conditions: Vcc1 = 5.0V, Ta = +25°C, in locking state.
Conditions: Vcc2 = 5.0V, Ta = +25°C, in locking state.
Conditions: Vcc = 5.0V, fOSC = 12.8MHz (-2dBm),Ta = +25°C
AC coupling, 1000pF capacitor is connected under the condition of min. operating frequency.
The symbol “–” (minus) means direction of current flow.
VCC = 5.0 V, Ta = +25°C (|I3| – |I4|)/[(|I3| + |I4|)/2] X 100(%)
VCC = 5.0 V, Ta = +25°C [(|I2| – |I1|)/2]/[(|I1| + |I2|)/2] X 100(%) (Applied to each IDOL, IDOH)
VCC = 5.0 V, [|IDO(85°C) – IDO(–40°C)|/2]/[|IDO(85°C) + IDO(–40°C)|/2] X 100(%) (Applied to each IDOL, IDOH)
IDOH
Min.
Fujitsu Microelectronics, Inc.
MB15U36
Measurement Circuit (For Measuring Input Sensitivity of fin and OSCin)
fOUT
Oscilloscope
Sig. Gen.
1000 pF
50 Ω
1000 pF
Sig. Gen.
1000 pF
.1 µF
50 Ω
LD/fOUT
OSCOUT
OSCIN
GND1
10
9
8
7
Xfin1
6
fin1
5
GND1
.1 µF
Do1
Vp1
Vcc1
4
3
2
1
MB15U36
11
Clock
From Controller
12
Data
13
LE
14
15
16
17
18
19
20
GND2
Xfin2
fin2
GND2
Do2
Vp2
Vcc2
1000 pF
.1 µF
Sig. Gen.
.1 µF
1000 pF
50 Ω
Fujitsu Microelectronics, Inc.
9
Dual PLL Frequency Synthesizer with On-Chip Prescaler
Typical Electrical Characteristics: MB15U36
Input Sensivity of fin (RF1) versus Input Frequency
VfinRF1 VS. finRF1
PfinRF1 vs. finRF1
10
Pfin R F1 [dBm]
(dBm )
VfinRF1
0
SPEC
-10
-20
P fin(dB m ]@
)@ 5.5V
Vfin[dBm
Vfin[dBm
]@ 5.0V
Pfin(dBm)@5.0V
Vfin[dBm
]@ 4.5V
Pfin(dBm)@4.5V
Vfin[dBm
]@ 3.0V
Pfin(dBm)@3.0V
-30
-40
-50
0
500
1000
1500
2000
2500
3000
finRF1
[MHz]
finRF1 (MHz)
Input Sensivity of fin (RF2) versus Input Frequency
VfinRF2 VS. finRF2
PfinRF2 vs. finRF2
10
VfinRF2 (dBm
[dBm])
Pfin
RF2
0
SPEC
-10
PVfin[dBm]@5.5V
fin(dB m )@ 5.5V
Pfin(dBm)@5.0V
Vfin[dBm]@5.0V
Pfin(dBm)@4.5V
Vfin[dBm]@4.5V
Pfin(dBm)@3.0V
Vfin[dBm]@3.0V
-20
-30
-40
-50
0
500
1000
1500
2000
finRF2 (MHz)
finRF2
[MHz]
Input Sensivity of OSCIN versus Input Frequency
Vfosc VS. fosc
PfinOSC vs. finRF2
10
SPEC
Pfin
(dBm )
VOSC
O S C [dBm]
0
-10
-20
VOSCin[dBm]@5.5V
P O S C (dB m )@ 5.5V
PO SC (dBm)@5.0V
VOSCin[dBm]@5.0V
VOSCin[dBm]@4.5V
PO SC (dBm)@4.5V
VOSCin[dBm]@3.0V
PO SC (dBm)@3.0V
-30
-40
-50
0
50
100
150
fosc [MHz]
10
Fujitsu Microelectronics, Inc.
200
250
MB15U36
Typical Electrical Characteristics: MB15U36
Conditions: Ta = +25°C
Do output current: 1 x Do mode
IDOH VS. VDOH
“H” level output voltage V
(V)
DOH
“H” level output voltage
VDOH (V
IDOH - VDOH
8
7
Vcc=5V
6
Vcc=3V
5
4
3
2
1
0
0
-0.5
-1
-1.5
-2
“H” level output
IDOH
“H” level voltage
output current
IDOH(mA)
(mA)
-2.5
-3
VDOL
IDOLIDOL
VS.- VDOL
leveloutput
output voltage
VDOL VDOL
(V)
“L” “L”
level
voltage
(V
8.0
7.0
6.0
5.0
Vcc=5V
4.0
Vcc=3V
3.0
2.0
1.0
0.0
0
0.5
1
1.5
2
2.5
—IDOL
“
Í (mA)
—
d ¬IDOL(mA)
“L” level output
“L” levelvoltage
output currento
3
Fujitsu Microelectronics, Inc.
11
Dual PLL Frequency Synthesizer with On-Chip Prescaler
Typical Electrical Characteristics: MB15U36
Conditions: Ta = +25°C
Do output current: 4 x Do mode
level output voltage VDOH (V)
"H”“H”level
output voltage VDOH (V
IDOH
IDOH
VS.- V
VDOH
DOH
8
7
6
5
Vcc=5V
4
Vcc=3V
3
2
1
0
0
-1
-2
-3
-4
-5
“H” level
output IDOH
current I(mA)
“H” level output
voltage
DOH (mA)
-6
-7
-8
IDOLIDOL
VS.-VDOL
VDOL
“L” leveloutput
output voltage
VDOLVDOL
(V)
“L” level
voltage
(V
8.0
7.0
6.0
5.0
Vcc=5V
4.0
Vcc=3V
3.0
2.0
1.0
0.0
0
1
2
3
4
5
“L” level output
voltage
IDOLI (mA)
“L” level
output current
(mA)
DOL
12
Fujitsu Microelectronics, Inc.
6
7
8
MB15U36
Reference Information: MB15U36
Test Circuit
SG
OSC
IN
fin
LPF
Do
f V C O = 1780 MHz
K V = 58 MHz/V
fr = 200 KHz
f O S C = 10 MHz
LPF
750pF
Spectrum
Analyzer
VCO
V C C = V P = 3.0V
V V C O = 5.0V
Ta = +25 °C
CP: 1mA mode
3.3KΩ
6 8 0 0Ω
150pF
6 8 0 0 pF
Typical plots measure with the test circuit are shown below. Each plot shows lock up time, phase noise, and reference leakage.
RF PLL Reference Leakage
@ 200 kHz offset = -80.3 dBc
RF PLL Phase Noise
@ max within loop band = -66.5 dBc/Hz
-80.3 dBc
RF PLL Lock Up Time = 442µs
(1760.000 MHz → 1800.000 MHz, within ± 1kHz)
RF PLL Lock Up Time = 387µs
(1800.000 MHz → 1760.000 MHz, within ± 1kHz)
Fujitsu Microelectronics, Inc.
13
Dual PLL Frequency Synthesizer with On-Chip Prescaler
Functional Descriptions
The VCO output frequency can be calculated using the following equation:
fVCO = {(M x N) + A} x fOSC ÷ R (A < N)
fVCO:
M:
N:
A:
fOSC:
R:
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of dual modulus prescaler (64 or 128 for RF1-PLL or RF2-PLL2)
Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
Reference oscillation frequency
Preset divide ratio of binary 14-bit programmable reference counter (3 to 32,767)
Serial Data Input
Serial data is entered using the Data, Clock, and LE pins. The serial data controls the programmable reference counters and the programmable
counters separately.
Binary serial data is entered through the Data pin when the LE pin is held low. One bit of data is shifted into the shift register on the rising
edge of the Clock. When the LE signal pin is taken high, entered data is latched into the appropriate counters according to the control bit
settings as follows:
Table 1. Control Bits
Control Bits
CN1
CN2
L
L
Destination of Serial Data
The programmable reference counter for the RF2-PLL
L
H
The programmable reference counter for the RF1-PLL
H
L
The programmable counter and the swallow counter for the RF2-PLL
H
H
The programmable counter and the swallow counter for the RF1-PLL
Shift Register Configuration
Programmable Reference Counter
LSB
MSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
C
N
1
C
N
2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
R
15
F
C
C
M
C
Z
C
L
D
S
F
D
S
CNT1, 2
Control bits
[Table 1]
R1 to R15
Divide ratio setting bits for the programmable reference counter (3 to 32,767)
[Table 2]
FC
Phase control bit for the phase detector
[Table 3]
CMC
Charge pump current select bit
[Table 4]
ZC
Forced high impedance control for the charge pump
[Table 5]
LDS/FDS
LD/fOUT signal select bits
[Table 6]
Note: Input Data with MSB first.
14
Fujitsu Microelectronics, Inc.
MB15U36
Functional Descriptions
Programmable Counter
LSB
MSB
Data Flow
1
2
3
4
5
6
7
8
9
C
C
A
A
A
A
A
A
N
N
1
2
3
4
5
6
1
2
19
10
11
12
13
14
15
16
17
18
A
N
N
N
N
N
N
N
N
N
N
7
1
2
3
4
5
6
7
8
9
10
CNT1, 2
Control bits
[Table 1]
N1 to N11
Divide ratio setting bits for the programmable counter (3 to 2,047)
[Table 7]
A1 to A7
Divide ratio setting bits for the swallow counter (0 to 127)
[Table 8]
SW
Divide ratio setting bit for the prescalers
(64/65 or 128/129 for the RF1-PLL and RF2-PLL)
[Table 9]
PS
Power saving mode control bit
[Table 10]
20
21
22
N
S
P
11
W
S
Note: Input Data with MSB first.
Table 2. Binary 15-bit Programmable Reference Counter Data Setting
Divide
Ratio
(R)
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table 3. Phase Comparator Phase Switching Data Setting
DoRF1-PLL,RF2-PLL
(1)
FCRF1-PLL,RF2-PLL = “H”
FCRF1-PLL,RF2-PLL = “L”
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO polarity
(1)
(2)
VCO output
frequency
Notes: 1) Z = High-impedance
2) The FC bit should be set depending upon the VCO and LPF polarity
(2)
VCO input voltage
Fujitsu Microelectronics, Inc.
15
Dual PLL Frequency Synthesizer with On-Chip Prescaler
Functional Descriptions
Table 4. Charge Pump Current Setting (CMC)
CMC
Current Value
L
1 x Do
H
4 x Do
Table 5. Charge Pump Output Impedance Setting (ZC)
ZC
Do Output Impedance
L
Normal output
H
High impedance
Table 6. LD/fout Output Select Data Setting
LDSRF1
LDSRF2
FDSRF1
FDSRF2
L
L
L
L
LD/fOUT Output Signal
Disabled
L
H
L
L
LD signal (RF2 lock detect)
H
L
L
L
LD signal (RF1 lock detect)
H
H
L
L
LD signal (RF1/RF2 lock detect)
X
L
L
H
fOUT (Output frRF2)
X
L
H
L
fOUT (Output frRF1)
X
H
L
H
fOUT (Output fpRF2)
X
H
H
L
fOUT (Output fpRF2)
L
L
H
H
Fastlock
L
H
H
H
RF2 counter reset
H
L
H
H
RF1 counter reset
H
H
H
H
RF1/RF2 counter reset
Note: X = Don’t care
Table 7. Binary 11-bit Programmable Counter Data Setting
Divide
Ratio
(N)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
.
.
.
.
.
.
.
.
.
.
.
.
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
16
Fujitsu Microelectronics, Inc.
MB15U36
Functional Descriptions
Table 8. Binary 7-bit Swallow Counter Data Setting
Divide
Ratio
(A)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
.
.
.
.
.
.
.
.
127
1
1
1
1
1
1
1
Note: Divide ratio (A) range = 0 to 127
Table 9. Prescaler Data Setting (SW)
Prescaler
Divide Ratio
SW = “L”
SW = “H”
RF1-PLL
64/65
128/129
RF2-PLL
64/65
128/129
Power-Saving Mode (Intermittent Mode Control)
• The intermittent mode control circuit greatly reduces the PLL power consumption by shuting down various internal functions, as
shown in Table 10, depending upon the settings of the power save (PS) bits. Setting the PS bits to “H” enters the corresponding PLL
into the power-saving mode. See the Electrical Characteristics chart for the specific value of current when in the power-saving mode.
• The phase detector output, Do, becomes high impedance.
• Serial data can be entered while in the power-saving mode.
• Setting the PS pins “L” releases the power-saving mode, returning the selected PLL to normal operation.
Note: When power (VCC) is first applied, the device must be in standby mode, PS = High, for at least 1µs.
Table 10. Power Save Internal Shutdown Logic (PS)
PSRF2
PSRF1
RF2-PLL Counters
RF1-PLL Counters
OSC Input Buffer
H
H
OFF
OFF
OFF
L
H
ON
OFF
ON
H
L
OFF
ON
ON
L
L
ON
ON
ON
Fujitsu Microelectronics, Inc.
17
Dual PLL Frequency Synthesizer with On-Chip Prescaler
Serial Data Input Timing
1st data
2nd data
Control bit
Data
MSB
Invalid data
LSB
Clock
t1
t2
t3
t6
t7
LE
t4
t5
Table 11. Timing Parameters
Parameter
Min.
Typ.
Max.
Unit
Parameter
Min.
Typ.
Max.
Unit
t1
20
–
–
ns
t5
100
–
–
ns
t2
20
–
–
ns
t6
20
–
–
ns
t3
30
–
–
ns
t7
100
–
–
ns
t4
30
–
–
ns
Notes: 1) On the rising edge of the clock, one bit of the data is transferred into the shift register.
2) LE should be set to “L” when the data is transferred into the shift register.
Power-ON Timing
OFF
VCC
ON
tV ≥ 1 µS
Clock
Data
LE
tPS ≥ 100 nS
PS
(1)
(1) PS = H (power-saving mode) at Power-ON
(2) Input serial data 1µs later after power supply remains stable (VCC > 2.2V).
(3) Release power-saving mode (PS: H Æ L) 100ns later after setting serial data.
18
Fujitsu Microelectronics, Inc.
(2)
(3)
MB15U36
Phase Detector Output Waveform
frRF1-PLL, RF2-PLL
fpRF1-PLL, RF2-PLL
tWU
tWL
LD
(FC bit = “H”)
H
DoRF1-PLL, RF2-PLL
Z
L
(FC bit = “L”)
DoRF1-PLL, RF2-PLL
Notes:
Z
1) Phase error detection range: –2π to +2π
2) Pulses on Do signal during locked state are output to prevent dead zone.
Fujitsu Microelectronics, Inc.
19
Dual PLL Frequency Synthesizer with On-Chip Prescaler
Application Example
OUTPUT
VCO
LPF
3V
3V
TCXO
1000 pF
.1 µF
1000 pF
.1 µF
1000 pF
Lock Detect
LD/fOUT
10
OSCOUT
OSCIN
GND1
Xfin1
fin1
GND1
Do1
Vp1
Vcc1
8
7
6
5
4
3
2
1
9
MB15U36
11
12
13
14
15
16
17
18
19
20
Clock
Data
LE
GND2
Xfin2
fin2
GND2
Do2
Vp2
Vcc2
From Controller
1000 pF
1000 pF
3V
.1 µF
OUTPUT
VCO
LPF
Notes: 1) Package Type: 20-pin SSOP
2) Clock, Data, LE: Insert a pull-down or pull-up resistor as needed to prevent oscillation when the terminals are left open.
20
Fujitsu Microelectronics, Inc.
3V
.1 µF
MB15U36
Application Example: Fastlock Mode
OUTPUT
LPF
VCO
3V
3V
TCXO
1000 pF
.1 µF
1000 pF
.1 µF
1000 pF
LD/fOUT
OSCOUT
OSCIN
GND1
Xfin1
fin1
GND1
Do1
Vp1
Vcc1
10
9
8
7
6
5
4
3
2
1
MB15U36
11
Clock
12
13
14
15
16
17
18
19
20
Data
LE
GND2
Xfin2
fin2
GND2
Do2
Vp2
Vcc2
From Controller
1000 pF
1000 pF
3V
.1 µF
3V
.1 µF
OUTPUT
VCO
LPF
Notes: 1) Package Type: 20-pin SSOP
2) Clock, Data, LE: Insert a pull-down or pull-up resistor as needed to prevent oscillation when the terminals are left open
3) The Fastlock mode is controlled by the LDS/FDS bits and the CMC RF1 bit. When the CMCRF1 bit is set to “H” (the RF1 charge pump current is increased
4x normal mode), the LD/fout pin (open drain output) is “L”, enabling the parallel resistor in the loop filter. This effectively increases the LPF bandwidth,
allowing the loop to lock faster. After the loop has locked onto a new frequency, the CMCRF1 bit is set to “L”, forcing the LD/fout output pin into a high
impedance state and returning the LPF bandwidth back to its original value.
Fujitsu Microelectronics, Inc.
21
Dual PLL Frequency Synthesizer with On-Chip Prescaler
Usage Precautions
To protect against damage by electrostatic discharge, note the following handling precautions:
•
•
•
•
Store and transport devices in conductive containers.
Use properly grounded workstations, tools, and equipment.
Turn off power before inserting or removing this device into or from a socket.
Protect leads with conductive sheet when transporting a board mounted device.
Ordering Information
22
Part Number
Package
MB15U36PFV
20-pin, Plastic SSOP (FPT-20P-M03)
Fujitsu Microelectronics, Inc.
MB15U36
Package Dimensions
20-pin, Plastic SSOP
(FPT-20P-M03)
* T hese dim e nsions do not include resin protrusion
* 6.50±0.10(.256±.004)
1.25
+0.20
-0.10
.049
+.008
-.004
(Mounting height)
0.10(.004)
INDEX
* 4.40±0.10
(.173±.004)
0.65±0.12
(.0256±.0047)
5.85(.230)REF
0.22
+0.10
-0.05
.009
+.004
-.002
6.40±0.20
(.252±.008)
5.40(.213)
NOM
"A"
0.15
+0.05
-0.02
.006
+.002
-.001
Details of "A" part
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
D im ensions in m m (inches)
Fujitsu Microelectronics, Inc.
23
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