SPANSION MB84VP23481FK

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50224-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
CMOS
64M (×16) Page FLASH MEMORY &
32M (×16) Mobile FCRAMTM
MB84VP23481FK-70
■ FEATURES
• Power Supply Voltage of 2.7 V to 3.1 V
• High Performance
25 ns maximum page read access time, 65 ns maximum random access time (Flash)
20 ns maximum page read access time, 70 ns maximum random access time (FCRAM)
• Operating Temperature
–30 °C to +85 °C
• Package 65-ball FBGA
(Continued)
■ PRODUCT LINEUP
Flash
Supply Voltage (V)
VCCf* = 3.0 V
FCRAM
+0.1V
–0.3 V
+0.1V
VCCr* = 3.0 V –0.3 V
Max Random Address Access Time (ns)
65
70
Max Page Address Access Time (ns)
25
20
Max CE Access Time (ns)
65
70
Max OE Access Time (ns)
25
40
*: Both VCCf and VCCr must be the same level when either part is being accessed.
■ PACKAGE
65-ball plastic FBGA
(BGA-65P-M01)
MB84VP23481FK-70
(Continued)
— FLASH MEMORY
• Simultaneous Read/Write Operations (Dual Bank)
• FlexBankTM *1
Bank A: 8 Mbit (8 KB ×8 and 64 KB ×15)
Bank B: 24 Mbit (64 KB ×48)
Bank C: 24 Mbit (64 KB ×48)
Bank D: 8 Mbit (8 KB ×8 and 64 KB ×15)
• 8 words Page
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Minimum 100,000 Program/Erase Cycles
• Sector Erase Architecture
Eight 8 Kbytes, a hundred twenty-six 64 Kbytes, eight 8 Kbytes sectors.
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Dual Boot Block
Sixteen to 8Kbytes boot block sectors, eight at the top of the address range and eight at the bottom of the
address range
• HiddenROM Region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
At VIL, allows protection of “outermost” 2×4 K words on both ends of boot sectors, regardless of sector protection/unprotection status
At VIH, allows removal of boot sector protection
At VACC, increases program performance
• Embedded EraseTM *2 Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM *2 Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for Detection of Program or Erase Cycle Completion
• Ready/Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, the device automatically switches itself to low power mode
• Program Suspend/Resume
Suspends the program operation to allow a read in another byte
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• New Sector Protection
Persistent Sector Protection
Password Sector Protection
• Please refer to “MBM29QM64DF” Datasheet in Detailed Function
(Continued)
2
MB84VP23481FK-70
(Continued)
— FCRAMTM *3
• Power Dissipation
Operating : 30 mA Max
Standby : 100 µA Max
• Power Down Mode
Sleep
: 10 µA Max
4M Partial : 45 µA Max
8M Partial : 55 µA Max
16M Partial: 70 µA Max
• Power Down Control by CE2r
• Byte Write Control: LB(DQ7 to DQ0), UB(DQ15 to DQ8)
• 8 words Page Access Capability
*1: FlexBankTM is a trademark of Fujitsu Limited, Japan.
*2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
*3: Mobile FCRAMTM is a trademark of Fujitsu Limited, Japan.
3
MB84VP23481FK-70
■ PIN ASSIGNMENT
(Top View)
Marking Side
A10
K10
N.C.
N.C.
A9
C9
D9
E9
F9
G9
H9
K9
N.C.
A15
A21
N.C.
A16
N.C
Vss
N.C.
B8
C8
D8
E8
F8
G8
H8
J8
A11
A12
A13
A14
N.C
DQ15
DQ7
DQ14
B7
C7
D7
E7
F7
G7
H7
J7
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
B6
C6
D6
G6
H6
J6
WE
CE2r
A20
DQ4
Vccr
N.C
B5
C5
D5
G5
H5
J5
WP/ACC
RESET
RY/BY
DQ3
Vccf
DQ11
B4
C4
D4
E4
F4
G4
H4
J4
LB
UB
A18
A17
DQ1
DQ9
DQ10
DQ2
B3
C3
D3
E3
F3
G3
H3
J3
A7
A6
A5
A4
VSS
OE
DQ0
DQ8
A2
C2
D2
E2
F2
G2
H2
K2
N.C.
A3
A2
A1
A0
CEf
CE1r
N.C.
A1
B1
K1
N.C.
N.C.
N.C.
(BGA-65P-M01)
4
MB84VP23481FK-70
■ PIN DESCRIPTION
Pin name
Input/
Output
A20 to A0
I
Address Inputs (Common)
A21
I
Address Input (Flash)
DQ15 to DQ0
I/O
CEf
I
Chip Enable (Flash)
CE1r
I
Chip Enable (FCRAM)
CE2r
I
Chip Enable (FCRAM)
OE
I
Output Enable (Common)
WE
I
Write Enable (Common)
RY/BY
O
Ready/Busy Output (Flash) Open Drain Output
UB
I
Upper Byte Control (FCRAM)
LB
I
Lower Byte Control (FCRAM)
RESET
I
Hardware Reset Pin/Sector Protection Unlock (Flash)
WP/ACC
I
Write Protect / Acceleration (Flash)
N.C.
—
VSS
Power
Device Ground (Common)
VCCf
Power
Device Power Supply (Flash)
VCCr
Power
Device Power Supply (FCRAM)
Description
Data Inputs/Outputs (Common)
No Internal Connection
5
MB84VP23481FK-70
■ BLOCK DIAGRAM
VCCf
VSS
A21 to A0
RY/BY
A21 to A0
WP/ACC
64 M bit Page
Flash Memory
RESET
CEf
DQ15 to DQ0
DQ15 to DQ0
VCCr
VSS
A20 to A0
DQ15 to DQ0
LB
UB
WE
OE
CE1r
CE2r
6
32 M bit
FCRAM
MB84VP23481FK-70
■ DEVICE BUS OPERATIONS
Operation*1, *2
Full Standby
CEf
CE1r CE2r OE WE
H
H
H
L
L
H
Read from Flash*4
L
Write to Flash
L
Output Disable*3
Read from FCRAM
FCRAM No Read
Write to FCRAM
H
H
H
LB
UB
A21 to
A0
DQ7 to
DQ0
DQ15 to RESET
WP/ACC*9
DQ8
H
X
X
X
X
X
High-Z
High-Z
H
X
H
H
H
X
X
X*8
High-Z
High-Z
H
X
H
H
L
H
X
X
Valid
DOUT
DOUT
H
X
H
H
H
L
X
X
Valid
DIN
DIN
H
X
L
L
DIN
DIN
H
L
High-Z
DIN
H
X
L
H
DIN
High-Z
H
H
High-Z
High-Z
H
X
L
L
DIN
DIN
H
L
High-Z
DIN
H
X
L
H
DIN
High-Z
L
L
L
H
H
H
L
L
H*7
H
H
L
Valid
Valid
Valid
FCRAM No Write
H
L
H
H*7
L
H
H
Valid
High-Z
High-Z
H
X
Flash Temporary Sector
Group Unprotection*5
X
X
X
X
X
X
X
X
X
X
VID
X
Flash Hardware Reset
X
H
H
X
X
X
X
X
High-Z
High-Z
L
X
Flash Boot Block Sector Write
Protection
X
X
X
X
X
X
X
X
X
X
X
L
FCRAM Power Down*6
X
X
L
X
X
X
X
X
X
X
X
X
Legend: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance.
See ■DC CHARACTERISTICS for voltage levels.
*1 : Other operations except for indicated this column are inhibited.
*2 : Do not apply for two or more states of the following conditions at the same time;
• CEf = VIL
• CE1r = VIL and CE2r = VIH
*3 : Should not be kept FCRAM Output Disable condition longer than 1µs.
*4 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*5 : It is also used for the extended sector group protections.
*6 : FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
Data retention depends on the selection of Power Down Program. Please refer to “Power Down Program”
in FCRAM Characteristics part.
*7 : OE can be VIL during Write operation if the following conditions are satisfied;
1) Write pulse is initiated by CE1r (refer to CE1r Controlled Write timing), or cycle time of the previous
operation cycle is satisfied.
2) OE stays VIL during Write cycle.
*8 : Can be either VIL or VIH but must be valid before Read or Write.
*9 : Protect “outer most” 2x8K bytes (4 words) on both ends of the boot block sectors.
7
MB84VP23481FK-70
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Tstg
TA
Min
–55
–30
Voltage with Respect to Ground All pins
except RESET, WP/ACC *1
VIN, VOUT
–0.3
VCCf/VCCr Supply *1
RESET *2
WP/ACC *3
VCCf, VCCr
VIN
VIN
–0.3
–0.5
–0.5
Storage Temperature
Ambient Temperature with Power Applied
Max
+125
+85
VCCf + 0.3
VCCr + 0.3
+3.3
+ 13.0
+10.5
Unit
°C
°C
V
V
V
V
V
*1 Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to –1.0 V for periods of up to 5 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCr + 0.3V.
During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCr + 1.0 V for periods of up to 5 ns.
*2: Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions RESET pins may undershoot VSS
to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf) does not
exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods
of up to 20 ns.
*3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot
Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Ambient Temperature
VCCf/VCCr Supply Voltages
Symbol
Value
Unit
Min
Max
TA
–30
+85
°C
VCCf, VCCr
+2.7
+3.1
V
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
8
MB84VP23481FK-70
■ DC CHARACTERISTICS
Parameter
Symbol
Value
Conditions
Min
Typ Max
Unit
Input Leakage Current
ILI
VIN = VSS to VCCf, VCCr
–1.0
—
+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCCf, VCCr, Output Disable –1.0
—
+1.0
µA
RESET Inputs Leakage Current
(Flash)
ILIT
VCCf = VCCf Max, RESET = 12.5 V
—
—
35
µA
WP/ACC Acceleration Program Current
(Flash)
ILIA
VCCf = VCCf Max, WP/ACC = VACC Max
—
—
20
mA
Flash VCC Active Current *1,*6
(Initial/Random Read)
ICC1f
CEf = VIL, OE = VIH, f = 10 MHz
—
—
45
mA
CEf = VIL, OE = VIH, f = 5 MHz
—
—
20
mA
Flash VCC Active Current *2
ICC2f
CEf = VIL, OE = VIH
—
—
25
mA
Flash VCC Current (Page Mode) *9,*6
ICC3f
CEf = VIL, OE = VIH, f = 40 MHz
—
—
10
mA
Flash VCC Active Current*5,*6
(Read-While-Program)
ICC4f
CEf = VIL, OE = VIH
—
—
45
mA
Flash VCC Active Current*5,*6
(Read-While-Erase)
ICC5f
CEf = VIL, OE = VIH
—
—
45
mA
Flash VCC Active Current*5,*6
(Erase-Suspend-Program)
ICC6f
CEf = VIL, OE = VIH
—
—
25
mA
Flash VCC Current (Standby) *6
ISB1f
VCCf = VCCf Max,CEf = VCCf ±0.3 V
RESET= VCCf ±0.3 V,
WP/ACC =VCCf ±0.3 V
—
1
5
µA
Flash VCC Current (Standby, Reset) *6
ISB2f
VCCf = VCCf Max, RESET= VSS ±0.3 V
—
1
5
µA
Flash VCC Current
(Automatic Sleep Mode)*3
ISB3f
VCCf = VCCf Max, CEf= VSS ±0.3 V,
RESET= VCCf ±0.3 V,
VIN = VCCf ±0.3 V or VSSf±0.3 V
—
1
5
µA
tRC / tWC
=Min
—
—
30
tRC / tWC
=1µs
—
—
3
ICC1r
FCRAM VCC Active Current *6, *8
ICC2r
VCCr = VCCr Max,
CE1r = VIL, CE2r = VIH,
VIN = VIH or VIL,
IOUT = 0 mA*7
mA
FCRAM VCC Page Read Current *6, *8
ICC3r
VCCr = VCCr Max, VIN = VIH or VIL,
CE1r = VIL, CE2r = VIH, IOUT = 0 mA *7,
tPRC=Min
—
—
10
mA
FCRAM VCC Standby Current *6, *8
ISB1r
VCCr = VCCr Max,
VIN < 0.2V or > VCCr – 0.2V
CE1r > VCCr – 0.2V, CE2r > VCCr– 0.2V
—
—
100
µA
Sleep
—
—
10
µA
4M Partial
—
—
45
µA
8M Partial
—
—
55
µA
16M Partial
—
—
70
µA
IDDPSr
FCRAM VCC Power Down Current *6, *8
IDDP4r VCCr = VCCr Max,
CE2r < 0.2V,
IDDP8r VIN = VIH or VIL
IDDP16r
(Continued)
9
MB84VP23481FK-70
(Continued)
Symbol
Conditions
Input Low Level
VIL
Input High Level
Voltage for Sector Protection, and
Temporary Sector Unprotection
(RESET) *4
Parameter
Voltage for WP/ACC
Sector Protection/Unprotection
and Program Acceleration *4
Output Low Voltage Level
Output High Voltage Level
Flash Low VCCf Lock-Out Voltage
Value
Typ
Max
—
–0.3
—
VCC × 0.2
*6
V
VIH
—
VCC × 0.8
*6
—
VCC + 0.2
*6
V
VID
—
11.5
12
12.5
V
VACC
—
8.5
9.0
9.5
V
—
—
0.4
V
VOLf
VCCf = VCCf Min, IOL=4.0 mA
VOLr
VCCr = VCCr Min, IOL =1.0mA FCRAM
—
—
0.4
V
VOHf
VCCf = VCCf Min, IOH=–2.0 mA
Flash
2.4
—
—
V
VOHr
VCCr = VCCr Min, IOH=–0.5 mA
FCRAM
2.4
—
—
V
2.3
2.4
2.5
V
VLKO
Flash
—
*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
*4: Applicable for only VCCf applying.
*5: Embedded Algorithm (program or erase) is in progress. (@5 MHz)
*6: VCC indicates lower of VCCf or VCCr.
*7: FCRAM Characteristics are measured after following POWER-UP timing.
*8: IOUT depends on the output load conditions.
*9: Address except A2, A1 and A0 are fixed.
10
Unit
Min
MB84VP23481FK-70
■ AC CHARACTERISTICS
• CE Timing
Parameter
Symbol
JEDEC
Standard
CE Recover Time
—
tCCR
CE Hold Time
—
CE1r High to WE Invalid time for
Standby Entry
—
Condition
Value
Unit
Min
Max
—
0
—
ns
tCHOLD
—
3
—
ns
tCHWX
—
10
—
ns
• Timing Diagram for alternating RAM to Flash
CEf
tCCR
tCCR
CE1r
WE
tCHWX
tCCR
tCHOLD
tCCR
CE2r
• Flash Characteristics
Please refer to “■64 M PAEG FLASH MEMORY CHARACTERISTICS for MCP”.
• FCRAM Characteristics
Please refer to “■32 M FCRAM CHARACTERISTICS for MCP”.
11
MB84VP23481FK-70
■ 64 M PAEG FLASH MEMORY CHARACTERISTICS for MCP
1. Flexible Sector-erase Architecture on FLASH MEMORY
• Sixteen 4K words, and one hundred twenty-six 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
Bank A
Bank B
SA0 : 8KB (4KW)
SA1 : 8KB (4KW)
SA2 : 8KB (4KW)
SA3 : 8KB (4KW)
SA4 : 8KB (4KW)
SA5 : 8KB (4KW)
SA6 : 8KB (4KW)
SA7 : 8KB (4KW)
SA8 : 64KB (32KW)
SA9 : 64KB (32KW)
SA10 : 64KB (32KW)
SA11 : 64KB (32KW)
SA12 : 64KB (32KW)
SA13 : 64KB (32KW)
SA14 : 64KB (32KW)
SA15 : 64KB (32KW)
SA16 : 64KB (32KW)
SA17 : 64KB (32KW)
SA18 : 64KB (32KW)
SA19 : 64KB (32KW)
SA20 : 64KB (32KW)
SA21 : 64KB (32KW)
SA22 : 64KB (32KW)
SA23 : 64KB (32KW)
SA24 : 64KB (32KW)
SA25 : 64KB (32KW)
SA26 : 64KB (32KW)
SA27 : 64KB (32KW)
SA28 : 64KB (32KW)
SA29 : 64KB (32KW)
SA30 : 64KB (32KW)
SA31 : 64KB (32KW)
SA32 : 64KB (32KW)
SA33 : 64KB (32KW)
SA34 : 64KB (32KW)
SA35 : 64KB (32KW)
SA36 : 64KB (32KW)
SA37 : 64KB (32KW)
SA38 : 64KB (32KW)
SA39 : 64KB (32KW)
SA40 : 64KB (32KW)
SA41 : 64KB (32KW)
SA42 : 64KB (32KW)
SA43 : 64KB (32KW)
SA44 : 64KB (32KW)
SA45 : 64KB (32KW)
SA46 : 64KB (32KW)
SA47 : 64KB (32KW)
SA48 : 64KB (32KW)
SA49 : 64KB (32KW)
SA50 : 64KB (32KW)
SA51 : 64KB (32KW)
SA52 : 64KB (32KW)
SA53 : 64KB (32KW)
SA54 : 64KB (32KW)
SA55 : 64KB (32KW)
SA56 : 64KB (32KW)
SA57 : 64KB (32KW)
SA58 : 64KB (32KW)
SA59 : 64KB (32KW)
SA60 : 64KB (32KW)
SA61 : 64KB (32KW)
SA62 : 64KB (32KW)
SA63 : 64KB (32KW)
SA64 : 64KB (32KW)
SA65 : 64KB (32KW)
SA66 : 64KB (32KW)
SA67 : 64KB (32KW)
SA68 : 64KB (32KW)
SA69 : 64KB (32KW)
SA70 : 64KB (32KW)
Word Mode
000000h
001000h
002000h
003000h
004000h
005000h
006000h
007000h
008000h
010000h
018000h
020000h
028000h
030000h
038000h
040000h
048000h
050000h
058000h
060000h
068000h
070000h
078000h
080000h
088000h
090000h
098000h
0A0000h
0A8000h
0B0000h
0B8000h
0C0000h
0C8000h
0D0000h
0D8000h
0E0000h
0E8000h
0F0000h
0F8000h
100000h
108000h
110000h
118000h
120000h
128000h
130000h
138000h
140000h
148000h
150000h
158000h
160000h
168000h
170000h
178000h
180000h
188000h
190000h
198000h
1A0000h
1A8000h
1B0000h
1B8000h
1C0000h
1C8000h
1D0000h
1D8000h
1E0000h
1E8000h
1F0000h
1F8000h
1FFFFFh
Bank C
Bank D
Sector Architecture
12
SA71 : 64KB (32KW)
SA72 : 64KB (32KW)
SA73 : 64KB (32KW)
SA74 : 64KB (32KW)
SA75 : 64KB (32KW)
SA76 : 64KB (32KW)
SA77 : 64KB (32KW)
SA78 : 64KB (32KW)
SA79 : 64KB (32KW)
SA80 : 64KB (32KW)
SA81 : 64KB (32KW)
SA82 : 64KB (32KW)
SA83 : 64KB (32KW)
SA84 : 64KB (32KW)
SA85 : 64KB (32KW)
SA86 : 64KB (32KW)
SA87 : 64KB (32KW)
SA88 : 64KB (32KW)
SA89 : 64KB (32KW)
SA90 : 64KB (32KW)
SA91 : 64KB (32KW)
SA92 : 64KB (32KW)
SA93 : 64KB (32KW)
SA94 : 64KB (32KW)
SA95 : 64KB (32KW)
SA96 : 64KB (32KW)
SA97 : 64KB (32KW)
SA98 : 64KB (32KW)
SA99 : 64KB (32KW)
SA100 : 64KB (32KW)
SA101 : 64KB (32KW)
SA102 : 64KB (32KW)
SA103 : 64KB (32KW)
SA104 : 64KB (32KW)
SA105 : 64KB (32KW)
SA106 : 64KB (32KW)
SA107 : 64KB (32KW)
SA108 : 64KB (32KW)
SA109 : 64KB (32KW)
SA110 : 64KB (32KW)
SA111 : 64KB (32KW)
SA112 : 64KB (32KW)
SA113 : 64KB (32KW)
SA114 : 64KB (32KW)
SA115 : 64KB (32KW)
SA116 : 64KB (32KW)
SA117 : 64KB (32KW)
SA118 : 64KB (32KW)
SA119 : 64KB (32KW)
SA120 : 64KB (32KW)
SA121 : 64KB (32KW)
SA122 : 64KB (32KW)
SA123 : 64KB (32KW)
SA124 : 64KB (32KW)
SA125 : 64KB (32KW)
SA126 : 64KB (32KW)
SA127 : 64KB (32KW)
SA128 : 64KB (32KW)
SA129 : 64KB (32KW)
SA130 : 64KB (32KW)
SA131 : 64KB (32KW)
SA132 : 64KB (32KW)
SA133 : 64KB (32KW)
SA134 : 8KB (4KW)
SA135 : 8KB (4KW)
SA136 : 8KB (4KW)
SA137 : 8KB (4KW)
SA138 : 8KB (4KW)
SA139 : 8KB (4KW)
SA140 : 8KB (4KW)
SA141 : 8KB (4KW)
Word Mode
200000h
208000h
210000h
218000h
220000h
228000h
230000h
238000h
240000h
248000h
250000h
258000h
260000h
268000h
270000h
278000h
280000h
288000h
290000h
298000h
2A0000h
2A8000h
2B0000h
2B8000h
2C0000h
2C8000h
2D0000h
2D8000h
2E0000h
2E8000h
2F0000h
2F8000h
300000h
308000h
310000h
318000h
320000h
328000h
330000h
338000h
340000h
348000h
350000h
358000h
360000h
368000h
370000h
378000h
380000h
388000h
390000h
398000h
3A0000h
3A8000h
3B0000h
3B8000h
3C0000h
3C8000h
3D0000h
3D8000h
3E0000h
3E8000h
3F0000h
3F8000h
3F9000h
3FA000h
3FB000h
3FC000h
3FD000h
3FE000h
3FF000h
3FFFFFh
MB84VP23481FK-70
• FlexBankTM Architecture
Bank 1
Bank 2
Bank
Splits
Volume
Combination
Volume
Combination
1
8 Mbit
Bank A
56 Mbit
Remainder (Bank B, C, D)
2
24 Mbit
Bank B
40 Mbit
Remainder (Bank A, C, D)
3
24 Mbit
Bank C
40 Mbit
Remainder (Bank A, B, D)
4
8 Mbit
Bank D
56 Mbit
Remainder (Bank A, B, C)
• Example of Virtual Banks Combination
Bank 1
Bank
Splits Volume Combination
Sector Size
Volume
1
8 Mbit
Bank A
8 × 8 Kbyte/4 Kword
+
56 Mbit
15 × 64 Kbyte/32 Kword
2
16 Mbit
Bank A
+
Bank D
16 × 8 Kbyte/4 Kword
+
48 Mbit
30 × 64 Kbyte/32 Kword
3
24 Mbit
Bank B
48 × 64 Kbyte/32 Kword 40 Mbit
4
32 Mbit
Bank A
+
Bank B
8 × 8 Kbyte/4 Kword
+
32 Mbit
63 × 64 Kbyte/32 Kword
Bank 2
Combination
Sector Size
Bank B
+
8 × 8 Kbyte/4 Kword
Bank C
+
+
111 × 64 Kbyte/32 Kword
Bank D
Bank B
+
96 × 64 Kbyte/32 Kword
Bank C
Bank A
+
16 × 8 Kbyte/4 Kword
Bank C
+
+
78 × 64 Kbyte/32 Kword
Bank D
Bank C
8 × 8 Kbyte/4 Kword
+
+
Bank D
63 × 64 Kbyte/32 Kword
Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which
a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,
neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.)
Meanwhile the system would get to read from either Bank C or Bank D.
13
MB84VP23481FK-70
• Simultaneous Operation
Case
1
2
3
4
5
6
7
Bank 1 Status
Read mode
Read mode
Read mode
Read mode
Autoselect mode
Program mode
Erase mode *
Bank 2 Status
Read mode
Autoselect mode
Program mode
Erase mode *
Read mode
Read mode
Read mode
* : By writing erase suspend command on the bank address of sector being erased, the erase operation gets
suspended so that it enables reading from or programming the remaining sectors.
Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank
consists of 4 banks, Bank A, Bank B, Bank C and Bank D. Bank Address (BA) meant to specify each of the
Banks.
14
MB84VP23481FK-70
• Sector Address Tables
Sector Address
Bank
Bank A
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
Bank Address
A21
A20
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address Range
A18
A17
A16
A15
A14
A13
A12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Word Mode
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
(Continued)
15
MB84VP23481FK-70
Sector Address
Bank
Bank B
Sector
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Bank Address
A21
A20
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address Range
A18
A17
A16
A15
A14
A13
A12
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Word Mode
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
(Continued)
16
MB84VP23481FK-70
Sector Address
Bank
Bank C
Sector
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
Bank Address
A21
A20
A19
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address Range
A18
A17
A16
A15
A14
A13
A12
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Word Mode
200000h to 207FFFh
208000h to 20FFFFh
210000h to 217FFFh
218000h to 21FFFFh
220000h to 227FFFh
228000h to 22FFFFh
230000h to 237FFFh
238000h to 23FFFFh
240000h to 247FFFh
248000h to 24FFFFh
250000h to 257FFFh
258000h to 25FFFFh
260000h to 267FFFh
268000h to 26FFFFh
270000h to 277FFFh
278000h to 27FFFFh
280000h to 287FFFh
288000h to 28FFFFh
290000h to 297FFFh
298000h to 29FFFFh
2A0000h to 2A7FFFh
2A8000h to 2AFFFFh
2B0000h to 2B7FFFh
2B8000h to 2BFFFFh
2C0000h to 2C7FFFh
2C8000h to 2CFFFFh
2D0000h to 2D7FFFh
2D8000h to 2DFFFFh
2E0000h to 2E7FFFh
2E8000h to 2EFFFFh
2F0000h to 2F7FFFh
2F8000h to 2FFFFFh
300000h to 307FFFh
308000h to 30FFFFh
310000h to 317FFFh
318000h to 31FFFFh
320000h to 327FFFh
328000h to 32FFFFh
330000h to 337FFFh
338000h to 33FFFFh
340000h to 347FFFh
348000h to 34FFFFh
350000h to 357FFFh
358000h to 35FFFFh
360000h to 367FFFh
368000h to 36FFFFh
370000h to 377FFFh
378000h to 37FFFFh
(Continued)
17
MB84VP23481FK-70
(Continued)
Sector Address
Bank
Bank D
18
Sector
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
Bank Address
A21
A20
A19
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address Range
A18
A17
A16
A15
A14
A13
A12
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
Word Mode
380000h to 387FFFh
388000h to 38FFFFh
390000h to 397FFFh
398000h to 39FFFFh
3A0000h to 3A7FFFh
3A8000h to 3AFFFFh
3B0000h to 3B7FFFh
3B8000h to 3BFFFFh
3C0000h to 3C7FFFh
3C8000h to 3CFFFFh
3D0000h to 3D7FFFh
3D8000h to 3DFFFFh
3E0000h to 3E7FFFh
3E8000h to 3EFFFFh
3F0000h to 3F7FFFh
3F8000h to 3F8FFFh
3F9000h to 3F9FFFh
3FA000h to 3FAFFFh
3FB000h to 3FBFFFh
3FC000h to 3FCFFFh
3FD000h to 3FDFFFh
3FE000h to 3FEFFFh
3FF000h to 3FFFFFh
MB84VP23481FK-70
• Sector Group Addresses
Sector Group
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
A21
0
0
0
0
0
0
0
0
A20
0
0
0
0
0
0
0
0
A19
0
0
0
0
0
0
0
0
A18
0
0
0
0
0
0
0
0
A17
0
0
0
0
0
0
0
0
SGA8
0
0
0
0
0
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
SGA25
SGA26
SGA27
SGA28
SGA29
SGA30
SGA31
SGA32
SGA33
SGA34
SGA35
SGA36
SGA37
SGA38
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
SGA39
1
1
1
1
1
SGA40
SGA41
SGA42
SGA43
SGA44
SGA45
SGA46
SGA47
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A16
0
0
0
0
0
0
0
0
0
1
1
A15
0
0
0
0
0
0
0
0
1
0
1
A14
0
0
0
0
1
1
1
1
A13
0
0
1
1
0
0
1
1
A12
0
1
0
1
0
1
0
1
Sectors
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
X
X
X
SA8 to SA10
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA11 to SA14
SA15 to SA18
SA19 to SA22
SA23 to SA26
SA27 to SA30
SA31 to SA34
SA35 to SA38
SA39 to SA42
SA43 to SA46
SA47 to SA50
SA51 to SA54
SA55 to SA58
SA59 to SA62
SA63 to SA66
SA67 to SA70
SA71 to SA74
SA75 to SA78
SA79 to SA82
SA83 to SA86
SA87 to SA90
SA91 to SA94
SA95 to SA98
SA99 to SA102
SA103 to SA106
SA107 to SA110
SA111 to SA114
SA115 to SA118
SA119 to SA122
SA123 to SA126
SA127 to SA130
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
SA131 to SA133
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
19
MB84VP23481FK-70
• Flash Memory Autoselect Codes
Type
A21 to A12
A6
A5
A4
A3
A2
A1
A0
Code (HEX)
Manufacture’s Code
BA
VIL
x
x
VIL
VIL
VIL
VIL
04h
Device Code
BA
VIL
x
x
VIL
VIL
VIL
VIH
227Eh
BA
VIL
x
x
VIH
VIH
VIH
VIL
2215h
BA
VIL
x
x
VIH
VIH
VIH
VIH
2201h
Sector
Group
Addresses
VIL
VIH
VIH
VIH
VIL
VIH
VIL
01h*1
Extended Device Code*2
Sector Group Protection*1
*1:Sector Group can be protected by “Sector Group Protection”, “Extended Sector Group Protection” and
“New Sector Protection (PPB Protection)”.
Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
*2:A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional
codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these
Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh
20
MB84VP23481FK-70
• Flash Memory Command Definitions
Command
Sequence
Second
Bus Fifth Bus
Seventh
Bus
First Bus
Third Bus Fourth
Sixth Bus
Bus
Read/Write Write
Bus
Write Write Cycle
Write
Cycle
Cycle
Write
Cycle
Write Cycle
Cycle
Write Cycle
Cycles
Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset *1
2
XXXh F0h
Read/Reset *1
4
555h
Autoselect
3
Program
RD
—
—
—
—
—
—
—
—
—
—
AAh 2AAh
55h
555h
F0h
RA
RD
—
—
—
—
—
—
555h
AAh 2AAh
55h
(BA)
555h
90h
—
—
—
—
—
—
—
—
4
555h
AAh 2AAh
55h
555h
A0h
PA
PD
—
—
—
—
—
—
Chip Erase
6
555h
AAh 2AAh
55h
555h
80h
555h
AAh 2AAh
55h
555h
10h
—
—
Sector Erase
6
555h
AAh 2AAh
55h
555h
80h
555h
AAh 2AAh
55h
SA
30h
—
—
Program/Erase
Suspend
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
—
—
Program/Erase
Resume
1
BA
30h
—
—
—
—
—
—
—
—
—
—
—
—
Set to Fast Mode
3
555h
55h
555h
20h
—
—
—
—
—
—
—
—
Fast Program *2
2
XXXh A0h
PD
—
—
—
—
—
—
—
—
—
—
Reset from
Fast Mode *2
2
—
—
—
—
—
—
—
—
—
—
Extended Sector
Group Protection*3
4
Query *4
1
(BA)
55h
98h
HiddenROM Entry
3
555h
HiddenROM
Program *5
4
HiddenROM
Exit *5
HiddenROM
Protect *5
Password
Program *7
BA
RA
AAh 2AAh
PA
90h XXXh F0h*6
SGA
60h
SGA
40h
SGA
SD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AAh 2AAh
55h
555h
88h
—
—
—
—
—
—
—
—
555h
AAh 2AAh
55h
555h
A0h (HRA)
PA
PD
—
—
—
—
—
—
4
555h
AAh 2AAh
55h
555h
90h XXXh 00h
—
—
—
—
—
—
6
555h
AAh 2AAh
55h
555h
60h OPBP 68h OPBP 48h XXXh RD(0)
—
—
4
XXXh 60h
555h
AAh 2AAh
55h
(HRBA)
555h
XX0h PD0
—
—
—
—
—
—
XX1h PD1
—
—
—
—
—
—
XX2h PD2
—
—
—
—
—
—
XX3h PD3
—
—
—
—
—
—
38h
Password Unlock
7
555h
AAh 2AAh
55h
555h
28h
XX0h PD0 XX1h PD1 XX2h PD2 XX3h PD3
Password Verify
4
555h
AAh 2AAh
55h
555h
C8h
PWA PWD
—
—
—
—
—
—
(Continued)
21
MB84VP23481FK-70
(Continued)
Command
Sequence
Second
Bus Fifth Bus
Seventh
Bus
First Bus
Third Bus Fourth
Sixth Bus
Bus
Read/Write Write
Bus
Write Write Cycle
Write
Cycle
Cycle
Write
Cycle
Write Cycle
Cycle
Write Cycle
Cycles
Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Password Mode
Locking Bit
Program
6
555h
AAh 2AAh
55h
555h
60h
48h
XXh
RD(0)
—
—
Persistent Protection Mode Locking
Bit Program
6
555h
AAh 2AAh
55h
555h
60h SPML 68h SPML 48h
XXh
RD(0)
—
—
PPB Program
6
555h
AAh 2AAh
55h
555h
60h SA+WP 68h SA+WP 48h
XXh
RD(0)
—
—
PPB Verify
4
555h
AAh 2AAh
55h
555h
90h SA+x02 RD(0)
—
—
—
—
All PPB Erase *8
6
555h
AAh 2AAh
55h
555h
60h SA+WP 60h SA+WP 40h
XXh
RD(0)
—
—
PPB Lock Bit Set
3
555h
AAh 2AAh
55h
555h
78h
—
—
—
—
—
—
—
—
PPB Lock Bit
Verify
4
555h
AAh 2AAh
55h
555h
58h
SA
RD(1)
—
—
—
—
—
—
DPB Write
4
555h
AAh 2AAh
55h
555h
48h
SA
X1h
—
—
—
—
—
—
DPB Erase
4
555h
AAh 2AAh
55h
555h
48h
SA
X0h
—
—
—
—
—
—
DPB Verify
4
555h
AAh 2AAh
55h
555h
58h
SA
RD(0)
—
—
—
—
—
—
PL
68h
PL
—
—
Legend:
RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector
BA = Bank Address
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
SGA = Sector group address to be protected. Set sector group address and (A6, A5, A4, A3, A2, A1, A0)
= (0, 1, 1, 1, 0, 1, 0)
SD = Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
HRA = Address of the HiddenROM area (000000h to 00007Fh)
HRBA = Bank Address of the HiddenROM area (A21 = A20 = A19 = VIL)
RD(0) = DQ0 data, RD(1) = DQ1 data. PPB Lock bit is read on DQ1 and PPB or DPB are read on DQ0.
If set, DQ0/DQ1=1. If cleared, DQ0/DQ1=0.
OPBP = (A6, A5, A4, A3, A2, A1, A0) is (X, 0, 1, 1, 0, 1, 0)
SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or
A6 = 0 for locked
PWA/PWD = Password Address/Password Data
PL =
(A6, A5, A4, A3, A2, A1, A0) is (X, 0, 0, 1, 0, 1, 0)
SPML = (A6, A5, A4, A3, A2, A1, A0) is (X, 0, 1, 0, 0, 1, 0)
WP = (A6, A5, A4, A3, A2, A1, A0) is (X, 1, 1, 1, 0, 1, 0)
22
MB84VP23481FK-70
*1: Both of these reset commands are equivalent.
*2: This command is valid during Fast Mode.
*3: This command is valid while RESET = VID.
*4: The valid addresses are A6 to A0.
*5: This command is valid during HiddenROM mode.
*6: The data “00h” is also acceptable.
*7: Data before fourth cycle also need to be programmed repearting from first cycle to third cycle.
*8: RD(0) of the sixth cycle shows PPB erase status. When RD(0) is "1", programming must be repeated
from the beginning of first cycle to the fourth cycle; both fifth and the sixth validate full completion of erase.
Notes : • Address bits A21 to A11 = X = “H” or “L” for all address commands except for
PA, SA, BA, SGA, OPBP, SLA, PWA, PL, SPML, WP.
• Bus operations are defined in "■ DEVICE BUS OPERATIONS".
• The system should generate the following address patterns:
555h or 2AAh to addresses A10 to A0
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• Command combinations not described in Command Definitions table are illegal.
23
MB84VP23481FK-70
2. AC Characteristics
• Read Only Operations Characteristics
Symbol
Value*
Parameter
Condition
JEDEC
Standard
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
tACC
Page Read Cycle Time
—
tPRC
Page Address to Output Delay
—
tPACC
Chip Enable to Output Delay
tELQV
tCE
Output Enable to Output Delay
tGLQV
tOE
Chip Enable to Output High-Z
tEHQZ
Output Enable to Output High-Z
Output Hold Time From Address, CEf or
OE,
Whichever Occurs First
RESET Pin Low to Read Mode
Max
65
—
ns
—
65
ns
25
—
ns
CEf = VIL
OE = VIL
—
25
ns
OE = VIL
—
65
ns
—
—
25
ns
tDF
—
—
25
ns
tGHQZ
tDF
—
—
25
ns
tAXQX
tOH
—
4
—
ns
—
tREADY
—
—
20
ns
—
CEf = VIL
OE = VIL
—
* : Test Conditions: Output Load:VCCf =2.7 V to 3.1 V:1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCf
Timing measurement reference level
Input: 0.5 × VCCf
Output: 0.5 × VCCf
24
Unit
Min
MB84VP23481FK-70
• Write (Erase/Program) Operations
Parameter
Symbol
Value
Unit
JEDEC
Standard
Min
Typ
Max
Write Cycle Time
tAVAV
tWC
65
—
—
ns
Address Setup Time
tAVWL
tAS
0
—
—
ns
—
tASO
12
—
—
ns
tWLAX
tAH
45
—
—
ns
—
tAHT
0
—
—
ns
Data Setup Time
tDVWH
tDS
35
—
—
ns
Data Hold Time
tWHDX
tDH
0
—
—
ns
—
tOEH
0
—
—
ns
10
—
—
ns
CE High During Toggle Bit Polling
—
tCEPH
20
—
—
ns
OE High During Toggle Bit Polling
—
tOEPH
20
—
—
ns
Read Recover Time Before Write
tGHWL
tGHWL
0
—
—
ns
Read Recover Time Before Write
tGHEL
tGHEL
0
—
—
ns
CE Setup Time
tELWL
tCS
0
—
—
ns
WE Setup Time
tWLEL
tWS
0
—
—
ns
CE Hold Time
tWHEH
tCH
0
—
—
ns
WE Hold Time
tEHWH
tWH
0
—
—
ns
Write Pulse Width
tWLWH
tWP
35
—
—
ns
CE Pulse Width
tELEH
tCP
35
—
—
ns
Write Pulse Width High
tWHWL
tWPH
30
—
—
ns
CE Pulse Width High
tEHEL
tCPH
30
—
—
ns
Word Programming Operation
tWHWH1
tWHWH1
—
6
—
µs
Sector Erase Operation*1
tWHWH2
tWHWH2
—
0.5
—
s
VCC Setup Time
—
tVCS
50
—
—
µs
Rise Time to VACC*2
—
tVACCR
500
—
—
ns
Address Setup Time to OE Low During
Toggle Bit Polling
Address Hold Time
Address Hold Time from CEf or OE High
During Toggle Bit Polling
Output Enable
Hold Time
Read
Toggle and Data Polling
(Continued)
25
MB84VP23481FK-70
(Continued)
Parameter
Symbol
Unit
JEDEC
Standard
Min
Typ
Max
Recover Time from RY/BY
—
tRB
0
—
—
ns
RESET Pulse Width
—
tRP
500
—
—
ns
RESET High Level Period Before Read
—
tRH
200
—
—
ns
Program/Erase Valid to RY/BY
Delay
—
tBUSY
—
—
90
ns
Delay Time from Embedded Output Enable
—
tEOE
—
—
65
ns
Erase Time-out Time
—
tTOW
50
—
—
ns
Erase Suspend Transition Time
—
tSPD
—
—
20
ns
*1 : This does not include the preprogramming time.
*2 : This timing is for Accelerated Program operation.
26
Value
MB84VP23481FK-70
• Read Operation Timing Diagram
tRC
Address
Address Stable
tACC
CEf
tOE
tDF
OE
tOEH
WE
tCE
Outputs
High-Z
tOH
Output Valid
High-Z
27
MB84VP23481FK-70
• Page Read Operation Timing Diagram
A21 to A3
Same page Addresses
A2 to A0
t
t
OEH
28
t
t
RC
Ac
t
PRC
PRC
Ad
Ae
t
t
PRC
Af
t
PRC
Ag
t
PRC
Ah
t
PRC
PRC
ACC
CE
t
OE
t
WE
Output
Ab
t
CEf
OE
Aa
High-Z
t
PACC
t
PACC
t
PACC
t
OH
t
OH
t
OH
Da
Db
Dc
t
t
PACC
OH
Dd
t
PACC
t
PACC
t
PACC
t
OH
t
OH
t
OH
De
Df
Dg
t
Dh
OH
DF
MB84VP23481FK-70
• Hardware Reset/Read Operation Timing Diagram
tRC
Address
Address Stable
tACC
CEf
tRH
tRP
tRH
tCE
RESET
tOH
Outputs
High-Z
Outputs Valid
29
MB84VP23481FK-70
• Alternate WE Controlled Program Operation Timing Diagram
3rd Bus Cycle
Data Polling
555h
Address
PA
tWC
tAS
PA
tRC
tAH
CEf
tCH
tCS
tCE
OE
tGHWL
tWP
tWPH
tOE
tWHWH1
WE
tDS
Data
A0h
tDF
tDH
PD
DQ7
DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
30
tOH
DOUT
MB84VP23481FK-70
• Alternate CE Controlled Program Operation Timing Diagram
3rd Bus Cycle
Address
Data Polling
PA
555h
tWC
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CEf
tDS
Data
A0h
tDH
PD
DQ7
DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
31
MB84VP23481FK-70
• Chip/Sector Erase Operation Timing Diagram
Address
2AAh
555h
tWC
tAS
555h
555h
2AAh
SA*
tAH
CEf
tCS
tCH
OE
tGHWL
tWP
tWPH
tDS
tDH
WE
AAh
Data
30h for Sector Erase
55h
tVCS
VCCf
* : SA is the sector address for Sector Erase.
32
80h
AAh
55h
10h/
30h
MB84VP23481FK-70
• Data Polling during Embedded Algorithm Operation Timing Diagram
CEf
t CH
t OE
t DF
OE
t OEH
WE
t CE
*
DQ7
Data
DQ7 =
Valid Data
DQ7
High-Z
t WHWH1 or 2
DQ6 to DQ0
Data
DQ6 to DQ0 = Output Flag
DQ6 to DQ0
Valid Data
High-Z
t EOE
* : DQ7 = Valid Data (The device has completed the Embedded operation).
33
MB84VP23481FK-70
• AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
Address
tAHT tASO
tAHT tAS
CEf
tCEPH
WE
tOEPH
tOEH
tOEH
OE
tDH
DQ 6/DQ2
tOE
Toggle
Data
Data
tCE
Toggle
Data
Toggle
Data
*
tBUSY
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation).
34
Stop
Toggling
Output
Valid
MB84VP23481FK-70
• Bank-to-Bank Read/Write Timing Diagram
Address
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
BA1
BA2
(555h)
BA1
BA2
(PA)
BA1
BA2
(PA)
tAS
tACC
tAH
tAS
tAHT
tCE
CEf
tOE
tCEPH
OE
tGHWL
tDF
tOEH
tWP
WE
tDS
DQ
Valid
Output
tDH
Valid
Intput
(A0h)
tDF
Valid
Output
Valid
Intput
(PD)
Valid
Output
Status
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1 : Address corresponding to Bank 1
BA2 : Address corresponding to Bank 2
35
MB84VP23481FK-70
• DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
WE
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE
Note : DQ2 is read from the erase-suspended sector.
• RY/BY Timing Diagram during Program/Erase Operation Timing Diagram
CEf
Rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
36
Erase
Complete
MB84VP23481FK-70
• RESET, RY/BY Timing Diagram
WE
RESET
tRP
tRB
RY/BY
tREADY
37
MB84VP23481FK-70
• Temporary Sector Group Unprotection Timing Diagram
VCCf
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CEf
WE
tVLHT
Program Command Sequence
RY/BY
Unprotection period
38
tVLHT
MB84VP23481FK-70
• Extended Sector Group Protection Timing Diagram
VCCf
tVCS
RESET
tVLHT
tVIDR
tWC
Address
tWC
SGAX
SGAX
SGAY
A6, A2, A0
A5, A4,
A3, A1
CEf
OE
TIME-OUT
tWP
WE
Data
60h
60h
40h
01h
60h
tOE
SGAX : Sector Group Address to be protected
SGAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
39
MB84VP23481FK-70
• Accelerated Program Timing Diagram
VCCf
tVACCR
tVCS
tVLHT
VACC
VIH
ACC
CEf
WE
tVLHT
Program Command Sequence
Acceleration period
40
tVLHT
MB84VP23481FK-70
3. Erase and Programming Performance
Limits
Parameter
Unit
Comments
2.0
s
Excludes programming time
prior to erasure
6
100
µs
Excludes system-level
overhead
—
25.2
95
s
Excludes system-level
overhead
100,000
—
—
cycle
Min
Typ
Max
Sector Erase Time
—
0.5
Word Programming Time
—
Chip Programming Time
Erase/Program Cycle
Note
—
Typical Erase conditions TA = + 25°C, VCCf = 2.9 V
Typical Program conditions TA = + 25°C, VCCf = 2.9 V, Data = Checker
41
MB84VP23481FK-70
■ 32 M FCRAM CHARACTERISTICS for MCP
1. Power Down (32M Page Mode FCRAM)
• Power Down (32M Page mode FCRAM)
The Power Down is to enter low power idle state when CE2r stays Low.
The 32M page mode FCRAM has four power down mode, Sleep, 4M Partial, 8M Partial, and 16M Partial.
These can be programmed by series of read/write operation. Each mode has following features.
Mode
Data Retention
Retention Address
Sleep (default)
No
N/A
4M Partial
4M bit
00000h to 3FFFFh
8M Partial
8M bit
00000h to 7FFFFh
16M Partial
16M bit
00000h to FFFFFh
The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2r is brought
to Low for Power Down. It is not required to program to Sleep mode after power-up.
• Power Down Program Sequence (32M Page mode FCRAM)
The program requires total 6 read/write operation with unique address and data. Between each read/write
operation requires that device be in standby mode. Following table shows the detail sequence.
Cycle #
Operation
Address
Data
1st
Read
1FFFFFh (MSB)
Read Data (RDa)
2nd
Write
1FFFFFh
RDa
3rd
Write
1FFFFFh
RDa
4th
Write
1FFFFFh
0000h
5th
Write
1FFFFFh
Data Key
6th
Read
Address Key
Read Data (RDb)
The first cycle is to read from most significant address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle. If the third cycle is written into
the different address, the program is cancelled and the data written by the second or third cycle is valid as a
normal write operation.
The forth and fifth cycle is to write the data key for program. The data of forth cycle must be all 0’s and data of
fifth cycle is a data key for mode selection. If the forth cycle is written into different address, the program is also
cancelled.
The last cycle is to read from specific address key for mode selection. The both data key written by fifth cycle
and address key must be the same mode for proper programming.
Once this program sequence is performed from a Partial mode to other Partial mode, the write data may be lost.
So, it should perform this program prior to regular read/write operation if Partial mode is used.
42
MB84VP23481FK-70
• Address Key (32M Page mode FCRAM)
The address key has following format.
Mode
Address
A20
A19
A18 to A0
Binary
Sleep (default)
1
1
1
1FFFFFh
4M Partial
0
1
1
0FFFFFh
8M Partial
1
0
1
17FFFFh
16M Partial
0
0
1
07FFFFh
• Data Key (32M Page mode FCRAM)
The data key has following format.
Mode
Data
DQ15 to DQ8
DQ7 to DQ2
DQ1
DQ0
Sleep (default)
0
0
1
1
4M Partial
0
0
1
0
8M Partial
0
0
0
1
16M Partial
0
0
0
0
The upper byte of data code may be ignored and it is just for recommendation to write 0’s to upper byte for future
compatibility.
43
MB84VP23481FK-70
2. AC Characteristics
• READ OPERATION (32M Page mode FCRAM)
Value
Parameter
Symbol
Min
Max
Unit
Remarks
Read Cycle Time
tRC
70
1000
ns
*1, *2
CE1r Access Time
tCE
—
70
ns
*3
OE Access Time
tOE
—
40
ns
*3
Address Access Time
tAA
—
70
ns
*3, *5
LB / UB Access Time
tBA
—
30
ns
*3
Page Address Access Time
tPAA
—
18
ns
*3, *6
Page Read Cycle Time
tPRC
25
1000
ns
*1, *6, *7
Output Data Hold Time
tOH
5
—
ns
*3
CE1r Low to Output Low-Z
tCLZ
3
—
ns
*4
OE Low to Output Low-Z
tOLZ
0
—
ns
*4
LB / UB Low to Output Low-Z
tBLZ
0
—
ns
*4
CE1r High to Output High-Z
tCHZ
—
20
ns
*4
OE High to Output High-Z
tOHZ
—
20
ns
*4
LB / UB High to Output High-Z
tBHZ
—
20
ns
*4
Address Setup Time to CE1r Low
tASC
–5
—
ns
Address Setup Time to OE Low
tASO
10
—
ns
Address Invalid Time
tAX
—
10
ns
*5, *8
Page Address Invalid Time
tAXP
—
10
ns
*6, *8
Address Hold Time from CE1r High
tCHAH
–5
—
ns
*9
Address Hold Time from OE High
tOHAH
–5
—
ns
tCP
15
—
ns
CE1r High Pulse Width
*1 : Maximum value is applicable if CE1r is kept at Low without change of address input of A20 to A3.
If needed by system operation, please contact local FUJITSU representative for the relaxation of 1µs limitation.
*2 : Address should not be changed within minimum tRC.
*3 : The output load 30 pF.
*4 : The output load 5 pF without any other load.
*5 : Applicable to A20 to A3 when CE1r is kept at Low.
*6 : Applicable only to A2, A1 and A0 when CE1r is kept at Low for the page address access.
*7 : In case Page Read Cycle is continued with keeping CE1r stays Low, CE1r must be brought to High within 4 µs.
In other words, Page Read Cycle must be closed within 4 µs.
*8 : Applicable when at least two of address inputs among applicable are switched from previous state.
*9 : tRC(Min) and tPRC(Min) must be satisfied.
44
MB84VP23481FK-70
• WRITE OPERATION (32M Page mode FCRAM)
Value
Parameter
Symbol
Min
Max
Unit
Notes
Write Cycle Time
tWC
70
1000
ns
*1, *2
Address Setup Time
tAS
0
—
ns
*2
CE1r Write Pulse Width
tCW
45
—
ns
*3
WE Write Pulse Width
tWP
45
—
ns
*3
LB / UB Write Pulse Width
tBW
45
—
ns
*3
CE1r Write Recovery Time
tWRC
15
—
ns
*4
WE Write Recovery Time
tWR
15
1000
ns
*4
LB / UB Write Recovery Time
tBR
15
1000
ns
*4
Data Setup Time
tDS
20
—
ns
Data Hold Time
tDH
0
—
ns
Address Invalid Time after Write
tAXW
—
10
ns
*5
OE High to CE1r Low Setup Time for
Write
tOHCL
–5
—
ns
*6
OE High to Address Setup Time
for Write
tOES
0
—
ns
*7
LB and UB Write Pulse Overlap
tBWO
20
—
ns
CE1r High Pulse Width
tCP
15
—
ns
*1 : Maximum value is applicable if CE1r is kept at Low without any address change. If the relaxation is needed by
system operation, please contact local FUJITSU representative for the relaxation of 1 µs limitation.
*2 : Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time
(tWRC, tWR or tBR).
*3 : Write pulse is defined from High to Low transition of CE1r, WE, or LB / UB, whichever occurs last.
*4 : Write recovery is defined from Low to High transition of CE1r, WE, or LB / UB, whichever occurs first.
*5 : Applicable to any address change when CE1r stays Low.
*6 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5ns
after CE1r is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met.
*7 : If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the
same time or before new address valid. Once read cycle is initiated, new write pulse should be input after
minimum tRC is met.
45
MB84VP23481FK-70
• POWER DOWN PARAMETERS (32M Page mode FCRAM)
Parameter
Symbol
Value
Min
Max
Unit
Remarks
CE2r Low Setup Time for Power Down Entry
tCSP
10
—
ns
CE2r Low Hold Time after Power Down Entry
tC2LP
70
—
ns
CE1r High Hold Time following CE2r High
after Power Down Exit [SLEEP mode only]
tCHH
300
—
µs
*1
CE1r High Hold Time following CE2r High
after Power Down Exit [not in SLEEP mode]
tCHHP
1
—
µs
*2
CE1r High Setup Time following CE2r High
after Power Down Exit
tCHS
0
—
ns
*1 : Applicable also to power-up.
*2 : Applicable when 4M, 8M, and 16M Partial mode is programmed.
• OTHER TIMING PARAMETERS (32M Page mode FCRAM)
Parameter
Symbol
Value
Min
Max
Unit
CE1r High to OE Invalid Time for Standby Entry
tCHOX
10
—
ns
CE1r High to WE Invalid Time for Standby Entry
tCHWX
10
—
ns
CE1r High Hold Time following CE2r High after Power-up
tCHH
300
—
µs
tT
1
25
ns
Input Transition Time
Remarks
*1
*2
*1 : Some data might be written into any address location if tCHWX(Min) is not satisfied.
*2 : The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns,
it may violate AC specification of some timing parameters.
• AC TEST CONDITIONS (32M Page mode FCRAM)
Description
Symbol
Test Setup
Value
Unit
Input High Level
VIH
—
VCCr
V
Input Low Level
VIL
—
VSS
V
VREF
—
VCCr × 0.5
V
5
ns
Input Timing Measurement Level
Input Transition Time
46
tT
Between VIL and VIH
Remarks
MB84VP23481FK-70
• READ Timing #1 (Basic Timing) (32M Page FCRAM)
tRC
Address Valid
Address
tASC
tCHAH
tCE
CE1r
tASC
tCP
tCHZ
tOE
OE
tOHZ
tBA
LB / UB
tBHZ
tBLZ
tOLZ
DQ
(Output)
tOH
tCLZ
Valid Data Output
Note : CE2r and WE must be High for entire read cycle.
47
MB84VP23481FK-70
• READ Timing #2 (OE & Address Access) (32M Page FCRAM)
tAx
tRC
Address
Address Valid
Address Valid
tAA
CE1r
tRC
tAA
tOHAH
Low
tASO
tOE
OE
LB / UB
tOHZ
tOLZ
tOH
tOH
DQ
(Output)
Valid Data Output
Note : CE2r and WE must be High for entire read cycle.
48
Valid Data Output
MB84VP23481FK-70
• READ Timing #3 (LB / UB Byte Access) (32M Page FCRAM)
tAX
tRC
Address
tAx
Address Valid
tAA
CE1r, OE
Low
tBA
tBA
LB
tBA
UB
tBHZ
tBHZ
tOH
tBLZ
tBLZ
tOH
DQ7 to DQ0
(Output)
Valid Data
Output
Valid Data
Output
tBLZ
tBHZ
tOH
DQ15 to DQ8
(Output)
Valid Data Output
Note : CE2r and WE must be High for entire read cycle.
49
MB84VP23481FK-70
• READ Timing #4 (Page Address Access after CE1r Control Access) (32M Page FCRAM)
tRC
Address
(A20 to A3)
Address Valid
tRC
Address
(A2 to A0)
Address Valid
tPRC
tPRC
Address
Valid
Address
Valid
tPAA
tPAA
tASC
tPRC
Address
Valid
tPAA
tCHAH
CE1r
tCE
tCHZ
OE
LB / UB
tCLZ
tOH
tOH
tOH
DQ
(Output)
Valid Data Output
(Normal Access)
Note : CE2r, and WE must be High for entire read cycle.
50
Valid Data Output
(Page Access)
tOH
MB84VP23481FK-70
• READ Timing #5 (Random and Page Address Access) (32M Page FCRAM)
tRC
Address
(A20 to A3)
tAX
Address
(A2 to A0)
tPRC
tPAA
tAA
tPRC
tRC
Address
Valid
Address
Valid
tAx
Address Valid
Address Valid
tRC
CE1r
tRC
Address
Valid
Address
Valid
tAA
tPAA
Low
tASO
tOE
OE
tBA
LB / UB
DQ
(Output)
tOLZ
tBLZ
tOH
Valid Data Output
(Normal Access)
tOH
tOH
tOH
Valid Data Output
(Page Access)
Note : CE2r, and WE must be High for entire read cycle.
Either or both LB and UB must be Low when both CE1r and OE are Low.
51
MB84VP23481FK-70
• WRITE Timing #1 (Basic Timing) (32M Page FCRAM)
tWC
Address
Address Valid
tAS
tWRC
tCW
tAS
CE1r
tAS
tWR
tWP
tAS
WE
tAS
tBR
tBW
LB, UB
tOHCL
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note : CE2r must be High for write cycle.
52
tAS
MB84VP23481FK-70
• WRITE Timing #2 (WE Control) (32M Page FCRAM)
tWC
tWC
Address Valid
Address
Address Valid
tOHAH
CE1r
Low
tAS
tWP
tWR
tAS
tWP
tWR
WE
LB, UB
tOES
OE
tOHZ
tDS
tDH
tDS
tDH
DQ
(Input)
Valid Data Input
Valid Data Input
Note : CE2r must be High for write cycle.
53
MB84VP23481FK-70
• WRITE Timing #3-1 (WE / LB / UB Byte Write Control) (32M Page FCRAM)
tWC
Address Valid
Address
CE1r
tWC
Address Valid
Low
tAS
tWP
tAS
tWP
WE
tBR
LB
tBR
UB
tDS
tDH
DQ7 to DQ0
(Input)
Valid Data Input
tDS
tDH
DQ15 to DQ8
(Input)
Valid Data Input
Note : CE2r must be High for write cycle.
54
MB84VP23481FK-70
• WRITE Timing #3-2 (WE / LB / UB Byte Write Control) (32M Page FCRAM)
tWC
Address Valid
Address
CE1r
tWC
Address Valid
Low
tWR
tWR
WE
tAS
tBW
LB
tAS
tBW
UB
tDS
tDH
DQ7 to DQ0
(Input)
Valid Data Input
tDS
tDH
DQ15 to DQ8
(Input)
Valid Data Input
Note : CE2r must be High for write cycle.
55
MB84VP23481FK-70
• WRITE Timing #3-3 (WE / LB / UB Byte Write Control) (32M Page FCRAM)
tWC
Address Valid
Address
CE1r
tWC
Address Valid
Low
WE
tAS
tBW
tBR
LB
tAS
tBW
tBR
UB
tDS
tDH
DQ7 to DQ0
(Input)
Valid Data Input
tDS
tDH
DQ15 to DQ8
(Input)
Valid Data Input
Note : CE2r must be High for write cycle.
56
MB84VP23481FK-70
• WRITE Timing #3-4 (WE / LB / UB Byte Write Control) (32M Page FCRAM)
tWC
Address Valid
Address
CE1r
tWC
Address Valid
Low
WE
tAS
tBW
tBR
tAS
tBW
tBR
LB
tBWO
tDS
DQ7 to DQ0
(Input)
tDH
tDS
Valid
Data Input
tAS
tBW
tDH
Valid
Data Input
tBR
tAS
tBWO
tBW
tBR
UB
tDS
DQ15 to DQ8
(Input)
Valid
Data Input
tDH
tDS
tDH
Valid
Data Input
Note : CE2r must be High for write cycle.
57
MB84VP23481FK-70
• READ / WRITE Timing #1-1 (CE1r Control) (32M Page FCRAM)
tWC
Address
tRC
WRITE Address
tCHAH
tAS
READ Address
tWRC
tASC
tCW
tCE
tCHAH
CE1r
tCP
tCP
WE
UB, LB
tOHCL
OE
tCHZ
tOH
tDS
tDH
DQ
READ Data Output
WRITE Data Input
Note : Write address is valid from either CE1r or WE of last falling edge.
58
tCLZ
tOH
MB84VP23481FK-70
• READ / WRITE Timing #1-2 (CE1r / WE / OE Control) (32M Page FCRAM)
tWC
Address
tRC
WRITE Address
tCHAH
tAS
READ Address
tWR
tASC
tCHAH
tCE
CE1r
tCP
tCP
tWP
WE
UB, LB
tOHCL
tOE
OE
tCHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
READ Data Output
WRITE Data Input
READ Data Output
Note : OE can be Low fixed in write operation under CE1r control RD-WR-RD operation.
59
MB84VP23481FK-70
• READ / WRITE Timing #2 (OE, WE Control) (32M Page FCRAM)
tWC
Address
tRC
WRITE Address
READ Address
tAA
tOHAH
CE1r
tOHAH
Low
tAS
tWR
tWP
WE
tOES
UB, LB
tASO
tOE
OE
tOHZ
tOH
tOHZ
tDS
tDH
tOLZ
tOH
DQ
READ Data Output
WRITE Data Input
Note : CE1r can be tied to Low for WE and OE controlled operation.
When CE1r is tied to Low, output is exclusively controlled by OE.
60
READ Data Output
MB84VP23481FK-70
• READ / WRITE Timing #3 (OE, WE, LB, UB Control) (32M Page FCRAM)
tWC
Address
tRC
WRITE Address
READ Address
tAA
tOHAH
CE1r
tOHAH
Low
WE
tOES
tAS
tBW
tBR
tBA
UB, LB
tASO
tBHZ
OE
tBHZ
tOH
tDS
tDH
tBLZ
tOH
DQ
READ Data Output
WRITE Data Input
READ Data Output
Note : CE1r can be tied to Low for WE and OE controlled operation.
When CE1r is tied to Low, output is exclusively controlled by OE.
61
MB84VP23481FK-70
• POWER-UP Timing (32M Page FCRAM)
CE1r
tCHH
CE2r
VCCr
VCCr Min
0V
Note : The tCHH specifies after VCCr reaches specified minimum level and applicable both CE1r and CE2r.
• POWER DOWN Entry and Exit Timing
CE1r
tCHS
CE2r
tCSP
tC2LP
tCHH (tCHHP)
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Note : This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied
and Power-Down program was not performed prior to this reset.
• Standby Entry Timing after Read or Write (32M Page FCRAM)
CE1r
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode.
If either of timing is not satisfied, it takes tRC (Min) period for Standby mode from CE1r Low to High transition.
62
MB84VP23481FK-70
• POWER DOWN PROGRAM Timing (32M Page FCRAM)
Address
tRC
tWC
tWC
MSB*1
MSB*1
MSB*1
tCP
tCP
tWC
tWC
MSB*1
tCP
tRC
MSB*1
tCP
Key*2
tCP
tCP*4
CE1r
OE
WE
LB, UB
DQ*3
RDa
Cycle #1
RDa
Cycle #2
RDa
Cycle #3
00
Cycle #4
Key*3
Cycle #5
RDb
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #5.
The address key must confirm the format specified in “■ 32 M FCRAM CHARACTERISTICS for MCP 1. Power
Down Program Timing (32 M Page FCRAM) ”. If not, the operation and data are not guaranteed.
*2 : The data key must confirm the format specified in “■ 32 M FCRAM CHARACTERISTICS for MCP 1. Power
Down Program Timing (32 M Page FCRAM) ”. If not, the operation and data are not guaranteed.
*3 : After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation.
63
MB84VP23481FK-70
■ PIN CAPACITANCE
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
Input Capacitance
CIN
VIN = 0

11.0
14.0
pF
Output Capacitance
COUT
VOUT = 0

12.0
16.0
pF
Control Pin Capacitance
CIN2
VIN = 0

14.0
16.0
pF
WP/ACC Pin Capacitance
CIN3
VIN = 0

21.5
26.0
pF
Note: Test conditions TA = + 25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of package create acute angles.
■ CAUTION
• The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when
autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET.
• Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group
Protection” command.
64
MB84VP23481FK-70
■ ORDERING INFORMATION
MB84VP23481
FK
-70
PBS
Package Type
PBS = 65-ball FBGA
Speed Option
Device Revision
Device Number/Description
64Mega-bit (2M × 16-bit + 2M × 16-bit) Dual Operation Page Flash Memory
3.0V-only Read, Program, and Erase
32Mega-bit(2M × 16-bit) Mobile FCRAM
65
MB84VP23481FK-70
■ PACKAGE DIMENSION
65-ball plastic FBGA
(BGA-65P-M01)
9.00±0.10(.354±.004)
0.20(.008) S B
+0.15
1.19 –0.10
(Seated height)
+.006
.047 –.004
0.39±0.10
(Stand off)
(.015±.004)
B
0.40(.016)
REF
0.80(.031)
REF
10
0.80(.031)
REF
9
8
7
6
5
4
3
2
1
A
9.00±0.10
(.354±.004)
0.40(.016)
REF
0.10(.004) S
K J H G F E D C B A
INDEX BALL
INDEX-MARK AREA
0.20(.008) S A
S
+0.10
65-Ø0.45 –0.05
+.004
0.08(.003)
M
S A B
65-Ø.018 –.002
0.10(.004) S
C
2001 FUJITSU LIMITED B65001S-c-1-2
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
66
MB84VP23481FK-70
FUJITSU LIMITED
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