FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12550-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89550A Series
MB89557A/558A/P558A/PV550A
■ DESCRIPTION
The MB89550A series is a general-purpose, single-chip microcontroller that features a compact instruction set
and contains a range of peripheral functions including a dual- clock control system, 5-level operating speed control,
LCD controller driver, A/D converter, D/A converter, timer, serial interface, PWM timer, PWC timer, and external
interrupts. The LCD controller driver is particularly suited for simultaneous control of LCD duty drive and static
drive functions.
■ FEATURES
• Range of package options
• LQFP package (0.5 mm pitch)
• TQFP package (0.4 mm pitch)
• High speed operation at low voltage
• Minimum instruction execution time 0.32 µs (for 12.5 MHz oscillation)
• F2MCR-8L CPU core
Instruction set optimized for controller applications
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
(Continued)
■ PACKAGE
100-pin Plastic LQFP
100-pin Plastic TQFP
100-pin Ceramic MQFP
(FPT-100P-M05)
(FPT-100P-M18)
(MQP-100C-P02)
MB89550A Series
(Continued)
• Dual-clock control system
• Main clock 12.5 MHz maximum : (Four speed settings available, oscillation halts in sub-clock mode)
• Sub-clock 32.768 kHz : (Operation clock for sub-clock mode)
• 11 timer systems
• 8/16-bit timer counter 1 (square wave output, 2-channel output switching available)
• 8/16-bit timer counter 2 (square wave output, 2-channel output switching available)
• 16-bit timer counter (also functions as event counter)
• 8-bit PWM timer (8-bit PWM timer × 2 channels or PPG timer × 1 channel, includes event counter function)
• 8-bit PWC timer (8-bit PWC timer × 1 channel)
• 6-bit PPG timer (6-bit PPG timer × 1 channel)
• 21-bit timebase timer
• Clock prescaler (17-bit)
• UART/serial interface
• UART/SIO switching
• UART
• Clock synchronous/asynchronous switching available
• 10-bit A/D converter
• 10-bit A/D × 8 channels
• 8-bit D/A converter
• 8-bit D/A × 2 channels
• External interrupts
• Eight independent inputs can be used for recovery from low-power consumption modes (selection of rising,
falling, or both edge detection functions).
• Eight independent inputs can be used for recovery from low-power consumption modes (L level detection
function included).
• Clock output functions
• High speed clock signal multiplied by 2 available as output from HCLK pin.
• Low speed clock pulse output available from LCLK pin.
• LCD controller driver
• 32SEG × 4COM (maximum 128 pixels)
8 dedicated to segment output only
8 for port or segment use
16 for port, segment, or static use
• Built-in step-up power supply for driving LCD (optionally available)
• Low-power consumption modes (standby modes)
• Stop mode (all oscillations halt in sub-clock mode, current consumption falls to almost zero)
• Sleep mode (the CPU stops to reduce current consumption to approximately 1/3 of normal)
• Clock mode (all operations other than the clock prescaler halt, current consumption is very low)
• Sub clock mode (systems operate on sub-clock signals)
• Maximum 66 I/O ports
• General-purpose I/O ports (N-ch open drain) : 4
• General-purpose I/O ports (N-ch open drain) : 24
• [also function as LCD ports, with restrictions]
• General purpose I/O ports (CMOS) : 38
2
MB89550A Series
■ PRODUCT LINEUP
MB89557A
MB89558A
Parameter
MB89P558A-201
MB89P558A-202
MB89P558A-203
MB89PV550A*-201
MB89PV550A*-202
MB89PV550A*-203
ROM size
48 KB
32 KB
48 KB
RAM size
2 KB
1 KB
2 KB
1 KB
Packages
LQFP100
TQFP100
LQFP100
TQFP100
LQFP100
TQFP100
LQFP100
One-time product
Mask ROM product
Mask ROM product
Evaluation product
Part no.
Classification
Number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
Interrupt processing time
Peripheral Functions
CPU functions
: 136
: 8-bit
: 1 to 3bytes
: 1-, 8-, 16-bits
: 0.32 µs (at 12.5 MHz)
: 2.88 µs (at 12.5 MHz)
Ports
Output-only ports (N-ch open drain)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS)
8/16-bit timer
counter 1
2-channel 8-bit timer/counter operation (also functions as 1-channel 16-bit timer)
with square wave output function
8/16-bit timer
counter 2
2-channel 8-bit timer/counter operation (also functions as 1-channel 16-bit timer)
with square wave output function
16-bit timer
counter
16-bit timer/counter operation, 16-bit event counter operation
PPWM timer
2-channel 8-bit PWM timer operation (also functions as 1-channel PPG timer)
with event counter function
PWC timer
1-channel 8-bit PWC timer operation
6-bit PPG timer
1-channel 6-bit PWM timer operation
LCD controller
driver
Maximum 32SEGÅ~4COM
(some ports provide selection of DUTY drive/STATIC drive/N-ch open drain I/O port functions)
UART
Switchable between UART (with clock synchronous/asynchronous data transfer function)
and SIO (simple serial)
SIO
UART/SIO
Data transfer function for UART/SIO
A/D converter
8-channel 10-bit resolution
D/A converter
2-channel, 8-bit resolution
Clock output
High speed clock multiplied×2, and sub clock output available
Standby modes
Sub clock mode, sleep mode, clock mode, and stop mode
* : The MB89PV550A provides only evaluation functions (functions for use with emulation tools). This model cannot
use piggyback functions (functions for use with E2PROM).
3
MB89550A Series
■ OPTIONS AND CORRESPONDING PRODUCTS
-201 Options
LCD step-up circuit
PORT/SEG
dual-use pin selection
Evaluation model
-202 Options
No step-up circuit
-203 Options
Step-up circuit included
SEG8 to SEG31
: SEG/PORT dual use
SEG8 to SEG31
: SEG/PORT dual use
SEG8 to SEG21
: SEG/PORT dual use
SEG22 to SEG31
: N-ch open drain*1
MB89PV550A-201
MB89PV550A-202
MB89PV550A-203
MB89P558A-202
MB89P558A-203
MB89557A
MB89557A
MB89558A
MB89558A
MB89P558A-201
Model One-time model
type
MB89557A
Mask ROM model*2
MB89558A
*1 : The SEG22-SEG31 pins (N-ch open drain) are not subject to the restriction that input voltage (VIN) must be
less than the voltage at the V3 pin.
*2 : Options may be specified at the time of mask ROM ordering.
■ OSCILLATOR STABILIZATION WAIT TIME SELECTION
The MB89557A/558A allow a selection of default value for oscillator stabilization wait time, to be selected at the
time of mask ROM ordering.
Oscillator stabilization wait time selection
Remarks
214/FCH
4
1.31 ms (at F = 12.5 MHz)
2 /FCH
10.48 ms (at F = 12.5 MHz)
218/FCH
20.97 ms (at F = 12.5 MHz)
17
MB89550A Series
■ DIFFERENCES AMONG PRODUCTS AND PRECAUTIONS FOR MODEL SELECTION
• Package and Model Combinations
Models
MB89PV550A
Package
FPT-100P-M05
(LQFP-100 0.5 mm pitch)
×
FPT-100P-M18
(TQFP-100 0.4 mm pitch)
×
MB89P558A
MB89557A
MB89558A
×
×
MQP-100C-P02
(MQFP-100 0.5 mm pitch)
Note : Compatible with all options (-201/202/203) .
• Memory Space
• When evaluating chips using piggyback evaluators etc., please take note of the differences among products
before making the evaluation.
• Current Consumption
• When operating at low speed, one-time PROM and EPROM products will consume more current than mask
ROM products. However, the current consumption in sleep/stop modes is the same.
• For specific details about each package, see "■ PACKAGE DIMENSIONS".
• For details about power consumption, see "■ ELECTRICAL CHARACTERISTICS" .
• Mask Options
• The available options, and methods of using options, differ according to the model. Be sure to confirm the
options from the "■ MASK OPTIONS" section.
• LCD Drive Step-up Power Circuit
The MB89550A series is available with or without the step-up circuit option as a mask option.
• Power Supply Path
The models in the MB89550A series have two power supply pins, VCC1 and VCC2, with power supply paths that
differ according to the model.
Models
Supply pin
Power supply path
MB89557A/
558A
MB89P558A
MB89PV550A
VCC1
3V power supply pin for internal resource operation, including the CPU.
VCC2
5V power supply pin for input/output ports.
VCC1
VPP pin for on-board writing.
VCC2
V power supply pin for internal resource operation, including the CPU, and for input/
output pins.
VCC1
Internally shut off, operates as input to VCC2 only.
5V power supply pin for internal resource operation, including the CPU, and for input/
output pins.
• Oscillator Startup and Power-on Reset
On the MB89PV550A and MB89P558A, oscillator startup and power-on reset are applied at the rise of the VCC2
input. On the MB89558A and MB89557A, oscillator startup and power-on reset are applied at the rise of the
VCC1 input.
VCC2
5
MB89550A Series
• Wide Register Functions
The space available for use of wide register functions is as follows.
MB89PV550A
2000H to FFFFH
MB89P558A
4000H to FFFFH
MB89558A
4000H to FFFFH
MB89557A
8000H to FFFFH
• The P40, P41, P84, P85 Pins
On the MB889PV550A, an external oscillator signal equivalent to 64 clock pulses is required to initialize the
P40, P41, P84, and P85 pins. Note therefore that at power-on there is an interval in which the values of these
ports is undefined.
On the MB89P558A, MB89558A, and MB89557A, these ports are set to "Hi-Z" status at power-on.
6
MB89550A Series
■ PIN ASSIGNMENTS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P86/EC2/LCLK
P85/TO22
P84/TO21
DVR
DAOUT1
DAOUT2
P31
P30
P27/INT23
P26/INT22
P25/INT21
P24/INT20
P23/PPG1
P22/UCK
P21/UO
P20/UI
P83/INT27
P82/INT26
P81/INT25
VSS
P80/INT24
X1
X0
MODA
X1A
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P75/SEG29
P76/SEG30
P77/SEG31
AVR
AVCC
P07/AN7
P06/AN6
P05/AN5
P04/AN4
P03/AN3
P02/AN2
P01/AN1
P00/AN0
AVSS
P17/INT17
P16/INT16
P15/INT15
P14/INT14
P13/INT13
P12/INT12
P11/INT11
VCC2
P10/INT10
RST
X0A
SEG05
SEG06
SEG07
P50/SEG08
VSS
P51/SEG09
P52/SEG10
P53/SEG11
P54/SEG12
P55/SEG13
P56/SEG14
P57/SEG15
P60/SEG16
P61/SEG17
P62/SEG18
P63/SEG19
P64/SEG20
P65/SEG21
P66/SEG22
P67/SEG23
P70/SEG24
P71/SEG25
P72/SEG26
P73/SEG27
P74/SEG28
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SEG04
SEG03
VCC1
SEG02
SEG01
SEG00
COM3
COM2
COM1
COM0
V3
V2
V1
V0
C0
C1
P47/PWC
P46/SI
P45/SO
P44/SCK
P43/PWM2
P42/PWM1/EC1
P41/TO12/HCLK
P40/TO11/WTO
P87/EC3
(TOP VIEW)
(QFP-100)
7
MB89550A Series
■ PIN DESCRIPTION
Pin
No.
Pin Name
Circuit
Type
1
SEG05
H
2
SEG06
H
3
SEG07
H
4
P50/
SEG08
G
N-ch open drain I/O pin.
Also functions as a segment output pin for LCDC duty drive.
5
VSS
Power supply (GND) pin.
6
P51/
SEG09
7
P52/
SEG10
8
P53/
SEG11
9
P54/
SEG12
G
N-ch open drain I/O pins.
Also function as segment output pins for LCDC duty drive.
10
P55/
SEG13
11
P56/
SEG14
12
P57/
SEG15
13
P60/
SEG16
14
P61/
SEG17
15
P62/
SEG18
16
P63/
SEG19
17
P64/
SEG20
G
18
P65/
SEG21
N-ch open drain I/O pins.
Also function as segment output pins for LCDC duty drive or static drive.
19
P66/
SEG22
20
P67/
SEG23
21
P70/
SEG24
22
P71/
SEG25
Function
Segment output pins for LCDC duty drive.
(Continued)
8
MB89550A Series
Pin
No.
Pin Name
23
P72/
SEG26
24
P73/
SEG27
25
P74/
SEG28
Circuit
Type
Function
G
N-ch open drain I/O pins.
Also function as segment output pins for LCDC duty drive or static drive.
26
P75/
SEG29
27
P76/
SEG30
28
P77/
SEG31
29
AVR
A/D converter reference voltage input pin.
30
AVCC
A/D converter and D/A converter power supply pin.
31
P07/AN7
32
P06/AN6
33
P05/AN5
34
P04/AN4
35
P03/AN3
D
General purpose I/O ports. Also function as analog input pins.
36
P02/AN2
37
P01/AN1
38
P00/AN0
39
AVSS
A/D converter and D/A converter power supply pin (GND).
40
P17/INT17
41
P16/INT16
42
P15/INT15
43
P14/INT14
E
44
P13/INT13
General purpose I/O ports.
Also function as external interrupt 1 input pins.
External interrupt 1 input signals are hysteresis signals (edge detection).
45
P12/INT12
46
P11/INT11
47
VCC2
Power supply (5V) pin.
48
P10/INT10
E
General purpose I/O port.
Also functions as an external interrupt 1 input pin.
External interrupt 1 input signals are hysteresis signals (edge detection).
49
RST
I
Reset input pin.
50
X0A
51
X1A
A
Crystal oscillator pins (32 KHz) .
(Continued)
9
MB89550A Series
Pin
No.
Pin Name
Circuit
Type
52
MODA
F
Operating mode setting pin.
53
X0
54
X1
A
Crystal oscillator pins (Max12.5 MHz) .
55
P80/INT24
E
General purpose I/O port.
Also functions as an external interrupt 2 input pin.
External interrupt 2 input signals are hysteresis signals (level detection).
56
VSS
Power supply (GND) pin.
57
P81/INT25
58
P82/INT26
E
59
P83/INT27
General purpose I/O ports.
Also function as external interrupt 2 input pins.
External interrupt 2 input signals are hysteresis signals (level detection).
60
P20/UI
E
61
P21/UO
B
62
P22/UCK
E
63
P23/PPG1
B
General purpose I/O port.
Also functions as the 6-bit PPG timer output.
64
P24/INT20
65
P25/INT21
66
P26/INT22
E
General purpose I/O ports.
Also function as external interrupt 2 input pins.
External interrupt 2 input signals are hysteresis signals (level detection).
67
P27/INT23
68
P30
69
P31
K
N-ch open drain I/O pins.
70
DAOUT2
71
DAOUT1
C
D/A converter output pins.
72
DVR
D/A converter reference voltage input pin.
73
P84/TO21
74
P85/TO22
B
75
P86/EC2/
LCLK
E
General purpose I/O ports.
Also function as 8/16-bit timer pins.
• P84 can be used as the output for the main clock×2 pulse.
• P86 can be used as the event counter input or sub-clock pulse output.
76
P87/EC3
E
General purpose I/O port.
Also functions as a 16-bit timer pin.
77
P40/TO11/
WTO
B
78
P41/TO12/
HCLK
General purpose I/O ports.
Also function as 8/16-bit timer pins.
79
P42/
PWM1/
EC1
E
80
P43/PWM2
B
Function
General purpose I/O ports.
Also function as 8-bit serial I/O pins.
General purpose I/O ports.
Also function as PWM timer pins.
(Continued)
10
MB89550A Series
(Continued)
Pin
Circuit
Pin Name
No.
Type
Function
81
P44/SCK
E
82
P45/SO
B
83
P46/SI
J
84
P47/PWC
J
General purpose I/O port.
Also functions as the PWC timer pin.
85
C1
86
C0
Step-up voltage circuit capacitance connection pins.
87
V0
88
V1
89
V2
LCD drive power supply pins.
90
V3
91
COM0
92
COM1
93
COM2
H
Dedicated LCDC common output pins.
94
COM3
95
SEG00
96
SEG01
H
Dedicated LCDC segment output pins.
97
SEG02
98
VCC1
Power supply (3V) pin.
99
SEG03
100
SEG04
H
Dedicated LCDC segment output pins.
General purpose I/O ports.
Also function as UART pins.
11
MB89550A Series
■ I/O CIRCUIT TYPES
Type
Circuit
Remarks
Oscillation feedback resistance
• High speed side = approx. 1 MΩ
• Low speed side = approx. 4.5 MΩ
X1 (X1A)
A
X0 (X0A)
Main clock control signal
(Sub-clock control signal)
• CMOS I/O
R
Pull-up control
register
Pch
Pch
B
Nch
Input control signal
• D/A output
Output enable
C
Analog output
R
Pull-up control
register
Pch
• A/D input
• CMOS I/O
Pch
D
Nch
Input control
signal
Port input
Analog input
(Continued)
12
MB89550A Series
Type
Circuit
R
Remarks
Pull-up control
register
Pch
• CMOS I/O
• Hysteresis input (for external interrupt 0, 1, 2 input)
Pch
E
Nch
Input control
signal
Port input
Resource input
• CMOS input
Input
F
Input control
signal
Port input
• LCDC output
• N-ch open drain I/O
G
Nch
• LCDC output
H
• Hysteresis input
• Pull-up resistance
R
Pch
I
Nch
Input
• Hysteresis input
• N-ch open drain I/O
J
Nch
Resource input
Input control signal
Port input
(Continued)
13
MB89550A Series
(Continued)
Type
Circuit
Remarks
• N-ch open drain I/O
K
Nch
Input control signal
14
Port input
MB89550A Series
■ HANDLING DEVICES
• Maximum rated voltage (Prevention of latchup)
Be careful never to exceed maximum rated voltages.
In CMOS IC devices, a condition known as latch-up may occur if voltages higher than Vcc or loser than Vss
are applied to input or output pins other than medium- or high-voltage pins, or if the voltage applied between
Vcc and Vss exceeds the rated voltage level.
When latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit
elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation.
Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power
supply voltages (AVcc, AVR, and DVR) and analog input voltages do not exceed the digital power supply (Vcc).
• Power supply voltages
Power supply voltages should be kept as stable as possible.
Rapid fluctuation of the voltage may cause the device to operate abnormally, even if the voltage remains within
the allowed operating range.
As a standard for power supply voltage stability, it is recommended that the peak-to-peak Vcc ripple voltage
at commercial supply frequency (50 Hz to 60 Hz) be 10% or less of Vcc. Also when the power supply is turned
on or off the transient voltage fluctuation be no more than 0.1V/ms or less.
• Treatment of unused input pins
Leaving unused input pins unconnected can cause abnormal operation. Unused input pins should always be
pulled up or down.
• Treatment of N.C. pins
N.C. (not connected) pins should always be left open.
• Treatment of power supply pins on devices with A/D or D/A converters
Even when the A/D or D/A converters are not in use, be sure to make the necessary connections to ensure
that AVCC = VCC, AVSS = AVR = DVR = VSS.
• Precautions on using an external clock
An oscillation stabilization delay occurs after a power-on reset or when recovering from sub-clock or stop
mode, even if an external clock is used.
• Treatment of unused dedicated LCD pins
Dedicated SEG output pins should be left open when not in use.
• Handling of ports also used as segment pins
When a ports is used as a segment pin, take care to ensure that the voltage applied to the pin does not exceed
V3 (the segment drive voltage). This precaution is particularly necessary in models with step-up voltage circuits.
Note also that after power-on or during a reset, an “L” level default signal is output form the segment/port pin.
• Treatment of unused LCD pins
Connect the V3 pin to VCC2. The other dedicated LCD pins V0, V1, V2, C0, and C1 should be pulled down.
• Executing programs on RAM
When programs are executed on RAM, debugging cannot be performed even with the use of the MB89PV550A.
• Wild register functions
Wild registers cannot be debugged with the MB89PV550A or tools. To verify operation, use the MB89P558A
and perform in-place testing.
15
MB89550A Series
■ PROGRAMMING SPECIFICATIONS FOR ONE-TIME PROM PRODUCTS
The MB89P558A has a "PROM mode" with functions equivalent to the MBM27C1001, that enables the microcontroller to be programmed by writing from a general-purpose ROM programmer with the use of a special
adapter. Note however that electronic signature mode is not available.
ROM Programmer Adapters
With some ROM programmers the insertion of approximately 0.1µF capacitance between VPP and VSS or between
VCC and VSS allows more stable writing performance. The following table lists ROM programmer adapters.
ROM Programmer Adapters
Part No.
MB89P558A
• Inquiries
Sun Hayato Co., Ltd.
Package
Adapter Part No.
FPT-100P-M05
ROM-100SQF-32DP-8LA2
FPT-100P-M18
ROM-100SQF-32DP-8LA
: TEL 03-3986-0403
• PROM Mode Memory Map
The PROM mode memory map is shown below.
PROM Mode Memory Map
Normal operating mode
PROM mode
(addresses on ROM programmer)
0000H
I/O
0080H
RAM
0880H
Not
availablel
4000H
14000H
Program
area
(PROM)
FFFFH
16
Program
area
(PROM)
1FFFFH
MB89550A Series
• EPROM Programming Procedure
1) Set the EPROM programmer type to MBM27C1001.
2) Load the program data into addresses 14000H to 1FFFFH in the EPROM programmer.
3) Use the EPROM programmer to program to addresses 14000H to 1FFFFH.
• Recommended Screening Conditions
High-temperature aging is the recommended method of screening unprogrammed one-time PROM microcontrollers before mounting.
The flow of the screening process is shown below.
Screening Flow
Program, verify
High-temperature aging
+150 °C, 48 h
Read
Mount
• About Writing Yields
The nature of chips before one-time writing of microcontroller programs to PROM prevents the use of all-bit
writing tests. Therefore it is not possible to guarantee writing yields of 100% in some cases.
17
MB89550A Series
■ BLOCK DIAGRAM
21-bit
time base timer
Main clock oscillator
circuit &
sub-clock oscillator
circuit
X0A
X1A
2-channel 8-bit
PWM timer
Clock control circuit
Reset output circuit
P57/SEG15 ∼ P50/SEG08
SEG07 ∼ SEG00
COM3 ∼ COM0
8-bit timer
counter
P40/TO11/WTO
LCD display
power generation and stepup circuit
8-bit timer
counter
LCD driver &
N-ch OD I/O ports
P67/SEG23 ∼ P60/SEG16
P41/TO12/HCLK
8-bit timer
counter
V3 ∼ V0
C1, C0
P77/SEG31 ∼ P70/SEG24
8-bit timer
counter
Power-on reset & WDG
circuit
LCD
controller &
driver
control
circuit
Static drive
control circuit
Internal bus
RST
P43/PWM2
P42/PWM1/EC1
Clock output
CMOS I/O Port
X0
X1
16-bit timer
counter
6 bit PPG
P23/PPG1
UART/SIO
P20/UI
P21/UO
P22/UCK
P17/INT17 ∼ P10/INT10
P44/SCK
P45/SO
External interrupt 1 (edge)
RAM 1 K/2 Kbyte
8-bit PWC timer
N-ch OD
I/O ports
CMOS I/O Port
SIO
P83/INT27 ∼ P80/INT24
P27/INT23 ∼ P24/INT20
Other pins
VSS
18
VSS VCC1 VCC2 MODA
N-ch open
drain I/O
ports
ROM 32 K/48 Kbyte
P47/PWC
AVCC
AVSS
AVR
CMOS I/O Port
8-channel
10-bit A/D
converter
P46/SI
DAOUT1
DAOUT2
DVR
2-channel
8-bit D/A
converter
F2MC-8L CPU
Wild register circuit
6 byte
P84/TO21
P86/EC2/LCLK
P87/EC3
UART
External interrupt 2 (level)
P85/TO22
P00/AN0 ∼ P07/AN7
P30
P31
MB89550A Series
■ CPU CORE
Memory space
The MB89550A has 64 Kbytes of memory space, composed of the I/O area, RAM area, ROM area, and external
area. The memory space includes general purpose registers, as well as areas used for special purposes such
as vector tables.
• I/O Area (address : 0000H to 007FH)
• This area is allocated to control registers and data registers for internal peripheral functions.
• Because the I/O area is part of memory space, it can be accessed in the same ways. Direct addressing provides
faster access.
• RAM Area
• Static RAM is provided for use as an internal data area.
• The size of internal RAM differs between product models.
• High speed access is available to addresses 80H to FFH using direct addressing (the area available for use is
restricted on some models).
• Addresses 100H to 1FFH are used as the general-purpose register area.
• If a reset is applied during writing to RAM, the value of date at the target addresses is not assured.
• ROM Area
• ROM is provided for use as the internal program area.
• The size of internal ROM differs between product models.
• Addresses FFC0H to FFFFH are used for special purpose data such as vector tables.
Memory Map
MB89P558A
MB89558A
MB89557A
0000H
0000H
I/O
0080H
0000H
I/O
0080H
RAM
0100H
RAM
Register
Register
Register
0200H
0480H
Wild register
0492H
RAM
0100H
0200H
0480H
I/O
0080H
0100H
0200H
MB89PV550A
0480H
Wild register
Wild register
0492H
0492H
RAM
0880H
Not available
Not available
Not available
4000H
4000H
8000H
External ROM
ROM
ROM
FFC0H
FFC0H
FFC0H
FFFFH
FFFFH
FFFFH
Vector tables
(Reset, interrupt, vector
call instructions)
Vector tables
(Reset, interrupt, vector
call instructions)
Vector tables
(Reset, interrupt, vector
call instructions)
19
MB89550A Series
■ I/O MAP
Address
Abbreviation
Resister Name
00H
PDR0
Port 0 data register
01H
DDR0
Port 0 direction register
02H
PDR1
Port 1 data register
03H
DDR1
Port 1 direction register
04H to 06H
Read/Write
Initial Value
R/W
XXXXXXXXB
W
0 0 0 0 0 0 0 0B
R/W
XXXXXXXXB
W
0 0 0 0 0 0 0 0B
Unused area
07H
SYCC
System clock control register
R/W
XXX MM1 0 0B
08H
STBC
Standby control register
R/W
0 0 0 1 0 XXXB
09H
WDTC
Watchdog control register
R/W
0XXXXXXXB
0AH
TBTC
Time base time control register
R/W
X 0 XXX 0 0 0B
0BH
WPCR
Clock prescaler control register
R/W
X 0 XX 0 0 0 0B
0CH
PDR2
Port 2 data register
R/W
XXXXXXXXB
0DH
DDR2
Port 2 direction register
R/W
0 0 0 0 0 0 0 0B
0EH
PDR3
Port 3 data register
R/W
- - - - - - 1 1B
0FH
PDR4
Port 4 data register
R/W
1 1 XXXXXXB
10H
DDR4
Port 4 direction register
R/W
- - 0 0 0 0 0 0B
11H
PDR5
Port 5 data register
R/W
0 0 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
12H
13H
Unused area
PDR6
Port 6 data register
14H
15H
Unused area
PDR7
Port 7 data register
16H
Unused area
17H
PDR8
Port 8 data register
R/W
XXXXXXXXB
18H
DDR8
Port 8 direction register
R/W
0 0 0 0 0 0 0 0B
19H
Unused area
1AH
T2CR#2
Timer 2 control register # 2(8/16-bit timer/counter -1)
R/W
X 0 0 0 0 0 X 0B
1BH
T1CR#1
Timer 1 control register # 1(8/16-bit timer/counter -1)
R/W
X 0 0 0 0 0 X 0B
1CH
T2DR#2
Timer 2 data register # 2(8/16-bit timer/counter -1)
R/W
XXXXXXXXB
1DH
T1DR#1
Timer 1 data register # 1(8/16-bit timer/counter -1)
R/W
XXXXXXXXB
1EH
T2CR#4
Timer 2 control register # 4(8/16-bit timer/counter -2)
R/W
X 0 0 0 0 0 X 0B
1FH
T1CR#3
Timer 1 control register # 3(8/16-bit timer/counter -2)
R/W
X 0 0 0 0 0 X 0B
20H
T2DR#4
Timer 2 data register # 4(8/16-bit timer/counter -2)
R/W
XXXXXXXXB
21H
T1DR#3
Timer 1 data register # 3(8/16-bit timer/counter -2)
R/W
XXXXXXXXB
22H
SMC1
Serial mode control register 1 (UART)
R/W
0 0 0 0 0 0 0 0B
23H
SRC1
Serial rate control register (UART)
R/W
- - 0 1 1 0 0 0B
(Continued)
20
MB89550A Series
Address
Abbreviation
24H
SSD1
25H
SIDR1/
SODR1
26H
Resister Name
Read/Write
Initial Value
Serial status and data register (UART)
R/W
0 0 1 0 0 - 1XB
Serial input/serial output data register (UART)
R/W
XXXXXXXXB
SMC2
Serial mode control register 2 (UART)
R/W
- - 1 0 0 0 0 1B
27H
CNTR1
PWM control register 1
R/W
0 0 0 0 0 0 0 0B
28H
CNTR2
PWM control register 2
R/W
0 0 0 X 0 0 0 0B
29H
CNTR3
PWM control register 3
R/W
X 0 0 0 XXXXB
2AH
COMR1
PWM compare register 1
W
XXXXXXXXB
2BH
COMR2
PWM compare register 2
W
XXXXXXXXB
2CH
PCR1
PWC pulse width control register 1
R/W
0 0 0 XX 0 0 0B
2DH
PCR2
PWC pulse width control register 2
R/W
0 0 0 0 0 0 0 0B
2EH
PLBR
PWC reload buffer register
R/W
XXXXXXXXB
2FH
SMC21
Serial mode control register 1 (UART/SIO)
R/W
0 0 0 0 0 0 0 0B
30H
SMC22
Serial rate control register 2 (UART/SIO)
R/W
0 0 0 0 0 0 0 0B
31H
SSD2
Serial status and data register
(UART/SIO)
R/W
0 0 0 0 1 XXXB
32H
SIDR2/
SODR2
Serial input/serial output date register (UART/SIO)
R/W
XXXXXXXXB
33H
SRC2
Baud rate generator reload register
(UART/SIO)
R/W
XXXXXXXXB
34H
ADC1
A/D control register 1
R/W
0 0 0 0 0 0 0 0B
35H
ADC2
A/D control register 2
R/W
X 0 0 0 0 0 0 1B
36H
ADDL
A/D data register low
R/W
XXXXXXXXB
37H
ADDH
A/D data register high
R/W
0 0 0 0 0 0 XXB
38H to 3BH
Unused area
3CH
TMCR
Timer control register (16-bit timer/counter)
R/W
XX 0 0 0 0 0 0B
3DH
TCHR
Timer count register high (16-bit timer/counter)
R/W
0 0 0 0 0 0 0 0B
3EH
TCLR
Timer count register low (16-bit timer/counter)
R/W
0 0 0 0 0 0 0 0B
3FH
EIC1
External interrupt register 1
R/W
0 0 0 0 0 0 0 0B
40H
EIC2
External interrupt register 2
R/W
0 0 0 0 0 0 0 0B
41H
EIC3
External interrupt register 3
R/W
0 0 0 0 0 0 0 0B
42H
EIC4
External interrupt register 4
R/W
0 0 0 0 0 0 0 0B
43H
DACR
D/A control register
R/W
XXXXXX 0 0B
44H
DADR1
D/A data register 1
R/W
XXXXXXXXB
45H
DADR2
D/A data register 2
R/W
XXXXXXXXB
R/W
0 0 0 0 0 0 0 0B
46H to 55H
56H
Unused area
EIE2
External interrupt 2 control register
(Continued)
21
MB89550A Series
(Continued)
Address
Abbreviation
57H
EIF2
58H
Read/Write
Initial Value
External interrupt 2 flag register
R/W
XXXXXXX 0B
RCR1
6-bit PPG control register 1
R/W
0 0 0 0 0 0 0 0B
59H
RCR2
6-bit PPG control register 2
R/W
0 - 0 0 0 0 0 0B
5AH
CKR
Clock output control register
R/W
XXXXXX 0 0B
5BH
LCR1
LCDC control register 1
R/W
0 0 0 1 0 0 0 0B
5CH
LCR2
LCDC control register 2
R/W
0 0 0 0 0 0 0 0B
5DH
LCR3
LCDC control register 3
R/W
- - - 0 0 0 0 0B
5EH
LCD1
LCD static display register 1
R/W
XXXXXXXXB
5FH
LCD2
LCD static display register 2
R/W
XXXXXXXXB
60H to 6FH
VRAM
LCD display RAM
R/W
XXXXXXXXB
70H
SMR
Serial mode register (8-bit serial I/O)
R/W
0 0 0 0 0 0 0 0B
71H
SDR
Serial data register (8-bit serial I/O)
R/W
XXXXXXXXB
72H
PORR0
Port 0 pull-up option setting register
R/W
11111111B
73H
PURR1
Port 1 pull-up option setting register
R/W
11111111B
74H
PURR2
Port 2 pull-up option setting register
R/W
11111111B
75H
PURR4
Port 4 pull-up option setting register
R/W
11111111B
76H
PURR8
Port 8 pull-up option setting register
R/W
11111111B
77H
WREN
Wild register/address comparator enable register
R/W
- - 0 0 0 0 0 0B
R/W
11111111B
78H
79H
Unused area
ADEN
7AH
A/D port input enable register
Unused area
7BH
ILR1
Interrupt level setting register 1
W
1 1 1 1 1 1 1 1B
7CH
ILR2
Interrupt level setting register 2
W
1 1 1 1 1 1 1 1B
7DH
ILR3
Interrupt level setting register 3
W
1 1 1 1 1 1 1 1B
7EH
ILR4
Interrupt level setting register 4
W
1 1 1 1 1 1 1 1B
7FH
22
Resister Name
Unused area
MB89550A Series
• Extended I/O Area
Address
Abbreviation
Resister Name
Read/Write
Initial Value
480H
WRARH1
H address setting register 1
R/W
XXXXXXXX
481H
WRARL1
L address setting register 1
R/W
XXXXXXXX
482H
WRDR1
Data setting register 1
W
XXXXXXXX
483H
WRARH2
H address setting register 2
R/W
XXXXXXXX
484H
WRARL2
L address setting register 2
R/W
XXXXXXXX
485H
WRDR2
Data setting register 2
W
XXXXXXXX
486H
WRARH3
H address setting register 3
R/W
XXXXXXXX
487H
WRARL3
L address setting register 3
R/W
XXXXXXXX
488H
WRDR3
Data setting register 3
W
XXXXXXXX
489H
WRARH4
H address setting register 4
R/W
XXXXXXXX
48AH
WRARL4
L address setting register 4
R/W
XXXXXXXX
48BH
WRDR4
Data setting register 4
W
XXXXXXXX
48CH
WRARH5
H address setting register 5
R/W
XXXXXXXX
48DH
WRARL5
L address setting register 5
R/W
XXXXXXXX
48EH
WRDR5
Data setting register 5
W
XXXXXXXX
48FH
WRARH6
H address setting register 6
R/W
XXXXXXXX
490H
WRARL6
L address setting register 6
R/W
XXXXXXXX
491H
WRDR6
Data setting register 6
W
XXXXXXXX
O Read/write notation
• R/W : Reading and writing enabled
•R
: Read-only
•W
: Write only
O Initial value notation
• 0 : Initial value of bit is “0”.
• 1 : Initial value of bit is “1”.
• X : Initial value of bit is undefined.
Note : Areas indicated as "unused area" are not to be used.
23
MB89550A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
(AVss = Vss = 0 V)
Rating
Unit
Remarks
Min
Max
VCC1
VSS − 0.3
VSS + 4.0
VCC2
VSS − 0.3
VSS + 6.0
A/D converter reference input
voltage
AVR
VSS − 0.3
VSS + 6.0
V
D/A converter reference input
voltage
DVR
VSS − 0.3
VSS + 6.0
V
V0-V3
VSS − 0.3
VSS + 6.0
V
On models without step-up circuits
V0-V3 are not to exceed VCC2.
VI1
VSS − 0.3
VCC2 + 0.3
V
Pins other than P50 to P57, P60 to
P67, P70 to P77, P46, P47, P30,
P31
VI2
VSS − 0.3
V3
V
P50 to P57, P60 to P67, P70 to P77
VI3
VSS − 0.3
VSS + 6.0
V
P46, P47, P30, P31
VO1
VSS − 0.3
VCC2
V
Pins other than P50 to P57, P60 to
P67, P70 to P77, P46, P47, P30,
P31
VO2
VSS − 0.3
V3
V
P50 to P57, P60 to P67, P70 to P77
VO3
VSS − 0.3
VSS + 6.0
V
P46, P47, P30, P31
IOL1
15
mA
Pins other than P22/UCK, P23/
PPG1
IOL2
30
mA
P22/UCK, P23/PPG1
Power supply voltage
LCD power supply voltage
Input voltage
Output voltage
“L” level maximum output
current
V
IOLAV1
4
mA
Pins other than P22/UCK, P23/
PPG1
average value
(operating current × operating ratio)
IOLAV2
15
mA
P22/UCK, P23/PPG1
average value
(operating current × operating ratio)
ΣIOL
100
mA
ΣIOLAV
60
mA
average value
(operating current × operating ratio)
IOH1
−15
mA
Pins other than P22/UCK, P23/
PPG1
IOH2
−30
mA
P22/UCK, P23/PPG1
“L” level average output
current
“L” level total maximum output
current
“L” level total average output
current
“H” level maximum output
current
VCC1 not to exceed VCC2.*
(Continued)
24
MB89550A Series
(Continued)
Parameter
Symbol
Rating
Min
Max
Unit
Remarks
IOHAV
−4
mA
Pins other than P22/UCK, P23/
PPG1 and open drain output pins
average value
(operating current × operating ratio)
IOHAV
−15
mA
P22/UCK, P23/PPG1
average value
(operating current × operating ratio)
ΣIOH
−50
mA
ΣIOHAV
−30
mA
Power consumption
PD
300
mW
Operating temperature
TA
−40
+85
°C
Tstg
−55
+150
°C
“H” level average output
current
“H” level total maximum
output current
“H” level total average output
current
Storage temperature
average value
(operating current × operating ratio)
* : Set AVCC to the same potential as VCC.
Also ensure that AVR and DVR do not exceed AVCC + 0.3 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
25
MB89550A Series
2. Recommended Operating Conditions
Item
Symbol
(AVss = Vss = 0 V)
Rating
Unit
Remark
Min
Max
VCC1
2.2*1
3.6
V
VCC2
2.2*
1
5.5
V
VCC1
V
VCC2
2.7*2
5.5
V
Guaranteed normal operating range
(MB89P558A)
VCC1, VCC2
1.5
3.6
V
To maintain RAM state in stop mode
A/D converter reference
voltage input*4
AVR
VCC1
AVCC
V
Guaranteed normal operating range
D/A converter reference
voltage input*4
DVR
VCC1
AVCC
V
Guaranteed normal operating range
Models without step-up circuit, pins V0
to V3. LCD power supply range and
maximum value are determined by the
characteristics of the LCD display element used.
3
Power supply voltage*
LCD supply voltage
Operating temperature
V0-V3
VSS
VCC2
V
TA
−40
+85
°C
Guaranteed normal operating range
(MB89557A/558A)
*1 : The operating power supply voltage differs depending on the instruction cycle time of the operating frequency.
See Figure 1.
*2 : The operating power supply voltage differs depending on the instruction cycle time of the operating frequency.
See Figure 2. Note also that on the MB89PV550A the input to the VCC1 pin is cut off internally, and on the
MB89P558A the VCC1 pin is used as the VPP pin for on-board writing.
*3 : AVcc and VCC2 should be set to the same potential. Also, care must be taken to ensure that VCC1 does not exceed
VCC2.
*4 : Care must be taken to ensure that the relation between AVR and DVR is such that “VCC1 ≤ AVR (DVR) ≤ AVCC
+ 0.3 V”.
26
MB89550A Series
Operating voltage (VCC1)
Figure 1. Operating Voltage vs. Operating Frequency (MB89558A/557A)
6
6
5
5
4
4
MB89557A/MB89558A*
3
3
2
2
1
1
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
Operating frequency (MHz) (at instruction cycle = 4 / Fc)
4.0 2.0
Instruction cycle
0.8
0.4
0.32
(µs)
* : Analog precision warranted range : AVCC = 3.5 V to 5.5 V
: TA = −40 °C ∼ +85 °C
Operating voltage (VCC2)
Figure 2. Operating Voltage vs. Operating Frequency (MB89P558A)
6
6
5
5
MB89P558A*
4
4
3
3
2
2
1
1
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
Operating frequency (MHz) (at instruction cycle = 4 / Fc)
0.8
4.0 2.0
Instruction cycle
0.4
0.32
(µs)
: TA = −40 °C ∼ +85 °C
: TA = −10 °C ∼ +55 °C
: TA = +25 °C
* : VCC2 = 2.2 V to 5.5 V (VCC2 ≥ VCC1)
Analog precision warranted range : AVCC = 3.5 V to 5.5 V
27
MB89550A Series
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
28
MB89550A Series
3. DC Characteristics
Parameter
“H” level input
voltage
“L” level input
voltage
Voltage
applied to
open drain
output pins
“H” level
output voltage
“L” level
output voltage
Input leak
current
(Hi-Z output
leak current)
(AVCC = AVR = DVR = VCC2 = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Symbol
Pin name
Condition
VIH1
P00 to P07, P10 to P17,
P20 to P27, P40 to P45,
P80 to P87
VIH2
Value
Unit
Remarks
Min
Typ
Max
0.7 VCC2
VCC2 + 0.3
V
P50 to P57, P60 to P67,
P70 to P77
0.7 VCC2
V3
V
VIH3
P46, P47, P30, P31
0.7 VCC2
VSS + 5.5
V
VIHS1
INT10 to INT17, UI,
UCK, INT20 to INT27,
SCK, EC1, EC2, EC3,
RST, MODA
0.8 VCC2
VCC2 + 0.3
V
Hysteresis
input
VIHS2
SI, PWC
0.8 VCC2
VSS + 5.5
V
Hysteresis
input
VIL1
P00 to P07, P10 to P17,
P20 to P27, P30, P31,
P40 to P47, P80 to P87
VSS − 0.3
0.3 VCC2
V
VIL2
P50 to P57, P60 to P67,
P70 to P77
VSS − 0.3
0.3 VCC2
V
VIL2 not to
exceed V3.
VILS
INT10 to INT17, UI,
UCK, INT20 to INT27,
SCK, EC1, EC2, EC3,
RST, MODA, SI, PWC
VSS − 0.3
0.2 VCC2
V
Hysteresis
input
VD1
P46, P47, P30, P31
VSS − 0.3
VSS + 5.5
V
VD2
P50 to P57, P60 to P67,
P70 to P77
VSS − 0.3
V3
V
VOH1
P00 to P07, P10 to P17,
IOH =
P20, P21, P24 to P27,
−2.0 mA
P40 to P45, P80 to P87
4.0
V
VOH2
P22, P23
IOH =
−4.0 mA
4.0
V
VOL1
P00 to P07, P10 to P17,
P20, P21, P24 to P27,
IOL =
P30, P31, P40 to P47,
4.0 mA
P50 to P57, P60 to P67,
P70 to P77, P80 to P87
0.4
V
VOL2
P22, P23
0.4
V
ILI
IOL = 12 mA
P00 to P07, P10 to P17,
P20 to P27, P30, P31
0.0V < VI <
P40 to P47, P50 to P57,
VCC2
P60 to P67, P70 to P77,
P80 to P87, MODA
±5
µA
VIH2 not to
exceed V3.
VD2 not to
exceed V3.
Without
pull-up
resistor
option
(Continued)
29
MB89550A Series
(AVCC = AVR = DVR = VCC2 = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
Pull-up
resistance
Symbol
Pin name
Condition
P00 to P07, P10 to P17,
RPULL P20 to P27, P40 to P45, VI = 0.0 V
P80 to P87, RST
Unit
Remarks
100
kΩ
With pull-up
resistor option
Min
Typ
Max
25
50
VCC1
VCC1 = 3.0 V
VCC2 = 5.0 V
FCH = 12.5 MHz
4.5
6
mA
tinst = 0.32 µs
MB89557A/
558A
VCC2
VCC2 = 5.0 V
FCH = 12.5 MHz
22
25
mA
tinst = 0.32 µs
MB89P558A
VCC1
VCC1 = 3.0 V
VCC2 = 5.0 V
FCH = 10.0 MHz
1.4
2.1
mA
tinst = 6.4 µs
MB89557A/
558A
VCC2
VCC2 = 3.0 V
FCH = 10.0 MHz
5.3
9
mA
tinst = 6.4 µs
MB89P558A
VCC1
VCC1 = 3.0 V
VCC2 = 3.0 V
FCH = 12.5 MHz
2
3
Sleep mode
tinst = 0.32 µs
mA
MB89557A/
558A
VCC2
VCC2 = 5.0 V
FCH = 12.5 MHz
6.2
10
Sleep mode
mA tinst = 0.32 µs
MB89P558A
VCC1
VCC1 = 3.0 V
VCC2 = 3.0 V
FCH = 10.0 MHz
0.35
1
Sleep mode
tinst = 6.4 µs
mA
MB89557A/
558A
VCC2
VCC2 = 3.0 V
FCH = 10.0 Hz
0.6
2
mA
Sleep mode
tinst = 6.4 µs
MB89P558A
VCC1
VCC1 = 3.0 V
VCC2 = 5.0 V
FCL = 32 kHz
TA = + 25 °C
30
50
µA
Sub-mode
MB89557A/
558A
VCC2
VCC2 = 3.0 V
FCL = 32 kHz
TA = + 25 °C
4
8
mA
Sub-mode
MB89P558A
VCC1
VCC1 = 3.0 V
VCC2 = 3.0 V
FCL = 32 kHz
TA = + 25 °C
10
20
µA
Sub-sleep
mode
MB89557A/
558A
VCC2
VCC2 = 3.0 V
FCL = 32 kHz
TA = + 25 °C
20
50
µA
Sub-sleep
mode
MB89P558A
ICC1
ICC2
ICCS1
Power supply
current
Value
ICCS2
ICCL
ICCLS
(Continued)
30
MB89550A Series
(AVCC = AVR = DVR = VCC2 = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Min
Typ
Max
Unit
Remarks
VCC1
5
15
µA
Clock mode
Main stop
MB89557A/
558A
VCC2
VCC2 = 3.0 V
FCL = 32 kHz
TA = + 25 °C
12
25
µA
Clock mode
Main stop
MB89P558A
VCC1
VCC1 = 3.0 V
VCC2 = 3.0 V
FCL = 32 kHz
TA = + 25 °C
5
10
µA
TA = +25 °C
Sub- stop
MB89557A/
558A
VCC2
VCC2 = 3.0 V
FCL = 32 kHz
TA = + 25 °C
5
10
µA
TA = +25 °C
Sub- stop
MB89P558A
AVCC
VCC1 = 3.0 V
AVCC = VCC2 =
5.0 V
FCH = 12.5 MHz
2
5
A/D converter
running
mA
MB89557A/
558A
AVCC
VCC2 = 5.0 V
FCH = 12.5 MHz
3
6
mA
A/D converter
running
MB89P558A
AVCC
VCC1 = 3.0 V,
AVCC = VCC2 =
5.0 V
FCH = 12.5 MHz
TA = + 25 °C
µA
TA = +25 °C
A/D converter
stopped
MB89557A/
558A
AVCC
VCC2 = 5.0 V
FCH = 12.5 MHz
TA = + 25 °C
10
µA
TA = +25 °C
A/D converter
stopped
MB89P558A
VCC to V0
at VCC = 5 V
500
kΩ
5
kΩ
15
kΩ
±5
µA
ICCH
IA
IAH
LCD divider
resistance
Value
VCC1 = 3.0 V
VCC2 = 3.0 V
TA = + 25 °C
FCL = 32 kHz
ICCT
Power supply
current
Condition
RLCD
COM0 to
COM3
output
impedance
RVCOM COM0 to COM3
SEG0 to
SEG31
output
impedance
RVSEG SEG0 to SEG31
LCD
leak current
V0 to V3,
ILCDL COM0 to COM3,
SEG0 to SEG31
10
V1 to V3 = 5 V
(Continued)
31
MB89550A Series
(Continued)
Parameter
LCD step-up
output voltage
32
Symbol
Pin name
VOV3 V3
VOV2 V2
Condition
V1 = 1.5 V
Reference
voltage input
impedance
RRIN
V1
Input
capacitance
CIN
Pins other than VCC,VSS FCH = 1 MHz
V1 input
voltage
VI1
V1
IIN = 0 µA
Value
Unit
Remarks
V
3.0
V
Models with
step-up circuits
only
600
1000
1400
kΩ
10
pF
1.5
V
Min
Typ
Max
4.5
Models with
step-up circuits
only
Models with
step-up circuits
only
MB89550A Series
4. AC Characteristics
(1) Reset Timing
Parameter
(DVR = VCC1 = 3 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Symbol
Confition
tZLZH
RST “L” pulse width
Rating
Min
Max
48 tHCLY
Unit
Remarks
ns
Note : tHCLY is the main clock oscillator period.
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
Parameter
Power supply rise time
Power supply cutoff time
(AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Symbol
Confition
tR
tOFF
Rating
Unit
Min
Max
0.05
50
ms
1
ms
Remarks
For repeated operation
Note : Be sure that the power supply rise time is less than the selected oscillator stabilization period. Also, when
varying the supply voltage during operation, it is recommended that the supply voltage be increased gradually.
tR
tOFF
1.8 V
VCC1, VCC2
0.2 V
0.2 V
0.2 V
On the MB89PV550A and MB89548A oscillation begins and the power-on reset is applied on the rise
of the VCC2.On the MB89558A and MB89557A, oscillation begins and the power-on reset is applied on
the rise of the VCC1.
33
MB89550A Series
(3) Power Supply Voltage
VCC2
VCC1
0V
Be sure that the power supply is set so that VCC2 ≥ VCC1.
The MB89PV550A and MB89P558A operate on the VCC2 power supply only.
On the MB89558A and MB89557A, VCC1 is the power supply for internal CPU operation, and VCC2 is the
I/O power supply.
(4) Clock Timing
(AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rise, fall time
34
Symbol Pin Name
Condition
Value
Min
Typ
Max
Unit
Remarks
FCH
X0, X1
1
12.5
MHz
FCL
X0A, X1A
32.768
kHz
tHCYL
X0, X1
80
1000
ns
tLCYL
X0A, X1A
30.5
µs
PWH1
PWL1
X0
20
ns
External clock
PWH2
PWL2
X0A
15.2
µs
External clock
tCR
tCF
X0
10
ns
External clock
MB89550A Series
• X0 and X1 clock timing and input conditions
tHCYL
PWH1
PWL1
tCF
tCR
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Clock configurations
When using a crystal
oscillator or
ceramic oscillator
X0
X1
X0
FCH
C1
When using an
external clock
C2
X1
Open
FCH
35
MB89550A Series
• X0A and X1A clock timing conditions
tLCYL
PWL2
PWH2
tCR
tCF
0.8 VCC
0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Clock configurations
When using a crystal
oscillator or
ceramic oscillator
X0A
When using an
external clock
X1A
X0A
Open
FCL
C1
FCL
C2
(5) Instruction Cycle
Parameter
Instruction cycle
(minimum instruction execution
time)
(AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Symbol
Value
Unit
Remarks
4/FCH, 8/FCH, 16/FCH, 64/FCH,
µs
Operating at FCH = 12.5 MHz
(4/FCH)
tinst = 0.32 µs
2/FCL
µs
Operating at FCL = 32.768 kHz
tinst = 61.036 µs
tinst
Note : Instruction execution time settings differ for 12.5 MHz operation.
36
X1A
MB89550A Series
(6) Serial I/O timing
(VCC1 = 3.0 V, AVCC = AVR = DVR = VCC2 = 5 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Symbol
Pin Nme
Serial clock cycle time
tSCYC
SCK, UCK
SCK↓→SO time
UCK↓→UO time
tSLOV
SCK, SO, UCK,
UO
Valid SI→SCK↑
Valid UI→UCK↑
tIVSH
SI, SCK
SCK↑→ valid SI hold time
UCK↑→ valid UI hold time
tSHIX
SCK, SI, UCK, UI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK↓→SO time
UCK↓→UO time
tSLOV
SCK, SO, UCK,
UO
Valid SI→SCK↑
Valid UI→UCK↑
tIVSH
SI, SCK, UI, UCK
SCK↑→ valid SI hold time
UCK↑→ valid UI hold time
tSHIX
SCK, SI, UCK, UI
Parameter
Condition
Internal
clock
operation
SCK, UCK
External
clock
operation
Value
Unit
Min
Max
2 tinst*
µs
−200
+200
ns
1/2 tinst*
µs
1/2 tinst*
µs
1 tinst*
µs
1 tinst*
µs
0
200
ns
1/2 tinst*
µs
1/2 tinst*
µs
Remarks
* : For a definition of tinst see “ (5) Instruction Cycle”.
• Internal shift clock mode
tSCYC
SCK
UCK
2.4 V
0.8 V
0.8 V
tSLOV
SO
UO
2.4 V
0.8 V
tIVSH
0.8 VCC
0.2 VCC
SI
UI
tSHIX
0.8 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
SCK
UCK
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
SO
UO
2.4 V
0.8 V
tIVSH
SI
UI
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
37
MB89550A Series
(7) Peripheral Input Timing
(VCC1 = 3 V, AVCC = AVR = DVR = VCC2 = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin Nme
Condition
Peripheral input “H” level
pulse width 1
tILIH1
EC1, EC2, EC3
INT10 to INT17
Peripheral input “L” level
pulse width 1
tIHIL1
Peripheral input “H” level
pulse width 1
Peripheral input “L” level
pulse width 1
Value
Max
1 tinst*
µs
EC1, EC2, EC3
INT10 to INT17
1 tinst*
µs
tILIH2
PWC,
INT20 to INT27
2 tinst*
µs
tIHIL2
PWC,
INT20 to INT27
2 tinst*
µs
* : For a definition of tinst see “ (5) Instruction Cycle”.
tIHIL1
EC1, EC2, EC3
INT10 ~ INT17
tILIH1
0.8 VCC
0.2 VCC
INT20 ~ INT27,
PWC
tILIH2
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tIHIL2
38
Unit
Min
0.2 VCC
0.8 VCC
Remarks
MB89550A Series
(8) Electrical Characteristics for the A/D Converter
(VCC1 = 3 V, AVCC = AVR = DVR = VCC2 = 3.5 V to 5.5 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C)
Symbol
Item
Pin
Nme
Rating
Condition
Typ
Max
10
bit
±5.0
LSB
±2.5
LSB
±1.9
LSB
AVSS − 3.5
+ 0.5
Resolution
Total error
Linearity error
Differential linearity error
Zero transition voltage
AVR = AVCC
VOT
Full scale transition voltage
VFST
AN0 to
AN7
4
LSB
60 tinst
µs
16 tinst
µs
10
µA
AVSS
AVR
V
AVSS + 2.7
AVCC
V
A/D operating
400
µA
A/D stop
5
µA
Sampling time
Analog input current
IAIN
Analog input voltage
VAIN
Reference voltage
Reference voltage supply
current
IR
AN0 to
AN7
AVR
IRH
AVSS + 4.5 LSB
AVR − 6.5 AVR − 1.5 AVR + 1.5 LSB
Variation between channels
Conversion time
Unit Remarks
Min
*
* : Includes sampling time.
(9) Electrical Characteristics for the D/A Converter
(VCC1 = 3 V, AVCC = AVR = DVR = VCC2 = 3.5 V to 5.5 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C)
Item
Symbol
Pin Nme
Differential linearity
error
8
bit
±0.9
LSB
±1.5
LSB
10
20
µs
VSS + 3.0
AVCC
V
D/A running
120
300
µA
*2
D/A off
10
µA
*3
20
kΩ
MB89P558A
30
kΩ
MB89558A/
557A
Analog reference
voltage
Reference voltage
supply current
Analog output
impedance
IDVR
DVR
IDVRS
Remarks
Max
AVR = AVCC
Conversion time
Unit
Typ
Rating
Min
Resolution
Linearity error
Condition
*1
*1 : With load capacitance 20 pF.
*2 : No-load conversion
*3 : Stop mode
39
MB89550A Series
(10) A/D Converter Glossary
• Resolution
The level of analog variation that can be recognized by the A/D converter.
• Linearity error (Unit : LSB)
The deviation between the actual conversion characteristics and the line linking the zero transition point (“00 0000
0000”←→“00 0000 0001”) and the full-scale transition point (“11 1111 1110”←→“11 1111 1111”) .
• Differential linearity error (Unit : LSB)
The variation from the theoretical input voltage required to change the output code by 1 LSB.
• Total error (Unit : LSB)
The total error is the difference between the actual value and the theoretical value.
Theoretical I/O characteristics
Total error
VFST
3FF
3FF
3FE
1.5 LSB
3FD
004
003
VOT
002
Digital output
Digital output
3FE
3FD
Actual conversion
characteristic
(1 LSB × N +
0.5 LSB)
004
VNT
003
002
1 LSB
001
001
Actual conversion
characteristic
Theoretical
characteristic
0.5 LSB
AVSS
AVR
Analog input
1 LSB =
VFST − VOT
1022
(V)
AVSS
AVR
Analog input
Total error for digital output N =
VNT − {1 LSB × N + 0.5 LSB}
1 LSB
(Continued)
40
MB89550A Series
(Continued)
Zero transition error
Full-scale transition error
004
Theoretical characteristic
Actual conversion
characteristic
3FF
002
Actual conversion
characteristics
Digital output
Digital output
003
Actual conversion
characteristics
3FE
001
3FC
VOT (actual
measured value)
3FF
Digital output
3FE
Linearity error
Differential linearity error
Actual conversion
characteristics
Theoretical characteristic
N+1
(1 LSB × N + VOT)
VNT
VFST
(actual
measured
value)
004
002
001
AVR
Analog input
3FD
003
Actual conversion
characteristics
Analog input
Actual conversion
characteristics
Theoretical characteristic
VOT (actual measured value)
AVSS
AVR
Analog input
Linearity error in = VNT − {1 LSB × N + VOT}
1 LSB
digital output N
Digital output
AVSS
VFST (actual
measured
value)
3FD
Actual conversion
characteristic
V (N + 1) T
N
N−1
N−2
AVSS
VNT
Actual conversion
characteristic
Analog input
AVR
Differential linearity
= V (N + 1) T − VNT −1
1 LSB
errorin digital output N
41
MB89550A Series
(11) Notes for A/D Conversion
• Analog input pins and input impedance
The A/D converter in the MB89550A series incorporates a sample & hold circuit as shown below. When an A/
D conversion starts, the voltage at the analog input pin is captured by the sample & hold capacitor for a period
of 16 instruction cycles.
Accordingly, if the output impedance of the external circuit connected to the analog input is high, the analog
input voltage may not stabilize within the period of the analog input sampling time. Therefore, it is recommended
that the output impedance of the external circuit be sufficiently low (10 kΩ or less) .
• Equivalent circuit for MB89558A and MB89557A analog input
Sample & hold circuit
C = 30 pF
Analog input pin
Comparator
R = 3.2 kΩ
Closed for approximately 16 instruction
cycles after start of A/D conversion
Analog channel selector
• Equivalent circuit for MB89P558A and MB89PV550A analog input
Sample & hold circuit
C = 64 pF
Analog input pin
Comparator
R = 1.4 kΩ
Closed for approximately 16 instruction
cycles after start of A/D conversion
Analog channel selector
• Error
The relative error increases as AVR − AVSS becomes smaller.
42
MB89550A Series
■ EXAMPLE CHARACTERISTICS
(1) Power Supply Current (External Clock)
ICCS - VCC1
ICC - VCC1
10
10
(TA = + 25 ˚C)
(TA = + 25 ˚C)
FC = 12.5 MHz, 4 division
8
8
6
ICCS [mA]
ICC [mA]
6
4
FC = 12.5 MHz, 4 division
4
2
2
FC = 10 MHz, 64 division
FC = 10 MHz, 64 division
0
0
1
2
3
4
1
5
2
3
4
5
VCC1 [V]
VCC1 [V]
(2) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input)
VIN - VCC2
4
(TA = + 25 ˚C)
VIN [V]
3
2
1
0
3
2
4
7
6
5
VCC2 [V]
(3) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input)
VIN - VCC2
4
(TA = + 25 ˚C)
VIHS
VIN [V]
3
VILS
2
1
0
2
3
4
5
6
7
VCC2 [V]
43
MB89550A Series
(4) Pull-up Resistance
RPULL - VCC2
1000
(TA = + 25 ˚C)
Pull-up [kΩ]
100
10
1
3
2
5
4
7
6
VCC2 [V]
(5) “H” Level Output Voltage
VOH2 - IOH
VOH1 - IOH
4.6
4.6
(VCC2 = 4.5 V, TA = + 25 ˚C)
(VCC2 = 4.5 V, TA = + 25 ˚C)
4.4
4.2
VOH2 [V]
4.4
VOH1 [V]
4.0
3.8
4.2
3.6
3.4
4.0
3.2
3.0
3.8
0
-2
-4
-6
-8
-5
0
- 10
IOH [mA]
- 15
- 10
IOH [mA]
- 20
- 25
(6) “L” Level Output Voltage
VOL2 - IOL
VOL1 - IOL
1.0
1.0
(VCC2 = 4.5 V, TA = + 25 ˚C)
(VCC2 = 4.5 V, TA = + 25 ˚C)
0.8
VOL2 [V]
VOL1 [V]
0.8
0.6
0.4
0.4
0.2
0.2
0.0
0.0
0
2
4
6
IOL [mA]
44
0.6
8
10
0
5
15
10
IOL [mA]
20
25
MB89550A Series
(7) A/D Converter Characteristic Example
Liniarity error
3.0
2.5
2.0
(VCC2 = 5.0 V, FC = 12.5 MHz, TA = + 25 ˚C)
Error (LSB)
1.5
1.0
0.5
0.0
- 0.5
- 1.0
- 1.5
- 2.0
- 2.5
- 3.0
0
100
200
300
400
500
600
700
800
900
1000
700
800
900
1000
Conversion characteristics
Differential liniarity error
Error (LSB)
3.0
2.5
2.0
(VCC2 = 5.0 V, FC = 12.5 MHz, TA = + 25 ˚C)
1.5
1.0
0.5
0.0
- 0.5
- 1.0
- 1.5
- 2.0
- 2.5
- 3.0
0
100
200
300
400
500
600
Conversion characteristics
45
MB89550A Series
■ MASK OPTIONS
Part No.
MB89557A
MB89558A
MB89P558A
MB89PV550A
Specifying procedure
Specify when
ordering mask
Specify at time of order
Specify at time of order
-201 built-in multiplier
resistance
-201 built-in multiplier
resistance
-202 built-in step-up
circuit
-202 built-in step-up
circuit
-203 built-in step-up
circuit
-203 built-in step-up
circuit
No.
1
2
3
LCD drive power supply
• Built-in step-up circuit
• Built-in multiplier resistance
(for external connection)
Selectable
-201 segment selected
-201 segment selected
(SEG22-SEG31 selected) (SEG22-SEG31 selected)
Port/segment selection*1
P66 (SEG22) , P67 (SEG23) ,
P70 (SEG24) , P71 (SEG25) ,
P72 (SEG26) , P73 (SEG27) ,
P74 (SEG28) , P75 (SEG29) ,
P76 (SEG30) , P77 (SEG31)
Selectable
Main clock
Initial value*2 selection for oscillator stabilization wait period
(Fch = 12.5 MHz)
• 01 : 214/Fch
(approx. 1.31 ms)
• 10 : 217/Fch
(approx. 10.48 ms)
• 11 : 218/Fch
(approx. 20.97 ms)
Selectable
-202 segment selected
-202 segment selected
(SEG22-SEG31 selected) (SEG22-SEG31 selected)
-203 port selected
(P66, P67, P70-P77
selected)
-203 port selected
(P66, P67, P70-P77
selected)
218/Fch
(approx. 20.97 ms)
218/Fch
(approx. 20.97 ms)
*1 : This selection determines whether pins P66, P67, P70-P77 are used as I/O ports or as segment output pins.
If they are used as ports, then SEG22-SEG31 (Nch open drain) are not restricted by the condition for input
voltage to pins (VIN), namely that “VIN must be lower than the voltage at the V3 pin”.
*2 : This represents the initial value of the oscillator stabilization period select bit (SYCC : WT1, WT0) of the system
clock control register.
46
MB89550A Series
■ ORDERING INFORMATION
Part No.
Package
MB89558APFV-XXX
100-pin Plastic LQFP
(FPT-100P-M05)
MB89558APFT-XXX
100-pin Plastic TQFP
(FPT-100P-M18)
MB89P558A-201PFV versions without step-up
MB89P558A-202PFV with step-up 32 Segment
MB89P558A-203PFV with step-up 22 Segment
100-pin Plastic LQFP
(FPT-100P-M05)
MB89P558A-201PFT versions without step-up
MB89P558A-202PFT with step-up 32 Segment
MB89P558A-203PFT with step-up 22 Segment
100-pin Plastic TQFP
(FPT-100P-M18)
MB89PV550A-201CF versions without step-up
MB89PV550A-202CF with step-up 32Segment
MB89PV550A-203CF with step-up 22Segment
100-pin Ceramic MQFP
(MQP-100C-P02)
Remarks
47
MB89550A Series
■ PACKAGE DIMENSIONS
100-pin plasic LQFP
(FPT-100P-M05)
Note) Pins width and pins thickness include plating thickness.
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
100
26
1
25
C
0.20±0.05
(.008±.002)
0.08(.003)
M
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.145±0.055
(.0057±.0022)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
2000 FUJITSU LIMITED F100007S-3c-5
Dimensions in mm (inches)
(Continued)
48
MB89550A Series
100-pin plasic TQFP
(FPT-100P-M18)
Note) Pins width and pins thickness include plating thickness.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
75
0.145±0.055
(.006±.002)
51
76
50
0.08(.003)
Details of "A" part
1.10±0.10
(.043±.004)
INDEX
0˚~8˚
26
100
0.10±0.05
(.004±.002)
(Stand off)
"A"
0.25(.010)
LEAD No.
1
0.40(.016)
C
0.60±0.15
(.024±.006)
25
0.18±0.05
(.007±.002)
0.07(.002)
M
2000 FUJITSU LIMITED F100029S-c-2-3
Dimensions in mm (inches)
(Continued)
49
MB89550A Series
(Continued)
100-pin Ceramic MQFP
(MQP-100C-P02)
PIN No.1 INDEX
15.00±0.25 SQ
(.591±.010)
14.82±0.35 SQ
(.583±.014)
10.92(.430)
TYP
0.50±0.15
(.0197±.0060)
0.18±0.05
(.007±.002)
0.30(.012)
TYP
1.02±0.13
(.040±.005)
7.14(.281)
TYP
12.00(.472) 17.20(.667)
TYP
TYP
PAD No.1 INDEX
4.50(.177)SQ
TYP
+0.45
1.10 –0.25
12.00(.472)TYP
+.018
10.92(.430)
TYP
.043 –.010
17.20(.667)TYP
9.94(.392)MAX
0.15±0.05
(.006±.002)
C
1994 FUJITSU LIMITED M100002SC-2-2
Dimensions in mm (inches)
50
MB89550A Series
FUJITSU LIMITED
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FUJITSU LIMITED Printed in Japan