FUJITSU SEMICONDUCTOR DATA SHEET DS07-12509-6E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89120/120A Series MB89121/P131/123A/P133A/125A/P135A/ MB89PV130A ■ DESCRIPTION The MB89120 series is a line of single-chip microcontrollers containing a compact instruction set and a great variety of peripheral functions such as a timer, serial interface, and external interrupt. The MB89120A series is an extended variant of the MB89120, with a remote control transmission function and wake-up interrupt channels. ■ FEATURES • • • • • • • • • • • • • • F2MC-8L family CPU core Low-voltage operation Low current consumption (allowing for dual clock) Minimum execution time : 0.95 µs at 4.2 MHz 21-bit timebase counter I/O ports : Max. 36 ports External interrupts : 3 channels External interrupts (wake-up function) : 8 channels (only in the MB89120A series) 8-bit serial I/O : 1 channel 8-/16-bit timer/counter : 1 channel Built-in remote-control transmitting frequency generator (only in the MB89120A series) Low-power consumption modes (stop mode, sleep mode, watch mode) Package : QFP-48 CMOS technology ■ PACKAGE 48-pin plastic QFP (FPT-48P-M13) MB89120/120A Series ■ PRODUCT LINEUP Part number Item MB89121 MB89123A MB89125A Mass-produced products (Mask ROM products) Classification ROM size 4 K × 8 bits (internal mask ROM) RAM size 128 × 8 bits 8 K × 8 bits (internal mask ROM) CPU functions Ports Output ports (N-ch open-drain) Output ports (CMOS) I/O ports (CMOS) Total MB89P131 One-time products 8 K × 8 bits 4 K × 8 bits (Internal PROM to (Internal PROM 16 K × 8 bits be programmed to be programmed (internal mask with a generalwith a generalROM) purpose EPROM purpose EPROM programmer) programmer) 256 × 8 bits The number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Minimum interrupt processing time 128 × 8 bits : 136 : 8 bits : 1 to 3 bytes : 1, 8, 16 bits : 0.95 µs at 4.2 MHz : 8.57 µs at 4.2 MHz : 4 (All also serves as peripherals.) :8 : 24 (8 ports also serve as peripherals.) : 36 8-bit timer/counter × 2 channels or 16-bit event counter × 1 channel Timer/counter 8 bits LSB/MSB first selectable Serial I/O External interrupt 1 MB89P133A 3 Independent channels (edge selection, interrupt vector, source flag) Rising edge/falling edge/both edges selectable Also for wake-up from stop/sleep mode (edge detection is also permitted in stop mode) External interrupt 2 (wake-up function) 8 channels (only for level detection) Remote control transmitting frequency generator 1 channel (pulse width and frequency selectable by program) Standby mode Process Operating voltage* EPROM for use Sleep mode, stop mode, watch mode CMOS 2.2 V to 4.0 V (with the dual clock option) 2.2 V to 6.0 V (with the single clock option) 2.7 V to 6.0 V * : Varies with conditions such as operating frequencies. (See “■ ELECTRICAL CHARACTERISTICS”.) (Continued) 2 MB89120/120A Series (Continued) Part number MB89P135A MB89PV130A One-time PROM products Piggyback/evaluation product ROM size 16 K × 8 bits (internal PROM, to be programmed with general-purpose EPROM programmer) 32 K × 8 bits (external ROM) RAM size 512 × 8 bits 1 K × 8 bits Item Classification CPU functions The number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Minimum interrupt processing time : 136 : 8 bits : 1 to 3 bytes : 1, 8, 16 bits : 0.95 µs/4.2 MHz : 8.57 µs/4.2 MHz Ports Output ports (N-ch open-drain ports) Output ports (CMOS) I/O ports (CMOS) Total : 4 (All also serve as peripherals.) :8 : 24 (8 ports also serve as peripherals.) : 36 Timer/counter 8-bit timer/counter × 2 channels or 16-bit event counter × 1 channel 8 bits LSB/MSB first selectable Serial I/O External interrupt 1 3 independent channels (edge selection, interrupt vector, source flag) Rising/falling/both edges selectable Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) External interrupt 2 (wake-up function) 8 channels (only for level detection) Remote control transmitting frequency generator 1 channel (Pulse width and cycle selectable by program) Standby mode Sleep mode, stop mode, and clock mode Process Operating voltage EPROM for use CMOS 2.7 V to 6.0 V 2.7 V to 6.0 V MBM27C256A-20TVM 3 MB89120/120A Series ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB89121 MB89123A MB89125A MB89P133A MB89P131 × × × × × MB89P135A MB89PV130A FPT-48P-M13 MQP-48C-P01 Package × FPT-48P-M13 MQP-48C-P01 × : Available, × : Not available Note : Package details of OTPROM products and piggyback/evaluation products are common to those of MB89130/ 130A series. Refer to the MB89130/130A series data sheet for details. ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the one-time ROM product, verify its difference from the product that will actually be used. Take particular care on the following points : • The number of register banks available is different between the MB89121 and the MB89123A/125A/P135A/ PV130A. • The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption • When operated at low speed, a product with an OTPROM (EPROM) will consume more current than a product with a mask ROM. However, the same is current consumption in the sleep/stop mode is the same. (For more information, see “■ ELECTRICAL CHARACTERISTICS”.) • In the case of the MB89PV130A, added is the current consumed by the EPROM which is connected to the top socket. 3. Mask Options Functions that can be selected as options and how to designate these options vary with product. Before using options, check “■ MASK OPTIONS”. Take particular care on the following point : • Pull-up resistor can’t be set for P40 to P43 on the MB89P135A. • Options are fixed on the MB89PV130A. 4 MB89120/120A Series ■ PIN ASSIGNMENT 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 P36/INT2 P37/BZ/(RCO) P00/(INT20) P01/(INT21) P02/(INT22) P03/(INT23) P04/(INT24) P05/(INT25) P06/(INT26) P07/(INT27) P10 P11 P24 P23 P22 P21 P20 P17 VSS P16 P15 P14 P13 P12 AVCC RST MOD0 MOD1 X0 X1 VCC X0A X1A P27 P26 P25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 P40 P41 P42 P43 AVR AVSS P30/SCK P31/SO P32/SI P33/EC/SCO P34/TO/INT0 P35/INT1 (TOP VIEW) (FPT-48P-M13) Note : Parenthesized function is available only for the MB89120A series. 5 MB89120/120A Series ■ PIN DESCRIPTION Pin no. Pin name 5 X0 6 X1 8 X0A 9 X1A 3 MOD0 4 MOD1 Circuit type Function A Main clock crystal oscillator pins (max. 4.2 MHz) B Subclock crystal oscillator pins (for 32.768 kHz) C Operation mode select pins Connect these pins directly to VSS. D Reset I/O pin This port is of N-ch open-drain output type with pull-up resistor and a hysteresis input type. The internal circuit is initialized by the input of “L”. “L” is output from this pin by an internal reset source as optional setting. 2 RST 27 to 34 P07/ (INT27) to P00/ (INT20) I General-purpose I/O ports On the MB89120A series, these pins also serve as external interrupt input. External interrupt input is hysteresis input. 18, 20 to 26 P17 to P10 E General-purpose I/O ports 10 to 17 P27 to P20 G General-purpose output-only ports 42 P30/SCK F General-purpose I/O port Also serves as clock I/O for the 8-bit serial I/O interface. This port is of hysteresis input type. 41 P31/SO F General-purpose I/O port Also serves as a serial I/O data output. This port is of hysteresis input type. 40 P32/SI F General-purpose I/O port Also serves as a serial I/O data input. This port is of hysteresis input type. F General-purpose I/O port Also serves as the external clock input for the 8-bit timer/ counter. This port is of hysteresis input type. System clock output is optional. 39 P33/EC/SCO 38 P34/TO/INT0 F General-purpose I/O port Also serves as the overflow output and external interrupt input for the 8-bit timer/counter. This port is of hysteresis input type. 36, 37 P36/INT2, P35/INT1 F General-purpose I/O ports Also serve as an external interrupt input. These ports are of hysteresis input type. F General-purpose I/O port Also serves as a buzzer output. This port is of hysteresis input type. On the MB89120A series, the pin also serves as a remote control output. 35 P37/BZ/ (RCO) (Continued) 6 MB89120/120A Series (Continued) Pin no. Pin name Circuit type 45 to 48 P43 to P40 H N-ch open-drain output ports 7 VCC — Power supply pin 19 VSS — Power supply (GND) pin 1 AVCC — Power supply (GND) pin Use this pin at the same voltage as VCC. 44 AVR — Reference voltage input pin 43 AVSS — Power supply (GND) pin Use this pin at the same voltage as VSS. Function 7 MB89120/120A Series ■ I/O CIRCUIT TYPE Type Circuit Remarks • Crystal and ceramic oscillation type (main clock) • Cricuit for the MB89P133A/P131/P135A/PV130A • External clock input select versions of MB89121/ 123A/125A At an oscillation feedback resistor of approximately 1 MΩ / 5 V X1 X0 Standby control signal A • Crystal and ceramic oscillation type (main clock) • Crystal or ceramic oscillator select versions of MB89121/123A/125A At an oscillation feedback resistor of approximately 1 MΩ / 5 V X1 X0 Standby control signal • Crystal and ceramic oscillation type (sub clock) Circuit for the MB89121/123A/125A At an oscillation feedback resistor of approximately 4.5 MΩ / 5 V X1A X0A Standby control signal B • Crystal and ceramic oscillation type (sub clock) Circuit for the MB89P131/P133A/P135A/PV130A At an oscillation feedback resistor of approximately 4.5 MΩ / 5 V X1A X0A Standby control signal C R P-ch • Output pull-up resistor (P-ch) of approximately 50 kΩ / 5 V • Hysteresis input D N-ch (Continued) 8 MB89120/120A Series (Continued) Type Circuit Remarks • CMOS output • CMOS input • Pull-up resistor optional R P-ch P-ch E N-ch R • CMOS output • Hysteresis input • Pull-up resistor optional P-ch P-ch F N-ch • CMOS output P-ch G N-ch • N-ch open-drain output • Pull-up resistor optional R P-ch H P-ch N-ch • CMOS output • CMOS input • The interrupt input is a hysteresis input (available only on the MB89120A series) . • Pull-up resistor optional R P-ch P-ch I N-ch Interrupt input Only for the MB89120A series 9 MB89120/120A Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high- voltage pins, or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in “■ ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly, and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down resistor. 3. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 4. Power Supply Voltage Fluctuations Although operation is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 5. Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and release from stop mode. 6. Turning on the supply voltage (only for the MB89P135A) When the power supply is turned on if MB89P135A is used, power on sharply up to 2.0 V within 13 clock cycles after starting of oscillation. Further, various option may be set, if power supply up to keep this condition. 10 MB89120/120A Series ■ PROGRAMMING TO THE EPROM ON THE MB89P131 The MB89P131 is a one-time PROM version of the MB89121. 1. Features • 4-Kbyte PROM on chip • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below : Address Single chip EPROM mode (Corresponding addresses in the EPROM programmer) 0000H I/O Not available RAM 0000H Not available F000H Not available 7000H PROM 4 KB FFFFH EPROM 32 KB 7FFFH 3. Programming to the EPROM In EPROM mode the MB89P131 functions equivalent to the MBM27C256A. This allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter. Note, however, that the electronic signature mode cannot be used. • Programming procedure (1) Set the EPROM programmer to MBM27C256A. (2) Load program data into the EPROM programmer at 7000H to 7FFFH (note that addresses F000H to FFFFH while operating as a single chip correspond to 7000H to 7FFFH in EPROM mode) . (3) Program with the EPROM programmer. 11 MB89120/120A Series ■ PROGRAMMING TO THE EPROM ON THE MB89P133A The MB89P133A is a one-time PROM version of the MP89123A. 1. Features • 8-Kbyte PROM on chip • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below : Address Single chip EPROM mode (Corresponding addresses in the EPROM programmer) 0000H I/O RAM 0000H Not available E000H Not available 6000H PROM 8 KB FFFFH EPROM 32 KB 7FFFH 3. Programming to the EPROM In EPROM mode the MB89P133A functions equivalent to the MBM27C256A, This allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter. Note, however, that the MB89P133A cannot use the electronic signature mode. • Programming procedure (1) Set the EPROM programmer to MBM27C256A. (2) Load program data into the EPROM programmer at 6000H to 7FFFH (note that addresses E000H to FFFFH while operating as a single chip correspond to 6000H to 7FFFH in EPROM mode) . (3) Program with the EPROM programmer. 12 MB89120/120A Series ■ PROGRAMMING TO THE EPROM ON THE MB89P135A The MB89P135A is an OTPROM version of the MB89123A/125A. 1. Features • 16-Kbyte PROM on chip • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below. Address Single chip 0000H EPROM mode (Corresponding addresses on the EPROM programmer) I/O 0080H RAM 0280H Not available 8000H 0000H Vacancy (Read value FFH) Not available BFF0H 3FF0H Option area Not available BFF6H 3FF6H Vacancy (Read value FFH) Not available C000H 4000H PROM 16 KB FFFFH EPROM 16 KB 7FFFH 3. Programming to the EPROM In EPROM mode, the MB89P135A functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH while operating as a single chip correspond to 4000H to 7FFFH in EPROM mode) . (3) Load option data into the EPROM programmer at 3FF0H to 3FF6H. (4) Program with the EPROM programmer. 13 MB89120/120A Series 4. Setting OTPROM Options (MB89P135A Only) The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map : • OTPROM option bit map Address Bit 7 Bit 6 Bit 5 Bit 4 Clock mode selection Reset pin output 1 : Single clock 1 : Yes 0 : Dual 0 : No clock Vacancy Vacancy Vacancy Readable and writable Readable and writable Readable and writable 3FF1H P07 Pull-up 1 : Yes 0 : No P06 Pull-up 1 : Yes 0 : No P05 Pull-up 1 : Yes 0 : No P04 Pull-up 1 : Yes 0 : No 3FF2H P17 Pull-up 1 : Yes 0 : No P16 Pull-up 1 : Yes 0 : No P15 Pull-up 1 : Yes 0 : No 3FF3H P37 Pull-up 1 : Yes 0 : No P36 Pull-up 1 : Yes 0 : No Vacancy 3FF0H 3FF4H 3FF5H 3FF6H Bit 3 Bit 2 Power-on reset Bit 1 Oscillation stabilization time 1 : Yes 0 : No 00 : 22/FCH 10 : 216/FCH 01 : 212/FCH 11 : 218/FCH P03 Pull-up 1 : Yes 0 : No P02 Pull-up 1 : Yes 0 : No P01 Pull-up 1 : Yes 0 : No P00 Pull-up 1 : Yes 0 : No P14 Pull-up 1 : Yes 0 : No P13 Pull-up 1 : Yes 0 : No P12 Pull-up 1 : Yes 0 : No P11 Pull-up 1 : Yes 0 : No P10 Pull-up 1 : Yes 0 : No P35 Pull-up 1 : Yes 0 : No P34 Pull-up 1 : Yes 0 : No P33 Pull-up 1 : Yes 0 : No P32 Pull-up 1 : Yes 0 : No P31 Pull-up 1 : Yes 0 : No P30 Pull-up 1 : Yes 0 : No Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Readable and writable Note : Each bit is set to “1” as the initialized value, therefore the pull-up option is not selected. 14 Bit 0 MB89120/120A Series ■ HANDLING MB89P131/P133A/P135A 1. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure. Program, verify Aging +150 °C, 48 h Data verification Assembly 2. Programming Yield Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test. For this reason, a programming yeild of 100% cannot be assured at all times. 3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer Part no. Package Compatible socket adapter Sun Hayato Co., Ltd. Recommended programmer manufacturer and programmer name Minato Electronics Inc. 1890A MB89P131PF MB89P133APFM QFP-48 ROM-48QF2-28DP-8L Recommended Inquiry : Sun Hayato Co., Ltd. : TEL : (81) -3-3986-0403 FAX : (81) -3-5396-9106 Minato Electronics Inc. : TEL : USA (1) -916-348-6066 JAPAN (81) -45-591-5611 15 MB89120/120A Series ■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TVM 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer : Sun Hayato Co., Ltd.) listed below : Package Adapter socket part number LCC-32 (Square) ROM-32LC-28DP-S Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403 FAX (81) -3-5396-9106 3. Memory Space Memory space in each mode, such as 32-Kbyte PROM is diagrammed below. Address Single chip Corresponding addresses on the EPROM programmer 0000 H I/O 0080 H RAM 0480 H Not available 8000 H 0000 H PROM 32 KB FFFFH EPROM 32 KB 7FFFH 4. Programming to the EPROM (1) (2) (3) 16 Set the EPROM programmer for the MBM27C256A. Load program data into the EPROM programmer at 0000H to 7FFFH. Program with the EPROM programmer. MB89120/120A Series ■ BLOCK DIAGRAM X0 X1 Main clock oscillator Timebase timer Clock controller Reset circuit (WDT) X0A X1A RST 8 8-bit timer/counter P34/TO/INT0 8-bit timer/counter P33/EC/SCO External interrupt∗ (Wake-up) 8 Port 2 External interrupt P20 to P27 P30/SCK P32/SI P31/SO 8-bit serial I/O P10 to P17 Port 3 P00/(INT20) to 8 P07/(INT27) Port 0/1 CMOS I/O port Internal bus Subclock oscillator (32.768 kHz) P35/INT1 Remote control transmission frequency generator∗ CMOS output port P36/INT2 Buzzer output P37/BZ/(RCO) CMOS I/O port N-ch open-drain output port F 2 M C- 8L CPU Port 4 RAM 4 P40 to P43 RO M The other pins MOD0, MOD1, VCC, VSS AVCC, AVR, AVSS * : Only the MB89120A series has wake-up interrupt inputs and remote control transmission. Note : Parenthesized pins are available only with the MB89120A series. 17 MB89120/120A Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89120/A series offer 64 Kbytes of memory for storing all of I/O, data, and program areas. The I/O area is allocated from the lowest address. The data area is allocated immediately above the I/ O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is allocated from exactly the opposite end of I/O area, that is, near the highest address. The tables of interrupt reset vectors and vector call instructions are allocated from the highest address with the program area. The memory space of the MB89120/A series is structured as illustrated below : Memory Space MB89123A MB89P133A MB89121 MB89P131 0000 H 0000 H 0000 H I/O I/O 007F H 0080 H 007F H 0080 H Not available 00BF H 00C0 H 0100 H RAM Not available DFFFH E000 H EFFFH F000 H ROM RAM 1 KB 00FF H 0100 H Register Register 01FF H 0200 H BFFFH C000 H Not available RAM 512 B Register Not available I/O 007F H 0080 H 00FF H 0100 H 017F H 0180 H 017F H 0180 H 0000 H 007F H 0080 H RAM Register MB89PV130A I/O I/O 0100 H 0100 H MB89P135A 0000 H 007F H 0080 H RAM Register 013F H 0140 H MB89125A 01FF H 0200 H 027F H 0280 H Vacancy BFFFH C000 H 047F H 0480 H 7FFF H 8000 H External ROM 32 KB ROM 16 KB ROM ROM FFFFH 18 FFFFH FFFFH FFFFH Vacancy FFFFH MB89120/120A Series 2. Registers The F2MC-8L family has two types of registers; dedicated hardware registers and general-purpose memory registers. The following dedicated registers are provided : Program counter (PC) : Accumulator (A) : A 16-bit-long register for indicating the instruction storage positions A 16-bit-long temporary register for arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T) : A 16-bit-long register which is used for arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX) : A 16-bit-long register for index modification Extra pointer (EP) : A 16-bit-long pointer for indicating a memory address Stack pointer (SP) : A 16-bit-long pointer for indicating a stack area Program status (PS) : A 16-bit-long register for storing a register pointer, a condition code Initial value 16 bits FFFDH : Program counter PC A : Accumulator T : Temporary accumulator Indeterminate IX : Index register Indeterminate EP : Extra pointer Indeterminate SP : Stack pointer Indeterminate PS : Program status Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are Indeterminate. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR) (see the diagram below) . Structure of the Program Status Register 15 PS 14 13 12 11 10 9 8 Vacancy Vacancy Vacancy RP RP 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR 19 MB89120/120A Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes "0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and bits for control of CPU operations at the time of an interrupt. H-flag : I-flag : IL1, 0 : N-flag : Z-flag : V-flag : C-flag : 20 Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared “0” otherwise. This flag is for decimal adjustment instructions. Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when the flag is cleared to “0”. Cleared to “0” at the reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low Set to “1” if the MSB becomes “1” as the result of an arithmetic operation. Cleared to “0” otherwise. Set to “1” when an arithmetic operation results in 0. Cleared to “0” otherwise. Set to “1” if the complement on “2” overflows as a result of an arithmetic operation. Cleared to “0” if the overflow does not occur. Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction. MB89120/120A Series The following general-purpose registers are provided : General-purpose registers : An 8-bit-long register for storing data The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 8 banks can be used on the MB89121/P131, and a total of 16 banks can be used on the MB89123A/125A/P133A and a total of 32 banks can be used on the MB89P135A/PV130A. The bank currently in use is indicated by the register bank pointer (RP) . Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 8 banks (MB89121/P131) 16 banks (MB89123A/125A/133A) 32 banks (MB89P135A/PV130A) Memory area 21 MB89120/120A Series ■ I/O MAP Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H Vacancy 06H Vacancy 07H (R/W) SYCC System clock control register 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog control register 0AH (R/W) TBTC Time-base timer control register 0BH (R/W) WPCR Watch prescaler control register 0CH (R/W) PDR3 Port 3 data register 0DH (W) DDR3 Port 3 data direction register 0EH (R/W) PDR4 Port 4 data register 0FH (R/W) BZCR Buzzer register 10H Vacancy 11H Vacancy 12H (R/W) SCGC 13H Peripheral control clock register Vacancy 14H (R/W) RCR1 Remote control transmission control register 1* 15H (R/W) RCR2 Remote control transmission control register 2* 16H Vacancy 17H Vacancy 18H (R/W) T2CR Timer 2 control register 19H (R/W) T1CR Timer 1 control register 1AH (R/W) T2DR Timer 2 data register 1BH (R/W) T1DR Timer 1 data register 1CH (R/W) SMR1 Serial mode register 1DH (R/W) SDR1 Serial data register 1EH Vacancy 1FH Vacancy (Continued) 22 MB89120/120A Series (Continued) Address Read/write Register name Register description 20H Vacancy 21H Vacancy 22H Vacancy 23H (R/W) EIC1 External interrupt control register 1 24H (R/W) EIC2 External interrupt control register 2 25H Vacancy 26H to 31H Vacancy 32H (R/W) EIE2 External interrupt 2 enable register* 33H (R/W) EIF2 External interrupt 2 flag register* 34H to 7BH Vacancy 7CH (W) ILR1 Interrupt level register 1 7DH (W) ILR2 Interrupt level register 2 7EH (W) ILR3 Interrupt level register 3 7FH Vacancy * : Only in the MB89120A series Note : Do not use vacancies. 23 MB89120/120A Series ■ ELECTRICAL CARACTERISTICS 1. Absolute Maximum Ratings Parameter (AVSS = VSS = 0.0 V) Symbol Value Unit Remarks Min. Max. VCC AVCC AVR VSS − 0.3 VSS + 7.2 V Use VCC, AVCC , and AVR set to the same voltage. VPP VSS − 0.6 VSS + 13.0 V MOD1 pin on the MB89P131/P133A/P135A Input voltage VI VSS − 0.3 VCC + 0.3 V Output voltage VO VSS − 0.3 VCC + 0.3 V “L” level maximum output current IOL 10 mA “L” level average output current IOLAV 4 mA “L” level total maximum output current ΣIOL 100 mA ΣIOLAV 20 mA IOH −10 mA “H” level average output current IOHAV −2 mA “H” level total maximum output current ΣIOH −30 mA “H” level total average output current ΣIOHAV −10 mA Power consumption PD 200 mW Operating temperature TA −40 +85 °C Tstg −55 +150 °C Power supply voltage Program voltage “L” level total average output current “H” level maximum output current Storage temperature Avarage value (operating current × operating rate) Avarage value (operating current × operating rate) Avarage value (operating current × operating rate) Avarage value (operating current × operating rate) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 24 MB89120/120A Series 2. Recommended Operating Conditions Parameter Power supply voltage Operating temperature Symbol (AVSS = VSS = 0.0 V) Value Unit Max. 2.2* 6.0* V Normal operation assurance range Applied to “MB89P131/P133A/P135A/PV130A, and single-clock MB89121/123A/125A*” 2.7* 6.0* V Normal operation assurance range Applied to “ Dual-clock MB89121/123A/125A*” 1.5 6.0 V Retains the RAM state in stop mode −40 +85 °C VCC TA Remarks Min. * : These values vary with the operating conditions. See “ Operating Voltage vs. Main Clock Operating Frequency.” WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 25 MB89120/120A Series • Operating Voltage vs. Main Clock Operating Frequency Dual-clock MB89121/123A/125A Operating voltage (V) 6 5 4 Operation assurance range 3 2 1 1 2 3 4 Main clock operating frequency (Instruction cycle time of 4/FCH) (MHz) 4.0 Minimum execution time (µs) 2.0 1.0 MB89P131/P133A/P135A/PV130A, and single-clock MB89121/123A/125A Operating voltage (V) 6 5 Operation assurance range 4 3 2 1 1 2 3 4 Main clock oprating frequency (Instruction cycle time of 4/FCH) (MHz) 4.0 Minimum execution time (µs) 2.0 1.0 Note : The shaded area is assured only for the MB89121/123A/125A (instruction cycle time of 4/FCH) . 26 MB89120/120A Series 3. DC Characteristics Parameter Symbol VIH “H” level input voltage “L” level input voltage Open-drain output pin applied voltage “H” level output voltage “L” level output voltage Input leakage current (Hi-z output leakage current) Pull-up resistance Pin P00 to P07, P10 to P17 (AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Value Condition Unit Remarks Min. Typ. Max. 0.7 VCC VCC + 0.3 V VIHS RST, P30 to P37, INT20 to INT27 0.8 VCC VCC + 0.3 V VIL P00 to P07, P10 to P17 VSS − 0.3 0.3 VCC V VILS RST, P30 to P37, INT20 to INT27 VSS − 0.3 0.2 VCC V VD P40 to P43 VSS − 0.3 VCC + 0.3 V VOH P00 to P07, P10 to P17, P20 to P27, P30 to P37 IOH = −2.0 mA 2.4 V VOL P00 to P07, P10 to P17 P20 to P27, P30 to P37, P40 to P43 IOL = 1.8 mA 0.4 V VOL2 RST IOL = 4.0 mA 0.6 V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P43, MOD0, MOD1 0.45 V < VI < VCC ±5 µA P00 to P07, P10 to P17, P30 to P37, P40 to P43, RST VI = 0.0 V 25 50 100 kΩ ILI RPULL INT20 to INT27 are available only in the MB89120A series. INT20 to INT27 are available only in the MB89120A series. Without pull-up resistor (Continued) 27 MB89120/120A Series (Continued) Parameter Symbol Pin MB89121/ 123A/125A 4 7 mA 6 10 MB89P131/ mA P133A/ P135A 2 5 mA 50 100 µA 1 3 MB89P131/ mA P133A/ P135A VCC = 3.0 V FCL = 32.768 kHz Subclock sleep mode 25 50 µA ICCT VCC = 3.0 V FCL = 32.768 kHz • Watch mode • Main clock stop mode at dual clock system 15 µA ICCH TA = +25 °C • Subclock stop mode • Main clock stop mode at single clock system 1 µA f = 1 MHz 10 pF VCC = 5.0 V FCH = 4.00 MHz tinst*2 = 1.0 µs ICC1 VCC = 5.0 V FCH = 4.00 MHz Main sleep mode tinst*2 = 1.0 µs ICCS1 VCC = 3.0 V FCL = 32.768 kHz Subclock mode ICCL Power supply current*1 ICCLS Input capacitance (AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Value Condition Unit Remarks Min. Typ. Max. CIN VCC (External clock operation) Other than AVCC, AVSS, VCC, and VSS MB89121/ 123A/125A *1 : The measurement conditions of power supply current is external clock. (VCC = 5.0 V, VCC = 3.0 V) *2 : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics.” 28 MB89120/120A Series 4. AC Characteristics (1) Reset Timing Parameter RST “L” pulse width Symbol (VCC = +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Value Condition Unit Remarks Min. Max. tZLZH 48 tHCYL* ns * : tHCYL is the oscillation cycle (1/FCH) input to the X0. tZLZH RST 0.8 VCC 0.2 VCC 0.2 VCC (2) Power-on Reset Parameter Power supply rising time Symbol Condition (AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Value Unit Remarks Min. Max. tR 50 ms Power-on reset function only 1 ms Due to repeated operations Power supply cut-off time tOFF Note : Make sure that power supply rises within the oscillation stabilization time selected. When the main clock is operating at FCH = 3 MHz and the oscillation stabilization time select option has been set to 212/FCH, for example, the oscillation settling time is 1.4 ms and accordingly the maximum value of power supply rising time is about 1.4 ms. Keep in mind that rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tOFF tR 2.0 V VCC 0.2 V 0.2 V 0.2 V 29 MB89120/120A Series (3) Clock Timings (VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin FCH Value Unit Remarks Min. Typ. Max. X0, X1 1 4.2 MHz Main clock FCL X0A, X1A 32.768 kHz tHCYL X0, X1 238 1000 ns Main clock tLCYL X0A, X1A 30.5 µs Subclock Input clock pulse width PWH1 PWL1 X0 72 ns External clock Input clock rising/falling time tCR1 tCF1 X0 24 ns External clock Clock frequency Clock cycle time Subclock X0, X1 Timings and Conditions of Applied Voltage tHCYL 0.8 VCC 0.2 VCC X0 PWH1 PWL1 tCF1 tCR1 Main Clock Conditions of Applied Voltage When a crystal or ceramic resonator is used X0 X1 When an external clock is used X0 X1 FCH C0 30 C1 Open FCH MB89120/120A Series X0A, X1A Timings and Conditions of Applied Voltage tLCYL 0.8 VCC X0A Subclock Conditions of Applied Voltage When a crystal or ceramic resonator is used X0A X1A Single-clock option is used X0A X1A Open Rd FCL C0 C1 (4) Instruction Cycles Parameter Instruction cycle (minimum execution time) (VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol tinst Value (typical) 4/FCH, 8/FCH, 16/FCH, 64/FCH 2/FCL Unit Remarks µs (4/FCH) tinst = 1.0 µs when operating at FCH = 4 MHz µs tinst = 61.036 µs when operating at FCL = 32.768 kHz 31 MB89120/120A Series (5) Recommended Resonator Manufacturers Sample Application of Piezoelectric Resonator (FAR Series) for Main Clock Oscillation Circuit (Only in the MB89120A Series) X0 X1 R C1∗2 FAR∗1 C2∗2 *1 : FUJITSU MEDIA DEVICE LIMITED FAR part number Frequency Dumping (built-in capacitor type) (MHz) resistor FAR-C4CC-02000-L00 2.00 FAR-C4 A-03580- 01 3.58 FAR-C4CB-04000-M00 4.00 Temperature Loading characteristics of FAR frequency capacitors*2 (TA = −20 °C to +60 °C) 1000 510 — Inquiry : FUJITSU MEDIA DEVICES LIMITED 32 Initial deviation of FAR frequency (TA = +25 °C) ±0.5% ±0.5% Built-in MB89120/120A Series Sample Application of Ceramic Resonator for Main Clock Oscillation Circuit X0 X1 R ∗ C1 C2 • Mask ROM products Resonator Frequency (MHz) C1 (pF) C2 (pF) R (kΩ) Kyocera Corporation KBR-4.0MKS 4.00 33 33 Not required Matsushita Electronic Components EFOV4004B 4.00 Built-in Built-in 1.5 CSBF1000J 1.00 100 100 6.8 Built-in Built-in Not required 100 100 Not required Built-in Built-in Not required Resonator manufacturer* Murata Mfg. Co. Ltd. CSTCS4.00MG800 CSA4.00MG040 CST4.00MGW040 4.00 Inquiry : Kyocera Corporation • AVX Corporation North American Sales Headquarters : TEL (803) 448-9411 • AVX Limited European Sales Headquarters : TEL (01252) 770000 • AVX/Kyocera H.K. Ltd. Asian Sales Headquarters : TEL 363-3303 Matsushita Electronic Components Co., Ltd. • Ceramic Division : TEL 81-6-908-1101 Murata Mfg Co., Ltd. • Murata Electronics North America, Inc. : TEL 1-404-436-1300 • Murata Europe Management GmbH : TEL 49-911-66870 • Murata Electronics Singapore (Pte.) Ltd. : TEL 65-758-4233 33 MB89120/120A Series Sample Application of Crystal Resonator for Subclock Oscillation Circuit X0A X1A Rd ∗ C1 C2 • Mask ROM product Resonator manufacturer* SII Resonator Frequency (kHz) C1 (pF) C2 (pF) Rd (kΩ) DS-VT-200 32.768 24 24 680 Inquiry : SII Seiko Instruments Inc. (Japan) : TEL 81-43-211-1219 Seiko Instruments U.S.A. Inc. : TEL 310-517-7770 Seiko Instruments GmbH : TEL 49-6102-297-122 34 MB89120/120A Series (6) Serial I/O Timings Parameter Symbol (VCC = +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin Condition Unit Remarks Min. Max. Serial clock cycle time tSCYC SCK SCK ↓ → SO time tSLOV SCK, SO Valid SI → SCK ↑ tIVSH SI, SCK SCK ↑ → Valid SI hold time tSHIX SCK, SI Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH Internal clock operation SCK External clock operation 2 tinst* µs −200 200 ns 200 ns 200 ns tinst* µs tinst* µs 0 200 ns SCK ↓ → SO time tSLOV SCK, SO Valid SI → SCK ↑ tIVSH SI, SCK 200 ns SCK ↑ → Valid SI hold time tSHIX SCK, SI 200 ns * : For information on tinst, see “ (4) Instruction Cycles.” Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SO 0.8 V tIVSH tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC SI External Shift Clock Mode tSLSH tSHSL SCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV SO 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC SI 35 MB89120/120A Series (7) Peripheral Input Timings Parameter Symbol tILIH Peripheral input “H” pulse width Peripheral input “L” pulse width tIHIL (VCC = +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin Unit Remarks Min. Max. EC, INT0 to INT2 2 tinst* µs 2 tinst* µs * : For information on tinst, see “ (4) Instruction Cycle.” tIHIL EC INT0 to INT2 0.8 VCC 0.2 VCC 36 tILIH 0.2 VCC 0.8 VCC MB89120/120A Series ■ EXAMPLE CHARACTERISTICS (1) “L” Level Output Voltage (2) “H” Level Output Voltage VCC − VOH vs. IOH VOL vs. IOL VOL (V) VCC − VOH (V) VCC = 2.5 V 1.1 TA = +25 °C VCC = 2.2 V 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 1 2 3 4 5 VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 6 7 8 9 10 IOL (mA) (3) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) TA = +25 °C 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1.00 2.00 3.00 4.00 VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V −2.5 −3.0 IOH (mA) VIN vs. VCC 4.5 0 .00 VCC = 2.5 V (4) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) VIN vs. VCC VIN (V) 5.0 1.1 TA = +25 °C VCC = 2.2 V 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 −.5 −1.0 −1.5 −2.0 5.00 6.00 7.00 VCC (V) VIN (V) 5.0 4.5 TA = +25 °C 4.0 VIHS 3.5 3.0 2.5 2.0 VILS 1.5 1.0 0.5 0 .00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 VCC (V) VIHS : Threshold when input voltage in hysteresis characteristics is set to “H” level VILS : Threshold when input voltage in hysteresis characteristics is set to “L” level (5) Pull-up Resistance RPULL vs. VCC RPULL (kΩ) 1000 TA = +25 °C 300 100 50 10 0 1 2 3 4 5 6 7 VCC (V) 37 MB89120/120A Series (6) Power Supply Current ICC1 vs. VCC ICC (mA) 5.0 4.5 4.0 ICCS1 vs. VCC Divide by 4 (ICC1) FCH = 4.0 MHz TA = +25 °C ICCS (mA) 3.0 FCH = 4.0 MHz TA = +25 °C 2.5 3.5 Divide by 4 (ICCS1) 2.0 Divide by 64 3.0 2.5 1.5 2.0 Divide by 64 1.5 1.0 1.0 0.5 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) ICCLS vs. VCC ICCL vs. VCC ICCL (µA) 200 TA = +25 °C 180 ICCLS (µA) 50 160 40 140 35 120 30 100 25 80 20 60 15 40 10 20 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) TA = +25 °C 45 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) ICCH vs. VCC ICCT vs. VCC ICCT (µA) 30 TA = +25 °C 25 20 ICCH (µA) 2.0 TA = +25 °C 1.8 1.6 1.4 1.2 15 1.0 0.8 10 5 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) 38 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) MB89120/120A Series ■ INSTRUCTIONS (136 INSTRUCTIONS) Execution instructions can be divided into the following four groups: • Transfer • Arithmetic operation • Branch • Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri × (×) (( × )) Instruction Symbols Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH prior to the instruction executed. • 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 39 MB89120/120A Series Table 2 Mnemonic Transfer Instructions (48 instructions) ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Note: During byte transfer to A, T ← A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 40 MB89120/120A Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A (Continued) 41 MB89120/120A Series (Continued) Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ # Operation 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 42 ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 TL TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Other Instructions (9 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 L MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel 9 A B C D E F A SUBC A XCH A, T XOR A AND A OR A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS R7 R6 R5 R4 R3 R2 R1 R0 DEC DEC DEC DEC DEC DEC DEC DEC R7 R6 R5 R4 R3 R2 R1 R0 rel rel rel rel CALLV BLT #7 rel CALLV BGE #6 rel CALLV BZ #5 CALLV BNZ #4 rel CALLV BN #3 CALLV BP #2 CALLV BC #1 CALLV BNC #0 rel CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP ADDC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP 8 A A SETC MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP CMPW CMP JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A 7 F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX E 6 D MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP C 5 B CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 A A DIVU SETI 9 4 8 RORC 7 3 6 ROLC A 5 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 4 2 A RETI 3 MULU RET 2 1 SWAP 1 NOP 0 0 H MB89120/120A Series ■ INSTRUCTION MAP 43 MB89120/120A Series ■ MASK OPTIONS Part number No. Specifying procedure MB89121 MB89123A MB89125A MB89P131 MB89P133A Specify when ordering masking MB89P135A MB89PV130A Set with EPROM programmer Specification impossible 1 Pull-up resistors • P00 to P07, P10 to P17, • P30 to P37, P40 to P43 Selectable by pin All pins fixed to Selectable by pin (P40 to P43 must be set to without no pull-up resisa pull-up resistor.) tor optional 2 Power-on reset Power-on reset provided No power-on reset Selectable Selectable Selectable With power-on reset 3 Selection of oscillation stabilization wait time • The oscillation stabilization wait time initial value is selectable from 4 types given below. Selectable 0 : Oscillation stabilization 22/FCH 1 : Oscillation stabilization 212/FCH 2 : Oscillation stabilization 216/FCH 3 : Oscillation stabilization 218/FCH Selectable Selectable Oscillation stabilization 218/FCH 4 Reset pin output • Reset output provided • No reset output Selectable Selectable Selectable With reset output 5 Clock mode selection • Single-clock mode • Dual-clock mode Selectable Selectable Selectable Dual-clock mode 6 Main clock oscillation circuit type • External clock input Selectable • Oscillation resonator Not required*1 7 Peripheral control clock output function*2 • Not used • Used Not required*3 Selectable *1 : Both external clock and oscillation resonator is usable on the one-time product. *2 : “Used” must be selected when P33 (39 pin) is used as SCO for the peripheral control clock output. *3 : The peripheral control clock function can be used only by software. 44 MB89120/120A Series ■ MB89P131/P133A STANDARD OPTIONS No. Product option MB89P131-101 MB89P133A-201 1 Pull-up resistor Not provided for any port Not provided for any port 2 Power-on reset Provided Provided 3 Selection of oscillation stabilization 2 : Oscillation stabilization 216/FCH 2 : Oscillation stabilization 216/FCH time 4 Reset pin output Provided Provided 5 Clock mode selection Dual-clock mode Dual-clock mode ■ ORDERING INFORMATION Part number MB89121PFM MB89123APFM MB89125APFM MB89P131PFM-101 MB89P133APFM-201 MB89P135APFM MB89PV130ACF-ES Package Remarks 48-pin Plastic QFP (FPT-48P-M13) 48-pin Ceramic MQFP (MQP-48C-P01) 45 MB89120/120A Series ■ PACKAGE DIMENSION 48-pin Plastic QFP (FPT-48P-M13) 13.10±0.40 SQ (.516±.016) 10.00±0.20 SQ (.394±.008) 36 2.35(.093)MAX (Mounting height) 0(0)MIN (STAND OFF) 25 37 Details of "A" part 24 0.15(.006) 8.80 (.346) REF INDEX 11.50±0.30 (.453±.012) 0.20(.008) 0.18(.007)MAX 0.53(.021)MAX "A" 48 13 Details of "B" part LEAD No. 1 0.80(.0315)TYP 12 0.30±0.10 (.012±.004) 0.16(.006) M 0.15±0.05 (.006±.002) 0~10° "B" 0.80±0.30 (.031±.012) 0.10(.004) C 1994 FUJITSU LIMITED F48023S-1C-1 Dimensions in mm (inches) 46 MB89120/120A Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0008 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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