FUJITSU MB89PV170ACF

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12518-8E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89170/170A/170L Series
MB89173/P173/174A/P175A/PV170A
MB89173L/174L
■ DESCRIPTION
The MB89170/170A/170L series has been developed as a general-purpose version of the F2MC*-8L family
consisting of proprietary 8-bit, single-chip microcontrollers.
In addition to a compact instruction set, the microcontrollers contain a great variety of peripheral functions such
as timers, a serial interface, a DTMF generator, and external interrupts, making it suitable for circuit control
such as required in telephones.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8L family CPU core
• Maximum memory space: 64 Kbytes
• Minimum execution time/interrupt processing time
MB89170 series: 1.1 µs/10 µs (at 3.58 MHz oscillation)
MB89170A/170L series: 0.6 µs/5.4 µs (at 7.16 MHz oscillation)
• Dual-clock control system (MB89170/170A series only)
• I/O ports: max. 37 ports
• 21-bit timebase counter
• Watch prescaler (MB89170/170A series only)
• Watchdog timer
• 8/16-bit timer/counter: 1 channel
(Continued)
■ PACKAGE
48-pin Plastic QFP
48-pin Ceramic MQFP
(FPT-48P-M16)
(MQP-48C-P01)
MB89170/170A/170L Series
(Continued)
• 8-bit serial I/O: 1 channel
• DTMF generator (MB89170/170A series only)
Selectable oscillation frequency (MB89170A series only)
• External interrupt 1: 3 channels
Three channels are independent and capable of using for wake-up from low-power consumption modes (with
an edge detection function).
• External interrupt 2 (wake-up): 8 channels
Eight channels are independent and capable of using for wake-up from low-power consumption modes (with
an “L” level detection function).
• Low-power consumption modes(stop mode, sleep mode, watch mode, and subclock mode)
• CMOS technology
2
MB89170/170A/170L Series
■ PRODUCT LINEUP
Part number
Item
MB89173
MB89P173
MB89174A
MB89P175A
MB89PV170A
Classification
Mass-produced
product
(mask ROM
product)
One-time PROM Mass-produced
product
product
(EPROM product) (mask ROM
product)
One-time PROM Piggyback/
evaluation
product
(EPROM product) product (for
evaluation and
development)
ROM size
8 K × 8 bits
(internal mask
ROM)
8 K × 8 bits
12 K × 8 bits
(internal PROM,
(internal mask
to be programmed ROM)
with generalpurpose EPROM
programmer)
16 K × 8 bits
(internal PROM,
to be programmed
with generalpurpose EPROM
programmer)
RAM size
CPU functions
384 × 8 bits
The number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
1.1 to 17.6 µs at 3.58 MHz, 61 µs at 32.768 kHz
Interrupt processing time:
10 to 160 µs at 3.58 MHz, 562.5 µs at 32.768 kHz
Ports
512 × 8 bits
32 K × 8 bits
(external ROM)
1 K × 8 bits
136
8 bits
1 to 3 bytes
1, 8, 16 bits
Minimum instruction execution time:
0.6 to 9.6 µs at 7.16 MHz, 61 µs at 32.768 kHz
Interrupt processing time:
5.4 to 86.4 µs at 7.16 MHz, 562.5 µs at 32.768 kHz
Output ports (N-ch open-drain):
Output ports (CMOS):
I/O ports (CMOS):
Total:
5
8
24 (16 ports also serve as peripherals.)
37
8/16-bit timer/
counter
8 bits × 2 ch or 16 bits × 1 ch, capable of rectangular wave output
One clock selectable from four operation clocks
(one external shift clock, three internal shift clocks: 2.2 µs, 35.2 µs, 563.2 µs; when operating at 3.58 MHz)
8-bit serial I/O
8 bits
LSB/MSB first selectable
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 2.2 µs, 8.8 µs, 35.2 µs; when operating at 3.58 MHz)
DTMF generator
All ITU-T (the old name: CCITT)
tones selectable as output
Fixed to oscillation frequency(3.58 MHz)
All ITU-T (the old name: CCITT) tones selectable as output
Selectable oscillation frequency(3.58 MHz or 7.16 MHz)
External interrupt 1
3 independent channels (selectable edge, interrupt vector, source flag)
Rising/falling/both edges selectable
Used also for wake-up from the watch/stop/sleep mode.
(Edge detection is also permitted in the watch/stop mode.)
External interrupt 2
(wake-up)
8 independent channels (“L” level interrupt)
Used also for wake-up from the watch/stop/sleep mode.
(Edge detection is also permitted in the watch/stop mode.)
Standby mode
Sleep mode, stop mode, watch mode, and subclock mode
Process
Operating voltage*
EPROM for use
CMOS
2.2 V to 6.0 V
2.7 V to 6.0 V
2.2 V to 6.0 V
2.7 V to 6.0 V
MBM27C256A
-20TVM
* : Varies with conditions such as the operating frequency and the assurance range for the DTMF generator.(See
“■ Electrical Characteristics.”)
3
MB89170/170A/170L Series
Part number
Item
MB89173L
Classification
MB89P174L
Mass-produced product
(mask ROM product)
ROM size
8 K × 8 bits
(internal mask ROM)
12 K × 8 bits
(internal mask ROM)
RAM size
384 × 8 bits
512 × 8 bits
CPU functions
The number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
Minimum instruction execution time:
Interrupt processing time:
Ports
Output ports (N-ch open-drain):
Output ports (CMOS):
I/O ports (CMOS):
Total:
0.6 to 9.6 µs at 7.16 MHz,
5.4 to 86.4 µs at 7.16 MHz,
5
8
24 (16 ports also serve as peripherals.)
37
8/16-bit timer/
counter
8 bits × 2 ch or 16 bits × 1 ch, capable of rectangular wave output
One clock selectable from four operation clocks
(one external shift clock, three internal shift clocks: 2.2 µs, 35.2 µs, 563.2 µs; when operating at 3.58 MHz)
8-bit serial I/O
8 bits
LSB/MSB first selectable
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 2.2 µs, 8.8 µs, 35.2 µs; when operating at 3.58 MHz)
DTMF generator

External interrupt 1
3 independent channels (selectable edge, interrupt vector, source flag)
Rising/falling/both edges selectable
Used also for wake-up from the stop/sleep mode.
(Edge detection is also permitted in the stop mode.)
External interrupt 2
(wake-up)
8 independent channels (“L” level interrupt)
Used also for wake-up from the stop/sleep mode.
(Edge detection is also permitted in the stop mode.)
Standby mode
Process
Operating voltage*
Sleep mode, stop mode
CMOS
2.2 V to 6.0 V
EPROM for use
* : Varies with conditions such as the operating frequency and the assurance range for the DTMF generator.(See
“■ ELECTRICAL CHARACTERISTICS.”)
4
MB89170/170A/170L Series
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89173
MB89P173
MB89174A
MB89P175A
MB89173L
MB89174L
Package
MB89PV170A
×
FPT-48P-M16
MQP-48C-P01
: Available
×
× : Not available
Note: For more information about each package, see “■ Package Dimensions.”
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
2. Current Consumption
In the case of the MB89PV170A, added is the current consumed by the EPROM which is connected to the top
socket.
3. Mask Options
Functions that can be selected as options and how to designate these options vary with the product.
Before using options, check “■ Mask Options.”
Take particular care on the following points:
• Pull-up resistor option cannot be set for P40 to P44 on the MB89P175A.
• Each option is fixed on the MB89PV170A.
5
MB89170/170A/170L Series
■ PIN ASSIGNMENT
48
47
46
45
44
43
42
41
40
39
38
37
P40
P41
P42
P43
P44
VSS
P30/SCK
P31/SO
P32/SI
P33/EC
P34/TO/INT0
P35/INT1
(Top view)
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
MB89170/170A series
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
P36/INT2
P37/BZ
P00/INT20
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10
P11
36
35
34
33
32
31
30
29
28
27
26
25
P36/INT2
P37/BZ
P00/INT20
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10
P11
P24
P23
P22
P21
P20
P17
VSS
P16
P15
P14
P13
P12
DTMF
RST
MOD0
MOD1
X0
X1
VCC
X0A
X1A
P27
P26
P25
(FPT-48P-M16)
48
47
46
45
44
43
42
41
40
39
38
37
P40
P41
P42
P43
P44
VSS
P30/SCK
P31/SO
P32/SI
P33/EC
P34/TO/INT0
P35/INT1
(TOP VIEW)
MB89170L series
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
P24
P23
P22
P21
P20
P17
VSS
P16
P15
P14
P13
P12
N.C.
RST
MOD0
MOD1
X0
X1
VCC
N.C.
N.C.
P27
P26
P25
(FPT-48P-M16)
6
MB89170/170A/170L Series
60
59
58
57
56
55
54
53
77
78
79
80
49
50
51
52
69
70
71
72
73
74
75
76
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
P36/INT2
P37/BZ
P00/INT20
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10
P11
P24
P23
P22
P21
P20
P17
VSS
P16
P15
P14
P13
P12
DTMF
RST
MOD0
MOD1
X0
X1
VCC
X0A
X1A
P27
P26
P25
68
67
66
65
64
63
62
61
48
47
46
45
44
43
42
41
40
39
38
37
P40
P41
P42
P43
P44
VSS
P30/SCK
P31/SO
P32/SI
P33/EC
P34/TO/INT0
P35/INT1
(Top view)
(MQP-48C-P01)
• Pin assignment on package top (MB89PV170A only)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
49
VPP
57
N.C.
65
O4
73
OE
50
A12
58
A2
66
O5
74
N.C.
51
A7
59
A1
67
O6
75
A11
52
A6
60
A0
68
O7
76
A9
53
A5
61
O1
69
O8
77
A8
54
A4
62
O2
70
CE
78
A13
55
A3
63
O3
71
A10
79
A14
56
N.C.
64
VSS
72
N.C.
80
VCC
N.C.: Internally connected. Do not use.
7
MB89170/170A/170L Series
■ PIN DESCRIPTION
Pin no.
Pin name
QFP*1
MQFP*2
5
X0
6
X1
8
X0A
9
X1A
3
MOD0
4
MOD1
2
Function
A
Main clock crystal oscillator pins
B
Subclock oscillation pins (32.768 kHz)
C
Operation mode selecting pins
Connect directly to VCC or VSS.
RST
D
Reset I/O pin
This pin is of an N-ch open-drain output type with pull-up
resistor and of hysteresis input type.
“L” is output from this pin by an internal reset source (optional
function).
The internal circuit is initialized by the input of “L”.
P00/INT20 to
P07/INT27
E
General-purpose I/O ports
Also serve as an external interrupt 2 input (wake-up function).
External interrupt input is a hysteresis input.
F
General-purpose I/O ports
P20 to P27
H
General-purpose output ports
42
P30/SCK
G
General-purpose I/O port
Also serves as the clock I/O for the 8-bit serial I/O.
This port is of hysteresis input type.
41
P31/SO
G
General-purpose I/O port
Also serves as the data output for the 8-bit serial I/O.
This port is of hysteresis input type.
40
P32/SI
G
General-purpose I/O port
Also serves as the data input for the 8-bit serial I/O.
This port is of hysteresis input type.
39
P33/EC
G
General-purpose I/O port
Also serves as an external clock input for a 8-bit timer/
counter.
This port is of hysteresis input type.
38
P34/TO/INT0
G
General-purpose I/O port
Also serves as the overflow output for the 8-bit timer/counter
and an external interrupt 1 input.
This port is of hysteresis input type.
36,
37
P36/INT2,
P35/INT1
G
General-purpose I/O ports
Also serve as an external interrupt 1 input.
These ports are of hysteresis input type.
34 to 27
26 to 20, 18 P10 to P17
17 to 10
*1: FPT-48P-M16
*2: MQP-48C-P01
Notes:
8
Circuit type
(Continued)
On the MB89170L series, DTMF pin (Pin No.:1), X0A pin (Pin No.:8) and X1A pin (Pin No.:9) are N.C. pins.
Please connect them with GND.
MB89170/170A/170L Series
(Continued)
Pin no.
Pin name
QFP*1
MQFP*2
35
Circuit type
Function
P37/BZ
G
General-purpose I/O port
Also serves as a buzzer output.
This port is of hysteresis input type.
P40 to P44
I
N-ch open-drain output ports
1
DTMF
J
DTMF signal output pin
7
VCC
—
Power supply pin
19, 43
VSS
—
Power supply (GND) pin
48 to 44
*1: FPT-48P-M16
*2: MQP-48C-P01
Notes:
On the MB89170L series, DTMF pin (Pin No.:1), X0A pin (Pin No.:8) and X1A pin (Pin No.:9) are N.C. pins.
9
MB89170/170A/170L Series
• External EPROM pins (the MB89PV170A only)
Pin no.
Pin name
MQFP*
Function
49
VPP
O
“H” level output pin
50
51
52
53
54
55
58
59
60
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
61
62
63
O1
O2
O3
I
Data input pins
64
VSS
O
Power supply (GND) pin
65
66
67
68
69
O4
O5
O6
O7
O8
I
Data input pins
70
CE
O
ROM chip enable pin
Outputs “H” during standby.
71
A10
O
Address output pin
73
OE
O
ROM output enable pin
Outputs “L” at all times.
75
76
77
78
79
A11
A9
A8
A13
A14
O
Address output pins
80
VCC
O
EPROM power supply pin
56
57
72
74
N.C.
—
Internally connected pin
Be sure to leave them open.
* : MQP-48C-P01
10
I/O
MB89170/170A/170L Series
■ I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
Main clock
• Oscillation feedback resistor of approximately
1 MΩ/5 V
X1
X0
Standby control signal
B
Subclock
• Oscillation feedback resistor of approximately
4.5 MΩ/5 V
• When single clock mode is selected, the switch is
open.
X1A
X0A
Standby control signal
C
D
• Output pull-up resistor (P-ch) of approximately
50 kΩ/5 V
• Hysteresis input
R
P-ch
N-ch
E
• CMOS output
• CMOS input
• Hysteresis input
R
P-ch
P-ch
N-ch
Port
Resource
• Pull-up resistor optional
(Continued)
11
MB89170/170A/170L Series
(Continued)
Type
Circuit
Remarks
F
• CMOS output
• CMOS input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
G
• CMOS output
• Hysteresis input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
H
• CMOS output
P-ch
N-ch
I
• N-ch open-drain output
R
P-ch
N-ch
• Pull-up resistor optional
J
• DTMF analog output
OPAMP
12
MB89170/170A/170L Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in “■ Electrical Characteristics” is applied between VCC to VSS.
When latchup occurs, power supply current increases rapidly and might thermally damaged elements. When
using, take great care not to exceed the absolute maximum ratings.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
registor.
3. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
4. Power Supply Voltage Fluctuations
Although operating is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the
voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC
is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple
fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60
Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as
when power is switched.
5. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and
wake-up from stop mode.
6. Turning on the supply voltage (only for the MB89P175A)
Power on sharply up to the option enabling voltage (2 V) within 13 clock cycles after starting of oscillation.
13
MB89170/170A/170L Series
■ PROGRAMMING TO THE EPROM ON THE MB89P173 AND MB89P175A
The MB89P173 is an OTPROM (one-time PROM) versions of the MB89170/170L series, and the MB89P175A
is of the MB89170A/170L series.
1. Features
• 8-Kbyte (MB89P173), 16-Kbyte (MB89P175A) PROM on chip
• Options can be set using the EPROM programmer (MB89P175A only).
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in each mode such as 8-Kbyte PROM,16-Kbyte PROM and option area is diagrammed below.
MB89P175A
MB89P173
Address
Single chip
0000 H
EPROM mode
(Corresponding addresses
on the EPROM programmer)
Address
Single chip
0000 H
I/O
EPROM mode
(Corresponding addresses
on the EPROM programmer)
I/O
0080 H
0080 H
RAM
RAM
0200 H
0280 H
Not available
8000 H
Not available
8000 H
0000 H
0000 H
Vacancy
(Read value
FF H)
Not available
BFF0 H
Vacancy
(Read value
FF H)
Not available
3FF0 H
Not available
BFF6 H
Option area
3FF6 H
Vacancy
(Read value
FF H)
Not available
C000 H
E000 H
6000 H
FFFF H
14
PROM
16 KB
EPROM
8 KB
PROM
8 KB
7FFF H
4000 H
FFFF H
EPROM
16 KB
7FFF H
MB89170/170A/170L Series
3. Programming to the EPROM
In EPROM mode, the MB89P173 and MB89P175A functions equivalent to the MBM27C256A. This allows the
PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot
be used) by using the dedicated socket adapter.
• Programming procedure (MB89P173)
(1) Set the EPROM programmer for the MBM27C256A.
(2) Load program data into the EPROM programmer at 6000H to 7FFFH (note that addresses E000H to 0FFFFH
while operating as a single chip correspond to 6000H to 7FFFH in EPROM mode).
(3) Program the data to the EPROM with the EPROM programmer.
• Programming procedure (MB89P175A)
(1) Set the EPROM programmer for the MBM27C256A.
(2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to 0FFFFH
while operating as a single chip assign to 4000H to 7FFFH in EPROM mode).
Load option data into addresses 3FF0H to 3FF6H of the EPROM programmer. (For information about each
corresponding option, see “7. Setting OTPROM Options (MB89P175A Only).”)
(3) Program the data to the EPROM with the EPROM programmer.
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+ 150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test. For this reason, a programming
yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Part number
MB89P175A
Package
QFP-48P
Compatible socket adapter
Sun Hayato Co., Ltd.
ROM-48QF-28DP-8L
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403
FAX (81)-3-5396-9106
15
MB89170/170A/170L Series
7. Setting OTPROM Options (MB89P175A Only)
The programming procedure is the same as that for the PROM. Options can be set by programming values at
the addresses shown on the memory map. The relationship between bits and options is shown on the following
bit map:
• OTPROM option bit map
Addre
ss
Bit 7
Bit 6
Bit 5
Vacancy
Vacancy
Vacancy
Bit 4
Bit 3
Bit 2
Bit 1
3FF0H
Clock mode
select
Readable
Readable
Readable
1: 1 clock
and writable and writable and writable 0: 2 clocks
Reset pin
output
1: Yes
0: No
Power-on
reset
1: Yes
0: No
00 23/FCH
01 212/FCH
10 216/FCH
11 218/FCH
3FF1H
P07
Pull-up
1: Yes
0: No
P06
Pull-up
1: Yes
0: No
P05
Pull-up
1: Yes
0: No
P04
Pull-up
1: Yes
0: No
P03
Pull-up
1: Yes
0: No
P02
Pull-up
1: Yes
0: No
P01
Pull-up
1: Yes
0: No
P00
Pull-up
1: Yes
0: No
3FF2H
P17
Pull-up
1: Yes
0: No
P16
Pull-up
1: Yes
0: No
P15
Pull-up
1: Yes
0: No
P14
Pull-up
1: Yes
0: No
P13
Pull-up
1: Yes
0: No
P12
Pull-up
1: Yes
0: No
P11
Pull-up
1: Yes
0: No
P10
Pull-up
1: Yes
0: No
3FF3H
P37
Pull-up
1: Yes
0: No
P36
Pull-up
1: Yes
0: No
P35
Pull-up
1: Yes
0: No
P34
Pull-up
1: Yes
0: No
P33
Pull-up
1: Yes
0: No
P32
Pull-up
1: Yes
0: No
P31
Pull-up
1: Yes
0: No
P30
Pull-up
1: Yes
0: No
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
3FF4H
3FF5H
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
and writable and writable and writable and writable and writable and writable and writable and writable
Vacancy
3FF6H
Oscillation stabilization time
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
and writable and writable and writable and writable and writable and writable and writable and writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
and writable and writable and writable and writable and writable and writable and writable and writable
Note: Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is selected.
16
Bit 0
MB89170/170A/170L Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TVM
2. Programming Socket Adapter
To program to the EPROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Socket adapter part number
LCC-32(Square)
ROM-32LC-28DP-S
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403
FAX (81)-3-5396-9106
3. Memory Space
Memory space in each mode, such as 32-Kbyte EPROM, is diagrammed below.
Address
Single chip
Corresponding address on the EPROM programmer
0000 H
I/O
0080 H
RAM
0480 H
Not available
0000 H
8000 H
EPROM
32 KB
PROM
32 KB
FFFF H
7FFF H
4. Programming to the EPROM
(1) Set the EPROM programmer for the MBM27C256A.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH.
(3) Program with the EPROM programmer.
17
MB89170/170A/170L Series
■ BLOCK DIAGRAM
1. MB89170/170A series
Main clock
oscillator
X0
X1
Timebase timer
Clock controller
Watch prescalar
X0A
X1A
Subclock oscillator
RST
Reset circuit
CMOS I/O port
16-bit timer/counter
P10 to P17
External interrupt 2
(wake-up)
8-bit timer/counter
P34/TO/INT0
8-bit timer/counter
P33/EC
8-bit serial I/O
P20 to P27
P30/SCK
P32/SI
P31/SO
P35/INT1
Port 2
8
Port 3
8
Internal bus
8
P00/INT20
to P07/INT27
Port 0 and Port 1
CMOS I/O ports
External interrupt 1
P36/INT2
P37/BZ
Buzzer output
CMOS output port
N-ch open-drain output port
Port 4
RAM
F2MC-8L
CPU
ROM
The other pins
MOD1, MOD0, VCC, VSS × 2
18
DTMF generator
5
P40 to P44
DTMF
MB89170/170A/170L Series
2. MB89170L series
Main clock
oscillator
X0
X1
Timebase timer
Clock controller
RST
Reset circuit
(Watch dog timer)
CMOS I/O port
16-bit timer/counter
P10 to P17
External interrupt 2
(wake-up)
8-bit timer/counter
P34/TO/INT0
8-bit timer/counter
P33/EC
8-bit serial I/O
P20 to P27
P30/SCK
P32/SI
P31/SO
P35/INT1
Port 2
8
Port 3
8
Internal bus
8
P00/INT20
to P07/INT27
Port 0 and Port 1
CMOS I/O ports
External interrupt 1
P36/INT2
P37/BZ
Buzzer output
CMOS output port
N-ch open-drain output port
F2MC-8L
CPU
Port 4
RAM
5
P40 to P44
ROM
The other pins
MOD1, MOD0, VCC, VSS × 2, N.C. × 2
19
MB89170/170A/170L Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89170/170A/170L series offer 64 Kbytes of memory for storing all of I/O, data,
and program areas. The I/O area is allocated from the lowest address. The data area is allocated immediately
above the I/O area. The data area can be divided into register, stack, and direct areas according to the application.
The program area is allocated from exactly the opposite end of I/O area, that is, near the highest address. The
tables of interrupt reset vectors and vector call instructions are allocated from the highest address within the
program area. The memory space of the MB89170/170A/170L series is structured as illustrated below.
Memory Space
MB89PV170A
0000 H
MB89P175A
0000 H
0000 H
I/O
0080 H
0000 H
I/O
0080 H
MB89P173
MB89173L
MB89173
MB89174A
MB89174L
I/O
0080 H
I/O
0080 H
RAM
RAM
RAM
RAM
1 KB
512 B
512 B
384 B
0100 H
0100 H
Register
0200 H
0100 H
Register
0100 H
Register
0200 H
0200 H
0280 H
0280 H
Register
0200 H
0480 H
Not available
Not available
8000 H
Not available
Not available
C000 H
External ROM
32 KB
D000 H
ROM
ROM
16 KB
E000 H
ROM
12 KB
8 KB
FFFF H
20
FFFF H
FFFF H
FFFF H
MB89170/170A/170L Series
2. Registers
The F2MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose
memory registers. The following dedicated registers are provided:
Program counter (PC):
A 16-bit register for indicating the instruction storage positions
Accumulator (A):
A 16-bit temporary register for arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A 16-bit register which is used for arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX):
A 16-bit register for index modification
Extra pointer (EP) :
A 16-bit pointer for indicating a memory address
Stack pointer (SP) :
A 16-bit pointer for indicating a stack area
Progam status (PS) :
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
FFFDH
: Program counter
PC
A
: Accumulator
T
: Temporary accumulator Indeterminate
IX
: Index register
Indeterminate
EP
: Extra pointer
Indeterminate
SP
: Stack pointer
Indeterminate
PS
: Program status
Indeterminate
I-flag = 0, IL1, 0 = 11
The other bit values are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
11
10
9
8
Vacancy Vacancy Vacancy
RP
RP
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
21
MB89170/170A/170L Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of arithmetic operation. Cleared
to ‘0’ otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared
to ‘0’ at the reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low
N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise.
Z-flag:
Set to ‘1’ when an arithmetic operation results in ‘0’. Cleared to ‘0’ otherwise.
V-flag:
Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the
overflow does not occur.
C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to
‘0’ otherwise. Set to the shift-out value in the case of a shift instruction.
22
MB89170/170A/170L Series
The following general-purpose registers are provided:
General-purpose register: An 8-bit register for storing data
The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used on the MB89170/170A/170L series . The bank currently
in use is indicated by the register bank pointer(RP).
Register Bank Configuraiton
This address = 0100 H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
} 32 banks
Memory area
23
MB89170/170A/170L Series
■ I/O MAP
1. MB89170/170A series
Address
Read/write
Register name
Register description
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
(R/W)
PDR1
Port 1 data register
03H
(W)
DDR1
Port 1 data direction register
04H
(R/W)
PDR2
Port 2 data register
05H
Vacancy
06H
Vacancy
07H
(R/W)
SYCC
System clock control register
08H
(R/W)
STBC
Standby control register
09H
(R/W)
WDTC
Watchdog control register
0AH
(R/W)
TBTC
Timebase timer control register
0BH
(R/W)
WPCR
Watch prescaler control register
0CH
(R/W)
PDR3
Port 3 data register
0DH
(R/W)
DDR3
Port 3 data direction register
0EH
(R/W)
PDR4
Port 4 data register
0FH
(R/W)
BZCR
Buzzer register
10H
Vacancy
11H
Vacancy
12H
Vacancy
13H
Vacancy
14H
Vacancy
15H
Vacancy
16H
Vacancy
17H
Vacancy
18H
(R/W)
T2CR
Timer 2 control register
19H
(R/W)
T1CR
Timer 1 control register
1AH
(R/W)
T2DR
Timer 2 data register
1BH
(R/W)
T1DR
Timer 1 data register
1CH
(R/W)
SMR
Serial mode register
1DH
(R/W)
SDR
Serial data register
1EH
Vacancy
1FH
Vacancy
(Continued)
24
MB89170/170A/170L Series
(Continued)
Address
Read/write *
Register name
20H
(R/W)
DTMC
DTMF control register
21H
(R/W)
DTMD
DTMF data register
22H
Register description
Vacancy
23H
(R/W)
EIC1
External interrupt control register 1
24H
(R/W)
EIC2
External interrupt control register 2
25H to 31H
Vacancy
32H
(R/W)
EIE2
External interrupt 2 enable register
33H
(R/W)
EIF2
External interrupt 2 flag register
34H to 7BH
Vacancy
7CH
(W)
ILR1
Interrupt level setting register 1
7DH
(W)
ILR2
Interrupt level setting register 2
7EH
(W)
ILR3
Interrupt level setting register 3
7FH
Vacancy
* R/W: Readable and writable
R:
Read only
W: Write only
Note: Do not use vacancies.
25
MB89170/170A/170L Series
2. MB89170L series
Address
Read/write
Register name
Register description
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
(R/W)
PDR1
Port 1 data register
03H
(W)
DDR1
Port 1 data direction register
04H
(R/W)
PDR2
Port 2 data register
05H
Vacancy
06H
Vacancy
07H
(R/W)
SYCC
System clock control register
08H
(R/W)
STBC
Standby control register
09H
(R/W)
WDTC
Watchdog control register
0AH
(R/W)
TBTC
Timebase timer control register
0BH
Vacancy
0CH
(R/W)
PDR3
Port 3 data register
0DH
(R/W)
DDR3
Port 3 data direction register
0EH
(R/W)
PDR4
Port 4 data register
0FH
(R/W)
BZCR
Buzzer register
10H
Vacancy
11H
Vacancy
12H
Vacancy
13H
Vacancy
14H
Vacancy
15H
Vacancy
16H
Vacancy
17H
Vacancy
18H
(R/W)
T2CR
Timer 2 control register
19H
(R/W)
T1CR
Timer 1 control register
1AH
(R/W)
T2DR
Timer 2 data register
1BH
(R/W)
T1DR
Timer 1 data register
1CH
(R/W)
SMR
Serial mode register
1DH
(R/W)
SDR
Serial data register
1EH
Vacancy
1FH
Vacancy
(Continued)
26
MB89170/170A/170L Series
(Continued)
Address
Read/write *
Register name
Register description
20H
Vacancy
21H
Vacancy
22H
Vacancy
23H
(R/W)
EIC1
External interrupt control register 1
24H
(R/W)
EIC2
External interrupt control register 2
25H to 31H
Vacancy
32H
(R/W)
EIE2
External interrupt 2 enable register
33H
(R/W)
EIF2
External interrupt 2 flag register
34H to 7BH
Vacancy
7CH
(W)
ILR1
Interrupt level setting register 1
7DH
(W)
ILR2
Interrupt level setting register 2
7EH
(W)
ILR3
Interrupt level setting register 3
7FH
Vacancy
* R/W: Readable and writable
R:
Read only
W: Write only
Note: Do not use vacancies.
As for MB89170L series, WPCR register(0BH), DTMC register(20H) and DTMD register(21H) become Vacancy.
27
MB89170/170A/170L Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = 0.0 V)
Parameter
Power supply voltage
Input voltage
Symbol
Unit
Remarks
Min.
Max.
VCC
VSS – 0.3
VSS + 7.0
V
VI
VSS – 0.3
VCC + 0.3
V
Except P40 to P44
VSS – 0.3
VCC + 0.3
V
P40 to P44
(with pull-up option)
VSS – 0.3
VSS + 7.0
V
P40 to P44
(without pull-up option)
VSS – 0.3
VCC + 0.3
V
Except P40 to P44
VSS – 0.3
VCC + 0.3
V
P40 to P44
(with pull-up option)
VSS – 0.3
VSS + 7.0
V
P40 to P44
(without pull-up option)
VI2
VO
Output voltage
Value
VO2
“L” level maximum output
current
IOL

10
mA
“L” level average output current
IOLAV

4
mA
“L” level total maximum output
current
ΣIOL

100
mA
“L” level total average output
current
ΣIOLAV

20
mA
“H” level maximum output
current
IOH

–10
mA
“H” level average output current
IOHAV

–2
mA
“H” level total maximum output
current
ΣIOH

–25
mA
“H” level total average output
current
ΣIOHAV

–10
mA
Power consumption
PD

200
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
Average value (operating
current × operating rate)
Average value (operating
current × operating rate)
Average value (operating
current × operating rate)
Average value (operating
current × operating rate)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
28
MB89170/170A/170L Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Power supply voltage
Operating temperature
Symbol
VCC
TA
Value
Unit
Remarks
Min.
Max.
2.2*
6.0*
V
Normal operation assurance range*
MB89174A/173/174L/173L
2.7*
6.0*
V
Normal operation assurance range*
MB89PV170A/P175A/P173
1.5
6.0
V
Retains the RAM state in the stop
mode
–40
+85
°C
* : These values vary with the operating frequency, instruction cycle, and the assurance range for the DTMF generator. See Figure 1 and “(7) Electrical Characteristics of DTMF Generator” in “4. AC characteristics.”
Figure 1 Operating Voltage vs. Main Clock Operating Frequency(MB89170/170A series)
6
5
Operating assurance range
Assurance range
for DTMF generator
Operating voltage (V)
4
3
2
1
1.0
2.0
3.0
4.0
5.0
6.0
Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz)
7.0
8.0
4.0
2.0
1.33
1.0
Minimum execution time (instruction cycle) (µs)
0.57
0.5
0.8
0.67
Note: The shaded area is assured only for the MB89170A series.
29
MB89170/170A/170L Series
Figure 2 Operating Voltage vs. Main Clock Operating Frequency(MB89170L series)
6
5
Operating assurance range
Operating voltage (V)
4
3
2
1
1.0
2.0
3.0
4.0
5.0
6.0
Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz)
7.0
8.0
4.0
2.0
1.33
1.0
Minimum execution time (instruction cycle) (µs)
0.57
0.5
0.8
0.67
Figure 1 and figure 2 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
30
MB89170/170A/170L Series
3. DC Characteristics
Parameter
Symbol
Pin name
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Typ.
Max.
VIH
P00 to P07,
P10 to P17
0.7 VCC

VCC +
0.3
V
VIHS
RST,
MOD0, MOD1,
P30 to P37,
INT20 to INT27
0.8 VCC

VCC +
0.3
V
VIL
P00 to P07,
PI0 to PI7
VSS −
0.3

0.3 VCC
V
VILS
RST,
MOD0, MOD1,
P30 to P37,
INT20 to INT27
VSS −
0.3

0.2 VCC
V
Open-drain output
VD
pin applied voltage
P40 to P44
VSS −
0.3

VSS +
6.0
V
“H” level output
voltage
VOH
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37
IOH = –2.0 mA
2.4


V
VOL1
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P44
IOL = 1.8 mA


0.4
V
VOL2
RST
IOL = 4.0 mA


0.6
V
ILI1
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P44,
MOD0, MOD1
0.0 V < VI < VCC


±5
µA
Without pullup resistor
P00 to P07,
P10 to P17,
P30 to P37,
P40 to P44,
RST
VI = 0.0 V
25
50
100
kΩ
With pull-up
resistor
“H” level input
voltage
“L” level input
voltage
“L” level output
voltage
Input leakage
current (Hi-z
output leakage
current)
Pull-up resistance RPULL

(Continued)
31
MB89170/170A/170L Series
(Continued)
Parameter
Symbol
ICC
ICCS1
ICCS2
Pin name
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Typ.
Max.
VCC = 5.0 V
FCH = 3.58 MHz
• Main clock
operation
mode
• Highest gear
speed
VCC = 5.0 V
FCH = 3.58 MHz
• Main clock
sleep mode
• Highest gear
speed
VCC = 3.0 V
FCL = 32.768
kHz
VCC
• Subclock
(when DTMF is
sleep
not operating)
mode
ICCH
TA = +25°C
• Subclock stop
mode
• Main clock
stop mode in
single clock
system
ICSB
VCC = 3.0 V
FCL = 32.768
kHz
• Subclock
operation
mode
Power supply
voltage*
ICCT
ID
Input capacitance CIN
VCC = 3.0 V
• Watch mode
VCC = 5.0 V
FCH = 3.58 MHz
• Main clock
VCC
(when DTMF is
operation
operating)
mode
• Highest gear
speed
Other than VCC,
f = 1 MHz
VSS
* : The power supply current is measured at the external clock.
32
—
3.5
8
MB89173/
mA 174A/173L/
174L
—
6.5
10
mA
—
2
5
mA
—
25
50
µA
—
—
1
µA
—
50
100
µA
MB89173/
174A
—
1
3
mA
MB89P173/
P175A
—
—
15
µA
—
5.5
10
mA
MB89173/
174A
—
8.5
13
mA
MB89P173/
P175A
—
10
—
pF
MB89P173/
P175A
MB89170/170A/170L Series
4. AC Characteristics
(1) Reset Timing
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
Symbol
Parameter
RST “L” pulse width
tZLZH
—
48 tHCYL
—
ns
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition
—
Value
Unit
Remarks
Min.
Max.
—
50
ms
Power-on reset function only
1
—
ms
Due to repeated operations
Note: Make sure that power supply rises within the oscillation stabilization time selected.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
tR
tOFF
2.0 V
VCC
0.2 V
0.2 V
0.2 V
33
MB89170/170A/170L Series
(3) Clock Timing
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Clock frequency
Symbol
FCH
Input clock pulse
width
Input clock rising/
falling time
Condition
Min.
Typ.
Max.
1
—
3.58
Unit
X0A, X1A
tHCYL
X0, X1
—
MB89173/
P173
1
—
7.16
MHz
MB89174A/
P175A/
PV170A/
173L/174L
—
32.768
—
kHz
Subclock
280
—
1000
ns
MB89173/
P173
140
—
1000
ns
MB89174A/
P175A/
PV170A/
173L/174L
tLCYL
X0A, X1A
—
30.5
—
µs
Subclock
PWH
PWL
X0
20
—
—
ns
External clock
PWHL
PWLL
X0A
—
15.2
—
µs
External clock
tCR
tCF
X0, X0A
—
—
10
ns
External clock
• Main Clock Timing Condition
tHCYL
PWH
PWL
tCR
X0
tCF
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Main Clock Configurations
When a crystal
or
ceramic resonator is used
X0
X1
When an external clock is used
X0
X1
Open
34
Remarks
MHz
X0, X1
FCL
Clock cycle time
Pin name
Value
MB89170/170A/170L Series
• Subclock Timing Condition
tLCYL
PWHL
PWLL
tCR
0.8 VCC
X0A
tCF
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Subclock Configurations
When a crystal
or
ceramic resonator is used
X0A
X1A
When an external clock is used
X0A
X1A
When a single clock option is used
X0A
X1A
Open
(4) Instruction Cycle
Parameter
Instruction cycle
(minimum execution time)
Symbol
Value (typical)
Unit
Remarks
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
(4/FC) tinst = 1.1 µs when operating at
FC = 3.58 MHz
2/FCL
µs
tinst = 61.036 µs when operating at FCL
= 32.768 kHz
(MB89170/170A series only)
tinst
35
MB89170/170A/170L Series
(5) Recommend Resonator Manufacturers
• Sample Application of Piezoelectric Resonator (FAR Family)
(MB89170 series only)
X0
X1
FAR*1
C1*2
C2*2
*1: Fujitsu Acoustic Resonator
FAR part number
(built-in capacitor type)
Frequency
(MHz)
Initial deviation of FAR
frequency
(TA = +25°C)
Temperature
characteristics of
FAR frequency
(TA = –20°C+60°C)
Loading
capacitors*2
FAR-C4 A-03580- 01
3.58
±0.5%
±0.5%
Built-in
Inquiry: FUJITSU LIMITED
(6) Serial I/O Timing
(VCC = +5.0 V±10%, VSS= 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
Internal shift
clock mode
SCK
External shift
clock mode
Value
Unit
Min.
Max.
2 tinst*
—
µs
–200
200
ns
0.5 tinst*
—
µs
0.5 tinst*
—
µs
1 tinst*
—
µs
1 tinst*
—
µs
0
200
ns
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
0.5 tinst*
—
µs
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
0.5 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycle.”
36
Condition
Remarks
MB89170/170A/170L Series
• Internal Shift Clock Mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
SI
• External Shift Clock Mode
tSLSH
tSHSL
SCK
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
SO
0.8 V
tIVSH
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
SI
37
MB89170/170A/170L Series
(7) Peripheral Input Timing
(VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name
Unit Remarks
Min.
Max.
Symbol
Parameter
Peripheral input “H” pulse width 1
tILIH1
Peripheral input “L” pulse width 1
tIHIL1
EC, INT0 to INT2,
INT20 to INT27
2 tinst*
—
µs
2 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL1
tILIH1
0.8 VCC
EC
INT0 to INT2
INT20 to INT27
0.8 VCC
0.2 VCC
0.2 VCC
(8) Electrical Characteristics of DTMF Generator
Parameter
Symbol
Operating voltage
range
Output load
requirements
—
Condition
(VSS = 0.0 V, FCH = 3.579545 MHz, TA = –30°C to + 60°C)
Value
Unit
Remarks
Min. Typ. Max.
3.0
—
6.0
V
MB89P173
2.4
—
6.0
V
MB89173/174A
2.7
—
6.0
V
MB89P175A
VCC = 4.5 V to 6.0 V
30
—
—
kΩ
VCC = 3.0 V to 4.5 V
200
—
—
kΩ
Defined when the DTMF
pin is connected to a pulldown resistor for the
MB89P173.
—
RO
VCC = 2.4 V to 6 V
30
—
—
kΩ
VCC = 2.7 V to 6 V
DTMF output offset
voltage (at signal
output)
VMOF
DTMF output
amplitude (COL
single tone)
VMFOC
DTMF output
amplitude (ROW
single tone)
VMFOR
Difference between
RMF
COL and ROW levels
38
Defined when the DTMF
pin is connected to a pulldown resistor for the
MB89173/174A
MB89P175A
—
2.4
—
V
When the DTMF pin is
open for MB89P173.
—
0.6
—
V
When the DTMF pin is
open for the MB89173/
174A/P175A.
VCC = 5.0 V
450
530
600
mVP-P
VCC = 5.0 V
350
420
480
mVP-P
—
1.6
2.0
2.4
dB
VCC = 5.0 V
When DTMF pin is open.
MB89170/170A/170L Series
■ EXAMPLE CHARACTERISTICS
(2) “H” Level Output Voltage
(1) “L” Level Output Voltage
VOL vs. IOL
VCC – VOH vs. IOH
VCC = 2.5 V
VCC = 2.2 V
VCC = 3.0 V
VOL (V)
1.1
1.0 TA = +25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
1 2 3
VCC – VOH (V)
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
4 5 6
IOL (mA)
7
8
9
10
(3) “H” Level Input Voltage/“L”ow Level Input
Voltage (CMOS Input)
1.1
1.0 TA = +25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0
–0.5 –1.0
VCC = 2.2 V
VCC = 2.5 V
VCC = 3.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
–1.5 –2.0
IOH (mA)
–2.5
–3.0
(4) “H” Level Input Voltage/“L” Level Input
Voltage (Hysteresis Input)
VIN vs. VCC
VIN (V)
5.0
4.5
TA = +25°C
4.0
VIHS
3.5
3.0
2.5
2.0
VILS
1.5
1.0
0.5
0
0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00
VCC (V)
VIN vs. VCC
VIN (V)
5.0
4.5
4.0
TA = +25°C
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.00
VIHS :
1.00
2.00
3.00 4.00
VCC (V)
5.00
6.00
7.00
VILS :
Threshold when input voltage in hysteresis characteristics
is set to “H” level
Threshold when input voltage in hysteresis characteristics
is set to “L” level
39
MB89170/170A/170L Series
(5) Power Supply Current
I D vs. V CC
I CC vs. V CC
I D (mA)
6
F CH = 3.58 MHz
5 T A = +25°C
I CC (mA)
6
F CH = 3.58 MHz
5 T A = +25°C
Divide-by-4 (I D)
Divide-by-4 (I CC)
3
Divide-by-8
3
Divide-by-16
Divide-by-64
2
2
1
1
0
1
2
3
4
5
6
0
1
7
V CC (V)
(6) Pull-up Resistance
RPULL vs. VCC
RPULL (kΩ)
1000
TA = +25°C
300
100
50
10
0
1
2
3
4
VCC (V)
40
Divide-by-8
Divide-by-16
Divide-by-64
4
4
5
6
7
2
3
4
V CC (V)
5
6
7
MB89170/170A/170L Series
■ INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups:
•
•
•
•
Transfer
Arithmetic operation
Branch
Others
Table 1 lists symbols used for notation of instructions.
Table 1
Instruction Symbols
Symbol
Meaning
dir
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
#vct
Vector table number (3 bits)
#d8
Immediate data (8 bits)
#d16
Immediate data (16 bits)
dir: b
Bit direct address (8:3 bits)
rel
Branch relative address (8 bits)
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
AH
Upper 8 bits of accumulator A (8 bits)
AL
Lower 8 bits of accumulator A (8 bits)
T
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)
TH
Upper 8 bits of temporary accumulator T (8 bits)
TL
Lower 8 bits of temporary accumulator T (8 bits)
IX
Index register IX (16 bits)
EP
Extra pointer EP (16 bits)
PC
Program counter PC (16 bits)
SP
Stack pointer SP (16 bits)
PS
Program status PS (16 bits)
dr
Accumulator A or index register IX (16 bits)
CCR
Condition code register CCR (8 bits)
RP
Register bank pointer RP (5 bits)
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
×
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(×)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
41
MB89170/170A/170L Series
Columns indicate the following:
Mnemonic:
Assembler notation of an instruction
~:
The number of instructions
#:
The number of bytes
Operation:
Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
•
•
•
•
“–” indicates no change.
dH is the 8 upper bits of operation description data.
AL and AH must become the contents of AL and AH prior to the instruction executed.
00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
42
MB89170/170A/170L Series
Table 2
Transfer Instructions (48 instructions)
Mnemonic
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
43
MB89170/170A/170L Series
Table 3
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→ C→A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
D2
D0
01
11
63
73
53
12
13
03
C ← A←
–
–
–
++–+
02
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
(Continued)
44
MB89170/170A/170L Series
(Continued)
Mnemonic
~
#
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
Operation
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
Table 5
TL
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
45
L
46
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0
R0,#d8
R0,#d8
dir: 0 dir: 0,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1
R1,#d8
R1,#d8
dir: 1 dir: 1,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2
R2,#d8
R2,#d8
dir: 2 dir: 2,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3
R3,#d8
R3,#d8
dir: 3 dir: 3,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4
R4,#d8
R4,#d8
dir: 4 dir: 4,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5
R5,#d8
R5,#d8
dir: 5 dir: 5,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6
R6,#d8
R6,#d8
dir: 6 dir: 6,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7
R7,#d8
R7,#d8
dir: 7 dir: 7,rel
9
A
B
C
D
E
F
A
SUBC
A
XCH
A, T
XOR
A
AND
A
OR
A
MOV
MOV
CLRB
BBC
INCW
DECW
MOVW
MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
DAS
R7
R6
R5
R4
R3
R2
R1
R0
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
R7
R6
R5
R4
R3
R2
R1
R0
rel
rel
rel
rel
CALLV
BLT
#7
rel
CALLV
BGE
#6
rel
CALLV
BZ
#5
CALLV
BNZ
#4
rel
CALLV
BN
#3
CALLV
BP
#2
CALLV
BC
#1
CALLV
BNC
#0
rel
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
dir: 4 dir: 4,rel
A,ext
ext,A
A,#d16
A,PC
ADDCW SUBCW XCHW
XORW
ANDW
ORW
MOVW
MOVW
CLRB
BBC
INCW
DECW
MOVW
MOVW
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
ADDC
CLRB
BBC
INCW
DECW
MOVW
MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
8
A
A
SETC
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,@EP
A,@EP
A,@EP
A,@EP
@EP,A
A,@EP
A,@EP
A,@EP @EP,#d8 @EP,#d8
dir: 7 dir: 7,rel
A,@EP
@EP,A EP,#d16
A,EP
CMPW
CMP
JMP
CALL
PUSHW POPW
MOV
MOVW
CLRC
addr16
addr16
IX
IX
ext,A
PS,A
7
F
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8
dir: 6
dir: 6,rel A,@IX +d @IX +d,A
IX,#d16
A,IX
E
6
D
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir
dir,#d8
dir,#d8
dir: 5 dir: 5,rel
A,dir
dir,A SP,#d16
A,SP
C
5
B
CLRB
BBC
INCW
DECW
JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
A
MOV
CMP
ADDC
SUBC
A,#d8
A,#d8
A,#d8
A,#d8
A
A
DIVU
SETI
9
4
8
RORC
7
3
6
ROLC
A
5
PUSHW POPW
MOV
MOVW
CLRI
A
A
A,ext
A,PS
4
2
A
RETI
3
MULU
RET
2
1
SWAP
1
NOP
0
0
H
MB89170/170A/170L Series
■ INSTRUCTION MAP
MB89170/170A/170L Series
■ MASK OPTIONS
Part number
No.
Specifying procedure
MB89173L
MB89174L
MB89P173
MB89173
MB89174A
Specify when Specify when
ordering
ordering
masking
masking
MB89P173-201 MB89P175A MB89PV170A
Standard
option
product
Set with
EPROM
programmer
Setting not
possible
1
Pull-up resistors
• P00 to P07, P10 to P17
• P30 to P37, P40 to P44
Can be
selected per
pin
Can be
selected per
pin
Can be set
per pin
(However,
All ports
P40 to P44
Fixed to no pullare available
up resistor
only for no
pull-up
resistor.)
2
Power-on reset
• Power-on reset provided
• No power-on reset
Selectable
Selectable
Fixed to no
Setting
power-on reset
possible
option
Fixed to
power-on
reset option
3
Selection of oscillation
stabilization
time initial value (when
operating at
FCH = 3.58 MHz)
3: 218/FCH (approx. 73.2 ms)
2: 216/FCH (approx. 18.3 ms)
1: 212/FCH (approx. 1.1 ms)
0: 23/FCH (approx. 0 ms)
Selectable
Selectable
Fixed to 216/FCH
Setting
possible
Fixed to 218/
FCH
4
Reset pin output
• Reset output enabled
• Reset output disabled
Selectable
Selectable
Fixed to reset
output option
Setting
possible
Fixed to reset
output option
5
Clock mode selection
• Dual-clock mode
• Single-clock mode
Fixed to
single-clock
mode
Selectable
Fixed to dualclock mode
Setting
possible
Fixed to dualclock mode
All ports
Fixed to no
pull-up
resistor option
Note: Reset is input asynchronized with the internal clock whether power-on reset is provided or not.
■ ORDERING INFORMATION
Part number
MB89173PF
MB89174APF
MB89P173PF
MB89P175APF
MB89173LPF
MB89174LPF
MB89PV170ACF
Package
Remarks
48-pin Plastic QFP
(FPT-48P-M16)
48-pin Ceramic MQFP
(MQP-48C-P01)
47
MB89170/170A/170L Series
■ PACKAGE DIMENSION
48-pin Plastic QFP
(FPT-48P-M16)
17.20±0.40 SQ
(.677±.016)
+0.30
12.00 –0.10 SQ
2.70(.106)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
+.012
36
.472 –.004
25
37
Details of "A" part
24
0.15(.006)
8.80
(.346)
REF
13.60±0.40
(.535±.016)
0.20(.008)
0.15(.006)MAX
INDEX
0.50(.020)MAX
48
13
"A"
Details of "B" part
LEAD No.
1
0.80(.0315)TYP
12
+0.05
0.15 –0.01
0.30±0.06
(.012±.002)
0.16(.006)
"B"
+.002
M
.006 –.0004
0~10°
1.80±0.30
(.071±.012)
0.15(.006)
C
48
1994 FUJITSU LIMITED F48026S-1C-1
Dimensions in mm (inches)
MB89170/170A/170L Series
48-pin Ceramic MQFP
(MQP-48C-P01)
PIN No.1 INDEX
17.20(.677)TYP
15.00±0.25
(.591±.010)
14.82±0.35
(.583±.014)
1.50(.059)TYP
8.80(.346)REF
1.00(.040)TYP
0.80±0.22
(.0315±.0087)
PIN No.1 INDEX
1.02±0.13
(.040±.005)
+0.13
10.92 –0.0
+.005
.430 –0
7.14(.281) 8.71(.343)
TYP
TYP
PAD No.1 INDEX
0.30(.012)TYP
+0.45
4.50(.177)TYP
1.10 –0.25
+.018
.043 –.010
0.40±0.08
(.016±.003)
0.60(.024)TYP
8.50(.335)MAX
0.15±0.05
(.006±.002)
C
1994 FUJITSU LIMITED M48001SC-4-2
Dimensions in mm (inches)
49
MB89170/170A/170L Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F9910
 FUJITSU LIMITED Printed in Japan